Prosecution Insights
Last updated: October 01, 2026
Application No. 17/516,265

DISPLAY APPARATUS HAVING A BACKLIGHT UNIT

Non-Final OA §103
Filed
Nov 01, 2021
Priority
Nov 30, 2016 — RE 10-2016-0161006 +5 more
Examiner
MIYOSHI, JESSE Y
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Seoul Viosys Co., Ltd.
OA Round
7 (Non-Final)
57%
Grant Probability
Moderate
7-8
OA Rounds
0m
Est. Remaining
76%
With Interview

Examiner Intelligence

Grants 57% of resolved cases
57%
Career Allowance Rate
277 granted / 486 resolved
-11.0% vs TC avg
Strong +19% interview lift
Without
With
+18.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
35 currently pending
Career history
547
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
50.7%
+10.7% vs TC avg
§102
22.2%
-17.8% vs TC avg
§112
24.3%
-15.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 486 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/19/2026 has been entered. Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 filed 11/4/2025 have been considered but are not found persuasive. Applicant argues on pages 10-11 that first semiconductor layer 122 does not have an edge spaced apart from the edge of the substrate 110. This is not found persuasive since the rejection has been updated such that the first semiconductor layer is element 126 of Kim, therefore as can be seen in fig. 10 element 126 is spaced apart from the edge of 110. The rejection has been updated to include the amended portions of the claims. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-5, 7-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US PGPub 2013/0105845; hereinafter “Kim”) in view of Nagai (US PGPub 2011/0266579). Re claim 1: Kim teaches (e.g. figs. 9-11, 13-15, 17) a light emitting apparatus comprising: a diffusive cover (light guide plate 840; e.g. paragraph 137); a lighting module (830, 835; hereinafter “BU”) supplying light to the diffusive cover (840) and comprising: a first substrate (830/10); a plurality of light emitters (835) arranged in a first pattern on the first substrate (830/10); and a light guide (850, 860; hereinafter “LGS”) disposed on the first substrate (830/10); wherein the plurality of light emitters (835) includes: a second substrate (115, 110); a first cell (cell P2) and a second cell (cell P1), each of the first cell (P2) and the second cell (P1) comprising a first conductivity type semiconductor layer (126; e.g. paragraph 46), an active layer (124), and a second conductivity type semiconductor layer (122); an ohmic layer (130 can be ITO, Ni, Ag; e.g. paragraph 59) disposed on the second conductivity type semiconductor layer (122) of the second cell (P1) and configured to form an ohmic contact; a connector (260-1 between P1 and P2) electrically connecting the first cell (P2) and the second cell (P1) and including a first material (material of 260-1 is conductive; hereinafter “1M”), the connector (260-1) disposed on the second conductivity type semiconductor layer (122) of the first cell (P2) and the first conductivity type semiconductor layer (126) of the second cell (P1), and the connector (260-1) covering an isolation region (air gap formed in 120 to separate P1 and P2; hereinafter “IR”) that is disposed between the first cell (P2) and the second cell (P1); a first pad metal layer (portion of 260-2 over P1 which electrically contacts 126 as shown in fig. 9 and 10; hereinafter “1PML”) electrically connected to the first conductivity type semiconductor layer (126) of the first cell (P2) and including the first material (1M), the first pad metal layer (1PML) disposed over the first cell (P2) without being disposed on the second cell (P1) and spaced apart (upper portion is separated from the lower part of 260-1) from the connector (260-1); a second pad metal layer (272 over P1 as shown in fig. 9, 10; hereinafter “2PML”) electrically connected to the ohmic layer (130) of the second cell (P1); an upper insulation layer (140-2) at least partially disposed above the first and second pad metal layer (1PML, 2PML); and a first bump pad (50) and a second bump pad (40) each at least partially disposed above (40 and 50 extends to a level above a level of 1PML, 2PML) the first pad metal layer (1PML) and the second pad metal layer (2PML), respectively, wherein the upper insulation layer (140-2) and the first bump pad (50) are positioned adjacent to each other above (50 extends to a level above a level of 1PML) the first pad metal layer (1PML) in the first cell (P2), and the upper insulation layer (140-2) and the second bump pad (40) are positioned adjacent to each other above (40 extends to a level above a level of 2PML) the ohmic layer (130) in the second cell (P2), wherein the light guide (LGS) comprises a first light guide region (850) and a second light guide region (860), a first distance from a top surface of the first light guide region (850) to a top surface of one or more light emitters (835) is different from a second distance from a top surface of the second light guide region (860) to the top surface of the one or more light emitters (835), and wherein an edge of the first conductivity type semiconductor layer (126) is spaced apart from an edge (edge of 115, 110) of the second substrate (115, 110). Kim is silent as to explicitly teaching wherein a portion of the second substrate is exposed at the isolation region by the first conductivity type semiconductor layers of the first cell and the second cell and the portion of the second substrate directly contacts a lower insulation layer. Nagai teaches (e.g. figs. 6-9) a portion of the second substrate (110) is exposed at the isolation region (1000) by the first conductivity type semiconductor layers (114) of the first cell (left 112 of fig. 6, step C1) and the second cell (middle 112 of fig. 6, step C1) and the portion of the second substrate (110) directly contacts a lower insulation layer (140 of Nagai which is equivalent to 140-1 of Kim). Further, it can be considered that Nagai teaches the first and second bump pads 106 and 108 to be provided over the first and second cells. It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the isolation region structure as taught by Nagai in the device of Kim in order to have the predictable result of using a structure which more effectively isolated each cell such that leakage current between adjacent cells is more effectively reduced. Re claim 2: Kim teaches the light emitting apparatus of claim 1, wherein the upper insulation layer (140-2) further comprises a distributed Bragg reflector in which SiO2 and TiO2 are repeatedly stacked on each other (DBR can include different material layers such as an alternating stack of SiO2 and TiO2; e.g. paragraph 63). Re claim 3: Kim teaches the light emitting apparatus of claim 1, wherein the lower insulation layer (140-1) arranged between the second conductivity type semiconductor layer (126) of the first cell (1P) and the second cell (2P) and the upper insulation layer (140-2), and wherein the upper insulation layer (140-2) further comprises a first opening region (opening for 252; hereinafter “1OR”) and the lower insulation layer (140-1) includes a second opening region (opening for 272; hereinafter “2OR”), and the first opening region (1OR) does not overlap with the second opening region (2OR). Re claim 4: Kim teaches the light emitting apparatus of claim 3, wherein a portion of the lower insulation layer (140-1) contacting the ohmic layer (130) has a different thickness with a portion of the lower insulation layer (140-1) disposed around the ohmic layer (130). Re claim 5: Kim teaches the light emitting apparatus of claim 3, wherein: the plurality of light emitters (835) further comprise a second substrate (110); and an edge of the lower insulation layer (140-1) is farther to an edge of the second substrate (110) than an edge of the upper insulation layer is (140-2). Re claim 7: Kim teaches the light emitting apparatus of claim 1, wherein the light guide (LGS) further comprises a protrusion region (850 is provided with ridges and valleys). Re claim 8: Kim teaches (e.g. figs. 9-11, 13-15, 17) a light emitting apparatus comprising: a diffusive cover (light guide plate 840; e.g. paragraph 137); a lighting module (830, 835; hereinafter “BU”) supplying light to the diffusive cover (840) and comprising: a first substrate (830/10); a plurality of light emitters (835) arranged in a first pattern on the at least one first substrate (830/10); a light guide (110, 840, 850, 860; hereinafter “LGS”) disposed on the first substrate (830/10); wherein the plurality of light emitters (835) comprises: a second substrate (115); a first cell (cell P2) and a second cell (cell P1), each of the first cell (P2) and the second cell (P1) comprising a first conductivity type semiconductor layer (126; e.g. paragraph 46), an active layer (124), and a second conductivity type semiconductor layer (122); an ohmic layer (130 can be ITO, Ni, Ag; e.g. paragraph 59) disposed on the second conductivity type semiconductor layer (122) of the second cell (P1) and configured to form an ohmic contact; a connector (260-1 between P1 and P2) electrically connecting the first cell (P2) and the second cell (P1) and including a first material (material of 260-1 is conductive; hereinafter “1M”), the connector (260-1) disposed on the second conductivity type semiconductor layer (122) of the first cell (P2) and the first conductivity type semiconductor layer (126) of the second cell (P1), and the connector (260-1) covering an isolation region (air gap formed in 120 to separate P1 and P2; hereinafter “IR”) that is disposed between the first cell (P2) and the second cell (P1); a first pad metal layer (portion of 260-2 over P1 which electrically contacts 126 as shown in fig. 9 and 10; hereinafter “1PML”) electrically connected to the first conductivity type semiconductor layer (126) of the first cell (P2) and including the first material (1M), the first pad metal layer (1PML) disposed over the first cell (P2) without being disposed on the second cell (P1) and spaced apart (upper portion is separated from the lower part of 260-1) from the connector (260-1); a second pad metal layer (272 over P1 as shown in fig. 9, 10; hereinafter “2PML”) electrically connected to the ohmic layer (130) of the second cell (P1); an upper insulation layer (140-2) at least partially disposed above the first and second pad metal layer (1PML, 2PML); and a first bump pad (50) and a second bump pad (40) each at least partially disposed above (40 and 50 extends to a level above a level of 1PML, 2PML) the first pad metal layer (1PML) and the second pad metal layer (2PML), respectively, wherein the upper insulation layer (140-2) and the first bump pad (50) are positioned adjacent to each other above (50 extends to a level above a level of 1PML) the first pad metal layer (1PML) in the first cell (P2), and the upper insulation layer (140-2) and the second bump pad (40) are positioned adjacent to each other above (40 extends to a level above a level of 2PML) the ohmic layer (130) in the second cell (P2), wherein the light guide (LGS) comprises a first light guide (110, 850) and a second light guide (870, 820), and the first light guide (110, 850) comprises a protrusion region (850 is provided with ridges and valleys; e.g. paragraph 138), and wherein an edge of the first conductivity type semiconductor layer (126) is spaced apart from an edge (edge of 115, 110) of the second substrate (115, 110). Kim is silent as to explicitly teaching wherein a portion of the second substrate is exposed at the isolation region by the first conductivity type semiconductor layers of the first cell and the second cell and the portion of the second substrate contacts a lower insulation layer. Nagai teaches (e.g. figs. 6-9) a portion of the second substrate (110) is exposed at the isolation region (1000) by the first conductivity type semiconductor layers (114) of the first cell (left 112 of fig. 6, step C1) and the second cell (middle 112 of fig. 6, step C1) and the portion of the second substrate (110) contacts a lower insulation layer (140 of Nagai which is equivalent to 140-1 of Kim). Further, it can be considered that Nagai teaches the first and second bump pads 106 and 108 to be provided over the first and second cells. It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the isolation region structure as taught by Nagai in the device of Kim in order to have the predictable result of using a structure which more effectively isolated each cell such that leakage current between adjacent cells is more effectively reduced. Re claim 9: Kim teaches the light emitting apparatus of claim 8, wherein the first light guide structure (110) further comprises a lens (110 acts as a lens and disperses light) disposed on the plurality of light emitters (20, P1-P9) and configured to adjust uniformity of light. Re claim 10: Kim teaches the light emitting apparatus of claim 8, wherein the first light guide structure (110, 850) is configured to cover the plurality of light emitters (20, P1-P9) and configured to adjust uniformity of light. Re claim 11: Kim teaches the light emitting apparatus of claim 8, wherein the second light guide structure (870, 820) further comprises a plurality of reflective sheets (870, 820) and a light emitting element (835) is disposed between a pair of reflective sheets (870, 820). Re claim 12: Kim teaches (e.g. figs. 9-11, 13-15, 17) a light emitting apparatus comprising: a diffusive cover (light guide plate 840; e.g. paragraph 137); a lighting module (830, 835; hereinafter “BU”) supplying light to the diffusive cover (840) and comprising: a first substrate (830/10); a plurality of light emitters (835) arranged in a first pattern on the first substrate (830/10) and comprising a first light emitting element (835 disposed where it is shown in fig. 17) disposed at a first terminal (left terminal end of 830) of the first pattern and a last light emitting element (835 at the opposite end of 830) disposed at a last terminal (835 disposed at the right terminal end of 830) of the first pattern; a light guide (840, 850, 860; hereinafter “LGS”) disposed on the first substrate (830/10); wherein the plurality of light emitters (835) comprises: a second substrate (115); a first cell (cell P2) and a second cell (cell P1), each of the first cell (P2) and the second cell (P1) comprising a first conductivity type semiconductor layer (126; e.g. paragraph 46), an active layer (124), and a second conductivity type semiconductor layer (122); an ohmic layer (130 can be ITO, Ni, Ag; e.g. paragraph 59) disposed on the second conductivity type semiconductor layer (122) of the second cell (P1) and configured to form an ohmic contact; a connector (260-1 between P1 and P2) electrically connecting the first cell (P2) and the second cell (P1) and including a first material (material of 260-1 is conductive; hereinafter “1M”), the connector (260-1) disposed on the second conductivity type semiconductor layer (122) of the first cell (P2) and the first conductivity type semiconductor layer (126) of the second cell (P1), and the connector (260-1) covering an isolation region (air gap formed in 120 to separate P1 and P2; hereinafter “IR”) that is disposed between the first cell (P2) and the second cell (P1); a first pad metal layer (portion of 260-2 over P2 which electrically contacts 126 as shown in fig. 9 and 10; hereinafter “1PML”) electrically connected to the first conductivity type semiconductor layer (126) of the first cell (P2) and including the first material (1M), the first pad metal layer (1PML) disposed over the first cell (P2) without being disposed on the second cell (P1) and spaced apart (upper portion is separated from the lower part of 260-1) from the connector (260-1); a second pad metal layer (272 over P1 as shown in fig. 9, 10; hereinafter “2PML”) electrically connected to the ohmic layer (130) of the second cell (P1); an upper insulation layer (140-2) at least partially disposed above the first and second pad metal layer (1PML, 2PML); and a first bump pad (50) and a second bump pad (40) each at least partially disposed above (40 and 50 extends to a level above a level of 1PML, 2PML) the first pad metal layer (1PML) and the second pad metal layer (2PML), respectively, wherein the upper insulation layer (140-2) and the first bump pad (50) are positioned adjacent to each other above (50 extends to a level above a level of 1PML) the first pad metal layer (1PML) in the first cell (P2), and the upper insulation layer (140-2) and the second bump pad (40) are positioned adjacent to each other above (40 extends to a level above a level of 2PML) the ohmic layer (130) in the second cell (P2), and wherein an edge of the first conductivity type semiconductor layer (126) is spaced apart from an edge (edge of 115, 110) of the second substrate (115, 110). Kim is silent as to explicitly teaching wherein a portion of the second substrate is exposed at the isolation region by the first conductivity type semiconductor layers of the first cell and the second cell and the portion of the second substrate directly contacts a lower insulation layer. Nagai teaches (e.g. figs. 6-9) a portion of the second substrate (110) is exposed at the isolation region (1000) by the first conductivity type semiconductor layers (114) of the first cell (left 112 of fig. 6, step C1) and the second cell (middle 112 of fig. 6, step C1) and the portion of the second substrate (110) directly contacts a lower insulation layer (140 of Nagai which is equivalent to 140-1 of Kim). Further, it can be considered that Nagai teaches the first and second bump pads 106 and 108 to be provided over the first and second cells. It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the isolation region structure as taught by Nagai in the device of Kim in order to have the predictable result of using a structure which more effectively isolated each cell such that leakage current between adjacent cells is more effectively reduced. Re claim 13: Kim teaches the light emitting apparatus of claim 12, wherein the plurality of light emitters (P1-P9) are regularly arranged in the first pattern. Re claim 14: Kim teaches the light emitting apparatus of claim 13, wherein: the light guide (LGS) further comprises a first light guide (840) and a second light guide (850), and a first distance from a top surface of the first light guide (LGS) to a top surface of the plurality of light emitters (835) is different from a second distance from a top surface of the second light guide (850) to the top surface of at least one of the plurality of light emitters (835). Re claim 15: Kim teaches the light emitting apparatus of claim 13, wherein the upper insulation layer (140-2) further comprises a distributed Bragg reflector in which SiO2 and TiO2 are repeatedly stacked on each other (DBR can include different material layers such as an alternating stack of SiO2 and TiO2; e.g. paragraph 63). Re claim 16: Kim teaches the light emitting apparatus of claim 12, wherein the lower insulation layer (140-1) arranged between the second conductivity type semiconductor layer (126) of the first cell (P1) and the second cell (P2) and the upper insulation layer (140-2), and wherein the upper insulation layer (140-2) further comprises a first opening region (opening for 252; hereinafter “1OR”) and the lower insulation layer (140-1) includes a second opening region (opening for 272; hereinafter “2OR”), and the first opening region (1OR) does not overlap with the second opening region (2OR). Re claim 17: Kim teaches the light emitting apparatus of claim 16, wherein a portion of the lower insulation layer (140-1) contacting the ohmic layer (130) has a different thickness with a portion of the lower insulation layer (140-1) disposed around the ohmic layer (130). Re claim 18: Kim teaches the light emitting apparatus of claim 16, wherein: the plurality of light emitters (20) further comprises a second substrate (110); and an edge of the lower insulation layer (140-1) is farther to an edge of the second substrate (110) than an edge of the upper insulation layer is (140-2). Re claim 20: Kim teaches the light emitting apparatus of claim 12, wherein the light guide structure (LGS) further comprises a protrusion region (850 is provided with ridges and valleys). Claim(s) 6 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim and Nagai as applied to claims 1 and 12 above, respectively, and further in view of Jang et al. (US PGPub 2016/0372630; hereinafter “Jang”). Re claims 6 and 19: Kim teaches substantially the entire structure as recited in claims 1 and 12 except explicitly teaching the light emitting apparatus, wherein the second bump pad further comprises an inclined surface. Jung teaches (e.g. fig. 3B) the light emitting apparatus, wherein the second bump pad (173) further comprises an inclined surface (portion of 173 extending into the upper and lower insulation layer has an inclined surface). It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the bump pad structure of Jung in the device of Kim in order to have the predictable result of using a bump pad structure which is in closer and intimate contact with more surface area of the LED device such that heat dissipation would be improved. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached on 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JESSE Y MIYOSHI/ Primary Examiner, Art Unit 2898
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Prosecution Timeline

Show 14 earlier events
May 09, 2025
Response after Non-Final Action
Aug 04, 2025
Non-Final Rejection mailed — §103
Nov 04, 2025
Response Filed
Dec 22, 2025
Final Rejection mailed — §103
Feb 12, 2026
Response after Non-Final Action
Mar 19, 2026
Request for Continued Examination
Mar 24, 2026
Response after Non-Final Action
Sep 04, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

7-8
Expected OA Rounds
57%
Grant Probability
76%
With Interview (+18.7%)
3y 7m (~0m remaining)
Median Time to Grant
High
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