DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 11/07/2025, in which claims 1, 11, 15-18, 20 were amended, claims 10, 13-14,19, 22 were cancelled, claims 23-25 were added, has been entered.
Specification
The amendment to the specification received on 11/07/2025 has been entered.
Drawings
The drawings were received on 11/07/2025. These drawings are acceptable.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 25 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 25, claim 25 recites the limitation "the portion of the sidewall spacer". There is insufficient antecedent basis for this limitation in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-9, 11-12, 15-18, 20, 23 are rejected under 35 U.S.C. 103 as being unpatentable over Holland et al. (US Pub. 20180323259) in view of Lu et al. (US Pub. 20180366666), Cea et al. (US Pub. 20200105755), and Kang et al. (US Pub. 20230282642), and Rachmady et al. (US Pub. 20130341704).
Regarding claim 1, Holland et al. discloses in Fig. 17B, 17C a semiconductor device having a gate-all-around field effect transistor (GAA FET), comprising:
one-dimensional structures [214] disposed over a substrate [202] and extending in a first direction;
a plurality of gate structures [330, 340, 350] extending in a second direction crossing the first direction and formed around each of the one-dimensional structures [214] in channel regions, wherein the plurality of gate structures [330, 340, 350] include a gate dielectric layer [330] wrapping around the one-dimensional structures [214], a work function adjustment layer [340] on the gate dielectric layer [330], and a body gate electrode layer [350] on the work function adjustment layer [340];
a plurality of source/drain regions [regions in which 510 is formed], each source/drain region [region in which 510 is formed] of the plurality of source/drain regions including a semiconductor layer [510] wrapping around each of the one-dimensional structures [214], the one-dimensional structures [214] extending through the plurality of source/drain regions [regions in which 510 is formed] in the first direction, wherein first ends of the one-dimensional structures [214] extend outside a first source/drain region [leftmost source/drain region] of the plurality of source/drain regions that is proximal to the first ends of the one-dimensional structures [214], and second ends of the one-dimensional structures [214] extend outside a second source/drain region [rightmost source/drain region] of the plurality of source/drain regions [regions in which 510 is formed] that is proximal to the second ends of the one-dimensional structures [214]; and
an insulating material [portion of 330 between adjacent nanowires 214] spanning distances between adjacent first ends of the first ends of the one-dimensional structures [214];
the insulating material [portion of 330 between adjacent nanowires 214] spanning distances between adjacent second ends of the second ends of the one-dimensional structures [214];
a sidewall spacer layer [312 and portion of 330 contacting sidewalls of nanowires 214] covering sidewalls of the plurality of gate structures [330, 340, 350], wherein the sidewall spacer layer [312] does not reside as support between the first ends of the one-dimensional structures [214] or the second ends of the one-dimensional structures [214];
source/drain contacts [520 and 530] formed over the source/drain regions [region in which 510 is formed].
Holland et al. fails to explicitly disclose
the semiconductor layer comprises a doped semiconductor layer;
the sidewall spacer layer directly contacting the tips of the first ends of one-dimensional structures and the tips of the second ends of the one-dimensional structures.
However, Holland et al. discloses in paragraph [0055]-[0056] that “a first portion of the first nanowire and second nanowire are doped to form source and drain regions.” Thus, the epitaxial layer [510] wraps around the first portion of first nanowire and second nanowire over the source and drain region is a doped semiconductor layer due to the diffusion of dopant from doped nanowires into the epitaxial layer [510].
Cea et al. discloses in Fig. 1a, paragraph [0033]-[0035], [0050]-[0052]
source/drain regions [102 or 104] includes a doped semiconductor layer;
the sidewall spacer layer [120] directly contacting the tips of the first ends of one-dimensional structures [114 or 116] and the tips of the second ends of the one-dimensional structures [114 or 116].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Cea et al. into the method of Holland et al. to include the semiconductor layer comprises a doped semiconductor layer; the sidewall spacer layer directly contacting the tips of the first ends of one-dimensional structures and the tips of the second ends of the one-dimensional structures. The ordinary artisan would have been motivated to modify Holland et al. in the above manner for the purpose of providing suitable semiconductor material of source/drain region and providing isolation between the source/drain regions from channel regions and preventing interference with the channel region of the nanowires [paragraph [0050] of Cea et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Holland et al. fails to disclose
the insulating material spanning distances from the first source/drain region to tips of the first ends of the one-dimensional structures in a cross-section extending vertically from the substrate and along the first direction;
the insulating material spanning distances from the second source/drain region to tips of the second ends of the one-dimensional structures, in the cross-section.
Rachmady et al. discloses in Fig. 5C, paragraph [0073]
the insulating material [512] spanning distances from the first source/drain region [558] to tips of the first ends of the one-dimensional structures [510] in a cross-section extending vertically from the substrate and along the first direction;
the insulating material [512] spanning distances from the second source/drain region [558] to tips of the second ends of the one-dimensional structures [510], in the cross-section.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Rachmady et al. into the method of Holland et al. to include the insulating material spanning distances from the first source/drain region to tips of the first ends of the one-dimensional structures in a cross-section extending vertically from the substrate and along the first direction; the insulating material spanning distances from the second source/drain region to tips of the second ends of the one-dimensional structures, in the cross-section. The ordinary artisan would have been motivated to modify Holland et al. in the above manner for the purpose of providing suitable material of sacrificial material so that no or substantially no leakage path is created by the sacrificial material [paragraph [0073] of Rachmady et al.].
Holland et al. fails to disclose
the one-dimensional structures comprise carbon nanotubes (CNTs).
Lu et al. discloses in Fig. 1A, Fig. 1B
the one-dimensional structures [100] comprise carbon nanotubes (CNTs).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lu et al. into the method of Holland et al. to include the one-dimensional structures comprise carbon nanotubes (CNTs). The ordinary artisan would have been motivated to modify Holland et al. in the above manner for the purpose of providing one-dimensional structures with superior electrostatics, higher performance and high carrier mobility [paragraph [0002] of Lu et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Holland et al. and Lu et al. fails to disclose
a bottom support layer comprising an insulating material, the bottom support layer spanning a width of the channel region and disposed between the CNTs and the substrate;
wherein a bottommost CNT of the CNTs is disposed equal to an upper surface of the bottom support layer; and
the bottom support layer extends beyond the first and second ends of the CNTs in the first direction.
Kang et al. discloses in Fig. 6, Fig. 7, paragraph [0040], [0046], [0072],
a bottom support layer [bottom portion of 142 and (454 or 554A)] comprising an insulating material, the bottom support layer [bottom portion of 142 and (454 or 554A)] spanning a width of the channel region and disposed between the one-dimensional structures [NSS] and the substrate [102];
wherein a bottommost one-dimensional structure [N1] of the one-dimensional structures [NSS] is disposed equal to an upper surface of the bottom support layer [bottom portion of 142 and (454 or 554A)]; and
the bottom support layer [bottom portion of 142 and (454 or 554A)] extends beyond the opposite ends of the one-dimensional structures [NSS] in the first direction and extends beyond the doped semiconductor layer [130 or 530] in the first direction.
Holland et al. discloses opposite ends of the one-dimensional structures [214] in the first direction contact isolation structure [330, 204 and 312]. Lu et al. discloses one-dimensional structures comprise CNTs and opposite ends of the CNTs 100 in the first direction contact isolation structure [18 and 14]. Kang discloses the bottom support layer covers entire surface of the substrate and extends beyond isolation structure [144 and vertical portion of 142]. Thus, the combination of Holland et al., Kang, and Lu would result to “a bottom support layer comprising an insulating material, the bottom support layer spanning a width of the channel region and disposed between the CNTs and the substrate; wherein a bottommost CNT of the CNTs is disposed equal to an upper surface of the bottom support layer, the bottom support layer extends beyond the opposite ends of the CNTs in the first direction.”
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of the invention to incorporate the teachings of Kang et al. into the method of Holland et al., and Lu et al. to include a bottom support layer comprising an insulating material, the bottom support layer spanning a width of the channel region and disposed between the CNTs and the substrate; wherein a bottommost CNT of the CNTs is disposed equal to an upper surface of the bottom support layer. The ordinary artisan would have been motivated to modify Holland et al., and Lu et al. in the above manner for the purpose of providing a substrate structure suitable for semiconductor device fabrication to provide CNT transistor structure capable of improving the electrical characteristics thereof by suppressing formation of unwanted parasitic transistors [paragraph [0004], [0046] of Kang et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 2, Holland et al. discloses in paragraph [0049] wherein the doped semiconductor layer [510] is crystalline silicon [epitaxial layer is a crystalline layer].
Cea et al. also discloses in paragraph [0052] wherein the doped semiconductor layer [102] is crystalline silicon [epitaxial layer is a crystalline layer].
Regarding claim 3, Holland et al. and Cea et al. fails to disclose wherein an impurity concentration in the doped semiconductor layer is in a range from 1 x 1020 atoms/cm3 to 1 x 1021 atoms/cm3.
However, Applicant has not provided any criticality of the claimed range. Thus, it would have been obvious to modify Holland et al. and Cea et al. to provide the claimed range for at least the purpose of optimization and routine experimentation to obtain desired conductivity for the S/D region and/or to form an ohmic contact with an S/D contact metal. Further, the claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Regarding claim 7, Holland et al. discloses in Fig. 17C
wherein: the one-dimensional structures [214] include multiple groups of one-dimensional structures [214], the one-dimensional structures [214] in a same group are located at a same height, and the multiple groups are located at different heights from each other.
Lu et al. discloses the one-dimensional structures are CNTs.
Lu et al. further discloses in Fig. 1E wherein: the CNTs [100] include multiple groups of CNTs, the CNTs in a same group are located at a same height, and the multiple groups are located at different heights from each other.
Regarding claim 8, Holland et al. discloses in Fig. 10B, Fig. 10C, paragraph [0045] one group of one-dimensional structures [214] of the multiple groups of one-dimensional structures [214] is separated from an adjacent group of one-dimensional structures [214] by a distance in a range from 5 nm to 15 nm.
Lu et al. discloses the one-dimensional structures are CNTs.
Lu et al. further discloses in Fig. 1B, paragraph [0055]-[0058] one group of CNTs of the multiple groups of CNTs is separated from an adjacent group of CNTs by a distance in a range from 5 nm to 15 nm.
Regarding claim 9, Holland et al. discloses in paragraph [0028] and Lu et al. discloses in paragraph [0052] the substrate is made of one of Si and SiGe.
Regarding claims 11-12, Holland et al. discloses in Fig. 17B a semiconductor device having a gate-all-around field effect transistor (GAA FET), comprising:
one-dimensional structures [214] disposed over a substrate [202] and extending in a first direction;
a plurality of gate structures [330, 340, 350] extending in a second direction crossing the first direction and formed around each of the one-dimensional structures [214] in channel regions, wherein the plurality of gate structures [330, 340, 350] include a gate dielectric layer [330] wrapping around the one-dimensional structures [214], a work function adjustment layer [340] on the gate dielectric layer [330], and a body gate electrode layer [350] on the work function adjustment layer [340];
a plurality of source/drain regions [regions in which 510 is formed], each source/drain region [region in which 510 is formed] of the plurality of source/drain regions including a semiconductor layer [510] wrapping around each of the one-dimensional structures [214], the one-dimensional structures [214] extending through the plurality of source/drain regions [regions in which 510 is formed] in the first direction, wherein first ends of the one-dimensional structures [214] extend outside a first source/drain region [leftmost source/drain region] of the plurality of source/drain regions that is proximal to the first ends of the one-dimensional structures [214], and second ends of the one-dimensional structures [214] extend outside a second source/drain region [rightmost source/drain region] of the plurality of source/drain regions [regions in which 510 is formed] that is proximal to the second ends of the one-dimensional structures [214];
an insulating material [portion of 330 between adjacent nanowires 214] spanning distances between adjacent first ends of the first ends of the one-dimensional structures [214] and extending to tips of the first ends of the one-dimensional structures [214] in a cross-section extending vertically from the substrate [202] and along the first direction;
the insulating material [portion of 330 between adjacent nanowires 214] spanning distances between adjacent second ends of the second ends of the one-dimensional structures [214] and extending to tips of the second ends of the one-dimensional structures [214], in the cross-section; and
a sidewall spacer layer [312] covering sidewalls of the plurality of gate structures [330, 340, 350], wherein the sidewall spacer layer [312] does not reside as support between the first ends of the one-dimensional structures [214] or the second ends of the one-dimensional structures [214];
source/drain contacts [520 and 530] formed over the source/drain regions [region in which 510 is formed].
Holland et al. fails to explicitly disclose
the semiconductor layer comprises a doped semiconductor layer;
the sidewall spacer layer directly contacting the tips of the first ends of one-dimensional structures and the tips of the second ends of the one-dimensional structures.
However, Holland et al. discloses in paragraph [0055]-[0056] that “a first portion of the first nanowire and second nanowire are doped to form source and drain regions.” Thus, the epitaxial layer [510] wraps around the first portion of first nanowire and second nanowire over the source and drain region is a doped semiconductor layer due to the diffusion of dopant from doped nanowires into the epitaxial layer [510].
Cea et al. discloses in Fig. 1a, paragraph [0033]-[0035], [0050]-[0052]
source/drain regions [102 or 104] includes a doped semiconductor layer;
the sidewall spacer layer [120] directly contacting the tips of the first ends of one-dimensional structures [114 or 116] and the tips of the second ends of the one-dimensional structures [114 or 116].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Cea et al. into the method of Holland et al. to include the semiconductor layer comprises a doped semiconductor layer; the sidewall spacer layer directly contacting the tips of the first ends of one-dimensional structures and the tips of the second ends of the one-dimensional structures. The ordinary artisan would have been motivated to modify Holland et al. in the above manner for the purpose of providing suitable semiconductor material of source/drain region and providing isolation between the source/drain regions from channel regions and preventing interference with the channel region of the nanowires [paragraph [0050] of Cea et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Holland et al. fails to disclose
the insulating material spanning distances from the first source/drain region to tips of the first ends of the one-dimensional structures in a cross-section extending vertically from the substrate and along the first direction;
the insulating material spanning distances from the second source/drain region to tips of the second ends of the one-dimensional structures, in the cross-section.
Rachmady et al. discloses in Fig. 5C, paragraph [0073]
the insulating material [512] spanning distances from the first source/drain region [558] to tips of the first ends of the one-dimensional structures [510] in a cross-section extending vertically from the substrate and along the first direction;
the insulating material [512] spanning distances from the second source/drain region [558] to tips of the second ends of the one-dimensional structures [510], in the cross-section.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Rachmady et al. into the method of Holland et al. to include the insulating material spanning distances from the first source/drain region to tips of the first ends of the one-dimensional structures in a cross-section extending vertically from the substrate and along the first direction; the insulating material spanning distances from the second source/drain region to tips of the second ends of the one-dimensional structures, in the cross-section. The ordinary artisan would have been motivated to modify Holland et al. in the above manner for the purpose of providing suitable material of sacrificial material so that no or substantially no leakage path is created by the sacrificial material [paragraph [0073] of Rachmady et al.].
Holland et al. fails to disclose
the one-dimensional structures comprise carbon nanotubes (CNTs).
Lu et al. discloses in Fig. 1A, Fig. 1B
the one-dimensional structures [100] comprise carbon nanotubes (CNTs).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lu et al. into the method of Holland et al. to include the one-dimensional structures comprise carbon nanotubes (CNTs). The ordinary artisan would have been motivated to modify Holland et al. in the above manner for the purpose of providing one-dimensional structures with superior electrostatics, higher performance and high carrier mobility [paragraph [0002] of Lu et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Holland et al., and Lu et al. fails to disclose
an isolation insulating layer disposed over a substrate;
the isolation insulating layer being disposed between the CNTs and the substrate;
the isolation insulating layer spanning a width of each of the channel regions in the second direction;
wherein the isolation insulating layer extends beyond the first and second ends of the CNTs in the first direction, the doped semiconductor layer is in contact with the isolation insulating layer, and a bottommost CNT of the CNTs is disposed equal to an upper surface of the isolation insulating layer;
wherein the doped semiconductor layer passes through the isolation insulating layer and is in contact with the substrate.
Kang et al. discloses in Fig. 6, Fig. 7, paragraph [0040], [0046], [0072],
an isolation insulating layer [bottom portion of 142 and (454 or 554A)] disposed over a substrate [102];
the isolation insulating layer [bottom portion of 142 and (454 or 554A)] being disposed between the one-dimensional structures [NSS] and the substrate [102];
the isolation insulating layer [bottom portion of 142 and (454 or 554A)] spanning a width of each of the channel regions in the second direction;
wherein the semiconductor layer [130, 730] is in contact with the isolation insulating layer [bottom portion of 142 and (454 or 554A)], and a bottommost one-dimensional structure [N1] of the one-dimensional structures [NSS] is disposed equal to an upper surface of the isolation insulating layer [bottom portion of 142 and (454 or 554A)];
wherein the semiconductor layer [130, 730] passes through the isolation insulating layer [bottom portion of 142 and (454 or 554A)] and is in contact with the substrate [102].
Holland et al. and Cea et al. discloses the semiconductor layer comprises the doped semiconductor layer. Holland et al. discloses opposite ends of the one-dimensional structures [214] in the first direction contact isolation structure [330, 204 and 312]. Lu et al. discloses one-dimensional structures comprise CNTs and opposite ends of the CNTs 100 in the first direction contact isolation structure [18 and 14]. Kang discloses the isolation insulating layer covers entire surface of the substrate and extends beyond isolation structure [144 and vertical portion of 142]. Thus, the combination of Holland et al., Cea et al., Kang, and Lu would result to “wherein the isolation insulating layer extends beyond the first and second ends of the CNTs in the first direction, the doped semiconductor layer is in contact with the isolation insulating layer, and a bottommost CNT of the CNTs is disposed equal to an upper surface of the isolation insulating layer; wherein the doped semiconductor layer passes through the isolation insulating layer and is in contact with the substrate.”
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of the invention to incorporate the teachings of Kang et al. into the method of Holland et al., Cea et al. and Lu et al. to include an isolation insulating layer disposed over a substrate; the isolation insulating layer being disposed between the CNTs and the substrate; the isolation insulating layer spanning a width of each of the channel regions in the second direction; wherein the isolation insulating layer extends beyond the first and second ends of the CNTs in the first direction, the doped semiconductor layer is in contact with the isolation insulating layer, and a bottommost CNT of the CNTs is disposed equal to an upper surface of the isolation insulating layer, wherein the doped semiconductor layer passes through the isolation insulating layer and is in contact with the substrate. The ordinary artisan would have been motivated to modify Holland et al., Cea et al., and Lu et al. in the above manner for the purpose of providing a substrate structure suitable for semiconductor device fabrication to provide CNT transistor structure capable of improving the electrical characteristics thereof by suppressing formation of unwanted parasitic transistors [paragraph [0004], [0046] of Kang et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 15-16, Kang et al. discloses in Fig. 3B, 5B paragraph [0032]
wherein the work function adjustment layer [a portion of 160] and the gate dielectric layer [152] partially wrap around the bottommost one-dimensional structure [N1];
wherein the work function adjustment layer [a portion of 160] and the gate dielectric layer [152] fully wrap around the one-dimensional structures [N2, N3] other than the bottommost one-dimensional structure [N1].
Holland et al. discloses in Fig. 17C wherein the work function adjustment layer [340] and the gate dielectric layer [330] fully wrap around the one-dimensional structures [214] other than the bottommost one-dimensional structure.
Lu et al. discloses the one-dimensional structures comprise CNTs.
Thus, the combination of Kang et al., Holland et al. and Lu et al. discloses
“wherein the work function adjustment layer and the gate dielectric layer partially wrap around the bottommost CNT; wherein the work function adjustment layer and the dielectric layer fully wrap around the CNTs other than the bottommost CNT.”
Regarding claims 17 and 18, Holland et al. discloses in Fig. 17B, 17C and paragraph [0038]-[0039]
wherein the gate dielectric layer [330] includes one selected from the group consisting of HfO2 and Al2O3;
wherein the work function adjustment layer [340] includes TiN.
Lu et al. discloses the one-dimensional structures comprise CNTs.
Consequently, the combination of Holland et al. and Lu et al. discloses “wherein each of the plurality of gate structures includes a gate dielectric layer wrapping around each of the CNTs.”
Regarding claim 20, Holland et al. discloses in Fig. 17B a semiconductor device having a gate-all-around field effect transistor (GAA FET), comprising:
a first GAA FET; and
a second GAA FET,
wherein: each of the first GAA FET and the second GAA FET includes:
one-dimensional structures [214] disposed over a substrate [202] and extending in a first direction;
a gate structure [330, 340, 350] extending in a second direction crossing the first direction and formed around each of the one-dimensional structures [214] in a channel region, wherein the gate structure [330, 340, 350] includes a gate dielectric layer [330] wrapping around each of the one-dimensional structures [214], a work function adjustment layer [340] formed on the gate dielectric layer [330] and a body gate electrode layer [350] formed on the work function adjustment layer [340];
wherein: the one-dimensional structures [214] are shared by the first GAA FET and the second GAA FET, and the one-dimensional structures [214] in source/drain regions are wrapped around by a silicon layer [510][paragraph [0049]], the one-dimensional structures [214] extend through the source/drain regions in the first direction, wherein first ends of the one-dimensional structures [214] extend outside a first source/drain region of the source/drain regions that is proximal to the first ends of the one-dimensional structures [214], and second ends of the one-dimensional structures [214] extend outside a second source/drain region of the source/drain regions that is proximal to the second ends of the one-dimensional structures [214];
an insulating material [portion of 330 between adjacent nanowires 214] spanning distances between adjacent first ends of the first ends of the one-dimensional structures [214] and extending to tips of the first ends of the one-dimensional structures [214] in a cross-section extending vertically from the substrate [202] and along the first direction;
the insulating material [portion of 330 between adjacent nanowires 214] spanning distances between adjacent second ends of the second ends of the one-dimensional structures [214] and extending to tips of the second ends of the one-dimensional structures [214], in the cross-section;
a sidewall spacer layer [312] covering sidewalls of the plurality of gate structures [330, 340, 350], wherein the sidewall spacer layer [312] does not reside as support between the first ends of the one-dimensional structures [214] or the second ends of the one-dimensional structures [214].
Holland et al. fails to explicitly disclose
the semiconductor layer comprises a doped semiconductor layer;
the sidewall spacer layer directly contacting the tips of the first ends of one-dimensional structures and the tips of the second ends of the one-dimensional structures.
However, Holland et al. discloses in paragraph [0055]-[0056] that “a first portion of the first nanowire and second nanowire are doped to form source and drain regions.” Thus, the epitaxial layer [510] wraps around the first portion of first nanowire and second nanowire over the source and drain region is a doped semiconductor layer due to the diffusion of dopant from doped nanowires into the epitaxial layer [510].
Cea et al. discloses in Fig. 1a, paragraph [0033]-[0035], [0050]-[0052]
source/drain regions [102 or 104] includes a doped semiconductor layer;
the sidewall spacer layer [120] directly contacting the tips of the first ends of one-dimensional structures [114 or 116] and the tips of the second ends of the one-dimensional structures [114 or 116].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Cea et al. into the method of Holland et al. to include the semiconductor layer comprises a doped semiconductor layer; the sidewall spacer layer directly contacting the tips of the first ends of one-dimensional structures and the tips of the second ends of the one-dimensional structures. The ordinary artisan would have been motivated to modify Holland et al. in the above manner for the purpose of providing suitable semiconductor material of source/drain region and providing isolation between the source/drain regions from channel regions and preventing interference with the channel region of the nanowires [paragraph [0050] of Cea et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Holland et al. fails to disclose
the insulating material spanning distances from the first source/drain region to tips of the first ends of the one-dimensional structures in a cross-section extending vertically from the substrate and along the first direction;
the insulating material spanning distances from the second source/drain region to tips of the second ends of the one-dimensional structures, in the cross-section.
Rachmady et al. discloses in Fig. 5C, paragraph [0073]
the insulating material [512] spanning distances from the first source/drain region [558] to tips of the first ends of the one-dimensional structures [510] in a cross-section extending vertically from the substrate and along the first direction;
the insulating material [512] spanning distances from the second source/drain region [558] to tips of the second ends of the one-dimensional structures [510], in the cross-section.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Rachmady et al. into the method of Holland et al. to include the insulating material spanning distances from the first source/drain region to tips of the first ends of the one-dimensional structures in a cross-section extending vertically from the substrate and along the first direction; the insulating material spanning distances from the second source/drain region to tips of the second ends of the one-dimensional structures, in the cross-section. The ordinary artisan would have been motivated to modify Holland et al. in the above manner for the purpose of providing suitable material of sacrificial material so that no or substantially no leakage path is created by the sacrificial material [paragraph [0073] of Rachmady et al.].
Holland et al., Rachmady et al. and Cea et al. fails to disclose
the one-dimensional structures comprise carbon nanotubes (CNTs).
Lu et al. discloses in Fig. 1A, Fig. 1B
the one-dimensional structures [100] comprise carbon nanotubes (CNTs).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lu et al. into the method of Holland et al., Rachmady et al. and Cea et al. to include the one-dimensional structures comprise carbon nanotubes (CNTs). The ordinary artisan would have been motivated to modify Holland et al., Rachmady et al. and Cea et al. in the above manner for the purpose of providing one-dimensional structures with superior electrostatics, higher performance and high carrier mobility [paragraph [0002] of Lu et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Holland et al., and Lu et al. fails to disclose
an isolation insulating layer between the CNTs and the substrate and spanning a width of the channel region in the second direction;
the isolation insulating layer extends beyond the first and second ends of the CNTs in the first direction, and
a bottommost CNT of the CNTs is disposed equal to an upper surface of the isolation insulating layer.
Kang et al. discloses in Fig. 6, Fig. 7, paragraph [0040], [0046], [0072],
an isolation insulating layer [bottom portion of 142 and (454 or 554A)] between the one-dimensional structures [NSS] and the substrate [102] and spanning a width of the channel region in the second direction;
the isolation insulating layer [bottom portion of 142 and (454 or 554A)] extends beyond the first and second ends of the one-dimensional structures [NSS] in the first direction, and
a bottommost one-dimensional structure [N1] of the one-dimensional structures [NSS] is disposed equal to an upper surface of the isolation insulating layer [bottom portion of 142 and (454 or 554A)].
Lu et al. discloses the one-dimensional structures are CNTs.
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of the invention to incorporate the teachings of Kang et al. into the method of Holland et al. and Lu et al. to include an isolation insulating layer between the CNTs and the substrate and spanning a width of the channel region in the second direction; the isolation insulating layer extends beyond the first and second ends of the CNTs in the first direction, and a bottommost CNT of the CNTs is disposed equal to an upper surface of the isolation insulating layer. The ordinary artisan would have been motivated to modify Holland et al. and Lu et al. in the above manner for the purpose of providing CNT transistor structure capable of improving the electrical characteristics thereof by suppressing formation of unwanted parasitic transistors; providing CNT transistor structure capable of improving the electrical characteristics thereof by suppressing formation of unwanted parasitic transistors [paragraph [0004], [0046] of Kang et al.].
Regarding claim 23, Cea et al. discloses in paragraph [0050]
wherein the sidewall spacer layer [120] includes one or more of silicon nitride, SiON, SiOC, SiOCN and SiCN [silicon nitride or silicon oxynitride].
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Holland et al. (US Pub. 20180323259) in view of Lu et al. (US Pub. 20180366666), Cea et al. (US Pub. 20200105755), Kang et al. (US Pub. 20230282642) and Rachmady et al. (US Pub. 20130341704) as applied to claim 1 above and further in view of Chiang et al. (US Pub. 20180151438).
Regarding claims 4-5, Holland et al. fails to disclose
wherein the GAA FET is an n-type FET and the doped semiconductor layer contains at least one of P and As as impurities;
wherein the GAA FET is a p-type FET and the doped semiconductor layer contains at least one of B and Ga as impurities.
Chiang et al. discloses in paragraph [0028]
wherein the GAA FET is an n-type FET and the doped semiconductor layer [510] contains at least one of P and As as impurities;
wherein the GAA FET is a p-type FET and the doped semiconductor layer [510] contains at least one of B and Ga as impurities.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chiang et al. into the method of Holland et al. to include wherein the GAA FET is an n-type FET and the doped semiconductor layer contains at least one of P and As as impurities; wherein the GAA FET is a p-type FET and the doped semiconductor layer contains at least one of B and Ga as impurities. The ordinary artisan would have been motivated to modify Holland et al. in the above manner for the purpose of providing suitable dopant for forming S/D features for a PFET/a NFET. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 6, Holland et al. discloses
wherein a semiconductor layer [portion of 214 between 510 and gate structure] is disposed between the doped semiconductor layer [510] and the gate structure [330, 340, 350].
PNG
media_image1.png
467
535
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Greyscale
Holland et al. fails to disclose
wherein the semiconductor layer having a lower impurity concentration than the doped semiconductor layer.
Chiang et al. discloses in Fig. 10, paragraph [0031]
wherein the semiconductor layer [portion of 108 vertically overlapped spacer 140] having a lower impurity concentration than the doped semiconductor layer [510].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chiang et al. into the method of Holland et al. to include wherein the semiconductor layer having a lower impurity concentration than the doped semiconductor layer. The ordinary artisan would have been motivated to modify Holland et al. in the above manner for the purpose of providing suitable dopant concentration in the nanowires with respect to dopant concentration in the doped semiconductor layer to obtain S/D feature having desired property [paragraph [0031] of Chiang et al.].
In addition, one of ordinary skill in the art would have recognized the finite number of predictable solutions for dopant concentration in the nanowires with respect to dopant concentration in the doped semiconductor layer: dopant concentration in the nanowires is higher than/lower than/same as dopant concentration in the doped semiconductor layer. Absent unexpected results, it would have been obvious to try dopant concentration in the nanowires with respect to dopant concentration in the doped semiconductor layer to obtain S/D feature having desired property.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Holland et al. (US Pub. 20180323259) in view of Lu et al. (US Pub. 20180366666), Kang et al. (US Pub. 20230282642), Cea et al. (US Pub. 20200105755) and Rachmady et al. (US Pub. 20130341704) as applied to claim 20 above and further in view of Ching et al. (US Pub. 20170005195)
Regarding claim 21, Holland et al. and Rachmady et al. fails to disclose
wherein the insulating material includes one or more of silicon oxide, silicon nitride, SiON, SiOC, SiOCN and SiCN;
Ching et al. discloses in Fig. 30A, Fig. 30B, paragraph [0048]-[0049]
wherein the insulating material [1102] includes one or more of silicon oxide, silicon nitride, SiON, SiOC, SiOCN and SiCN;
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Ching et al. into the method of Holland et al. and Rachmady et al. to include wherein the insulating material includes one or more of silicon oxide, silicon nitride, SiON, SiOC, SiOCN and SiCN. The ordinary artisan would have been motivated to modify Holland et al. and Rachmady et al. in the above manner for the purpose of providing suitable insulating material filling the gaps between nanowires in the source/drain region [paragraph [0049] of Ching et al.].
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Holland et al. (US Pub. 20180323259) in view of Lu et al. (US Pub. 20180366666), Kang et al. (US Pub. 20230282642), Cea et al. (US Pub. 20200105755) and Rachmady et al. (US Pub. 20130341704) as applied to claim 20 above and further in view of Iwata et al. (US Pub. 20180277566).
Regarding claim 24, Holland et al. and Rachmady et al. fails to disclose
wherein the insulating material is made of an organic material.
Iwata et al. discloses in paragraph [0085]
wherein the insulating material is made of an organic material.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Iwata et al. into the method of Holland et al. and Rachmady et al. to include wherein the insulating material is made of an organic material. The ordinary artisan would have been motivated to modify Holland et al. and Rachmady et al. in the above manner for the purpose of providing suitable insulating material. Further, it would have been obvious to select organic insulating materials based on its suitability for use as the insulating material in the device of Holland et al. and Rachmady et al. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Response to Arguments
Applicant’s arguments with respect to claims 1-9, 11-12, 15-18, 20-21, 23-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited art discloses similar materials, devices and methods.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893