Attorney Docket Number: AD6680-US
Filing Date: 11/02/2021
Inventors: Shan et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments filed 7/29/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgment
The Amendment filed on 7/29/2025, responding to the Office action mailed on 6/18/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant cancelled claims 5-7 and 17-20, and added new claims 21-27. Accordingly, pending in this application are claims 1-4, 8-16, and 21-27.
Election/Restrictions
Newly submitted claims 25-27 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
Invention in claim 25 pertains to a central interconnect system, as opposed to the solder joint configuration of claims 1 and 12. It also discloses a core between the layers of conductive lines, which is found distinct from the setup of claims 1 and 12 wherein the conductive lines are comprised within the substrate/die at the top of the device. It also discloses a conductive via through the core between the first layer and second layer comprising the conductive lines, which is found distinct from the setup of claims 1 and 12 wherein a via is comprised within a substrate at the bottom of the device, with the conductive lines located within the substrate/die at the top of the device.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 25-27 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Response to Arguments
Applicant’s arguments and amendments to the Claims successfully overcome the claim rejections under 35 U.S.C. 103, as previously formulated in the Non-Final Office action mailed on 6/18/2025. The Applicant’s response filed 7/29/2025 argues that the usage of the reference Sharma is not prior art to the present patent application under 35 U.S.C. 102(b)(2)(c). This argument is found persuasive and the claim rejection of record regarding the Sharma reference is withdrawn. However, additional prior art regarding the new amendments of record were found, and therefore this action is FINAL.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, 10, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Suh (US 20070080451 A1) in view of Gupta (US 20200403299 A1) further in view of Liao (US 20220328952 A1).
Regarding claim 1, Suh (see, e.g., fig. 1) shows most aspects of the instant invention including a microelectronic package comprising:
A first substrate (e.g., packaging substrate 108), wherein a first face of the first substrate (e.g., packaging substrate 108) comprises a first conducive contact (e.g., solder pad 110);
A second substrate (e.g., microprocessor die 102) over the first substrate (e.g., packaging substrate 108), wherein a second face of the second substrate (e.g., microprocessor die 102) comprises a second conductive contact (e.g., solder pad 104);
A plurality of solder joints (e.g., solder 106) between and coupled with the first substrate (e.g., packaging substrate 108) and the second substrate (e.g., microprocessor die 102), wherein:
the plurality of solder joints (e.g., solder 106) comprises a first solder joint (e.g., leftmost solder joint 106) and a second solder joint (e.g., center solder joint 106) coplanar with the first solder joint (e.g., leftmost solder joint 106);
the first solder joint (e.g., leftmost solder joint 106) comprises a continuous layer of intermetallic compounds (IMCs) (see, e.g., paragraph 15: “In an embodiment, the solder 106 may include a bulk intermetallic compound…that includes a first and second element…In yet another embodiment, the solder 106 may be substantially entirely intermetallic compounds…”) between the first conductive contact (e.g., solder pad 110) and the second conductive contact (e.g., solder pad 104);
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Suh (see, e.g., fig. 1), however, fails to show the first solder joint is conductively isolated from conductive lines in the second substrate, and the second solder joint is conductively coupled with one or more of the conductive lines.
Gupta (see, e.g., fig. 3E), in a similar device to Suh, teaches conductive lines (see, e.g., paragraph 38 “The semiconductor die may include various elements…including…conductive lines”) within the die (e.g., IC die 180)
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the conductive lines of Gupta within the die of Suh, in order to achieve the expected result of providing conductive pathways to travel between different regions of the die substrate. Note that the second solder joint, which is electrically coupled with the die, would be conductively coupled with these conductive lines.
Suh in view of Gupta, however, fails to teach the first solder joint is conductively isolated from conductive lines in the second substrate.
Do (see, e.g., fig. 1F) teaches a plurality of dies (e.g., 160A + 160B, separated by encapsulant 172), with individual sets of solder joints (e.g., electrical connectors 152 + paragraph 39 “…electrical connectors 152 include a conductive material such as solder…”) provided for each die.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the encapsulant layer of Do within the die of Suh in view of Gupta, in order to divide the die into different package portions (all within the same substrate), each with an individual set of solder joints, decreasing the chance of risk defect and reducing the cost of manufacturing a single large monolithic die. Note that this encapsulation layer electrically isolates the solder joint regions to their own respective dies, and hence the first solder joint would be electrically isolated from the conductive lines conductively coupled with the second solder joint.
Regarding claim 8, Suh (see, e.g., fig. 1) teaches all aspects of the instant invention including the first substrate (e.g., packaging substrate 108) and the second substrate (e.g., microprocessor die 102) include one or more of: a substrate (packaging substrate 108 is a substrate), a die (microprocessor die 102 is a die), a bridge die, an interposer, a patch, a thin film, a motherboard, a redistribution layer (RDL), and an organic PCB.
Regarding claim 10, Suh (see, e.g., fig. 1) teaches all aspects of the instant invention including the plurality of solder joints includes at least three solder joints (see figure below; solder joints 1-3) each including a continuous layer of IMCs (see, e.g., paragraph 15: “In an embodiment, the solder 106 may include a bulk intermetallic compound…that includes a first and second element…In yet another embodiment, the solder 106 may be substantially entirely intermetallic compounds…”) from a respective conductive contact (e.g., solder pad 110 below each respective solder joint) of the first substrate (e.g., solder pad 110 of packaging substrate 108) to a respective conductive contact (e.g., solder pad 104 above each respective solder joint) of the second substrate (e.g., solder pad 104 of microprocessor die 102).
Regarding claim 12, Suh teaches most aspects of the instant invention, including system comprising:
A substrate (e.g., packaging substrate 108);
A die (e.g., microprocessor die 102) over the substrate (e.g., packaging substrate 108);
A plurality of solder joints (e.g., solder 106) between the substrate (e.g., packaging substrate 108) and the die (e.g., microprocessor die 102), the plurality of solder joints (e.g., solder 106) comprises a first solder joint (e.g., leftmost solder joint 106) and a second solder joint (e.g., center solder joint 106) coplanar with the first solder joint (e.g., leftmost solder joint 106), including a continuous layer of intermetallic compounds (IMCs) (see, e.g., paragraph 15: “In an embodiment, the solder 106 may include a bulk intermetallic compound…that includes a first and second element…In yet another embodiment, the solder 106 may be substantially entirely intermetallic compounds…”) between a first conductive contact (e.g., solder pad 110) of the substrate (e.g., packaging substrate 108) to a second conductive contact (e.g., solder pad 104) of the die (e.g., microprocessor die 102).
Suh (see, e.g., fig. 1), however, fails to show the first solder joint is conductively isolated from conductive lines in the die, and the second solder joint is conductively coupled with one or more of the conductive lines.
Gupta (see, e.g., fig. 3E), in a similar device to Suh, teaches conductive lines (see, e.g., paragraph 38 “The semiconductor die may include various elements…including…conductive lines”) within the die (e.g., IC die 180)
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the conductive lines of Gupta within the die of Suh, in order to achieve the expected result of providing conductive pathways to travel between different regions of the die substrate. Note that the second solder joint, which is electrically coupled with the die, would be conductively coupled with these conductive lines.
Suh in view of Gupta, however, fails to teach the first solder joint is conductively isolated from conductive lines in the die.
Do (see, e.g., fig. 1F) teaches a plurality of dies (e.g., 160A + 160B, separated by encapsulant 172), with individual sets of solder joints (e.g., electrical connectors 152 + paragraph 39 “…electrical connectors 152 include a conductive material such as solder…”) provided for each die.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the encapsulant layer of Do within the die of Suh in view of Gupta, in order to divide the die into different package portions (all within the same substrate), each with an individual set of solder joints, decreasing the chance of risk defect and reducing the cost of manufacturing a single large monolithic die. Note that this encapsulation layer electrically isolates the solder joint regions to their own respective dies, and hence the first solder joint would be electrically isolated from the conductive lines conductively coupled with the second solder joint.
Regarding claim 13, Suh (see, e.g., fig. 6) teaches a processor (see, e.g., paragraph 35 “The processor 606….may be connected to other components…” or paragraph 36 “a graphics processor (integrated with the motherboard 604…)”).
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Suh in view of Gupta further in view of Liao and Liu (US 2019010533 A1).
Regarding claim 2, Suh in view of Gupta further in view of Liao fails to teach the first solder joint including the continuous layer of IMCs includes copper particles throughout the solder joint, including throughout a middle portion of the solder joint between lower and upper portions adjacent to the first conductive contact and the second conductive contact.
Liu (see, e.g., figure 1B), in a similar device to Suh in view of Gupta further in view of Liao, teaches (see, e.g., paragraph 21: ”Example compositions of intermetallic compounds include a copper, nickel, and solder(e.g., tin/silver/copper) composition, a copper and solder (e.g., tin/silver/copper) composition, or the like.”)
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention that the IMCs in the first solder joint of Suh in view of Gupta further in view of Liao could comprise the copper particles of Liu, including throughout a middle portion of the solder joint (see paragraph 15 of Suh: “In yet another embodiment, the solder 106 may be substantially entirely intermetallic compounds…”), as copper is a known material to be included in intermetallic compounds, as taught by paragraph 21 of Liu.
Regarding claim 14, Suh in view of Gupta further in view of Liao fails to teach the first solder joint including the continuous layer of IMCs includes copper particles throughout the solder joint, including throughout a middle portion of the solder joint between lower and upper portions adjacent to the first conductive contact and the second conductive contact.
Liu (see, e.g., figure 1B), in a similar device to Suh in view of Gupta further in view of Liao, teaches (see, e.g., paragraph 21: ”Example compositions of intermetallic compounds include a copper, nickel, and solder(e.g., tin/silver/copper) composition, a copper and solder (e.g., tin/silver/copper) composition, or the like.”)
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention that the IMCs in the first solder joint of Suh in view of Gupta further in view of Liao could comprise the copper particles of Liu, including throughout a middle portion of the solder joint (see paragraph 15 of Suh: “In yet another embodiment, the solder 106 may be substantially entirely intermetallic compounds…”), as copper is a known material to be included in intermetallic compounds, as taught by paragraph 21 of Liu.
Claims 3 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Suh in view Gupta further in view of Liao and Miyauchi (US 20210125784 A1).
Regarding claim 3, Suh in view of Gupta further in view of Liao fails to teach the first solder joint including the continuous layer of IMCs includes cured epoxy from a no-remelt solder around the continuous layer of IMCs.
Miyauchi (see, e.g., fig. 4), in a similar device to Suh in view of Gupta further in view of Liao, teaches a first solder joint including the cured epoxy from a no-remelt solder (see, e.g., paragraph 35 “A joining material 70 is used for connection. Joining material may preferably be made using a material such as solder, an electrically conductive adhesive, a transient liquid-phase sintering (TLP) material, for example.”)
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention that the first solder joint of Suh in view of Gupta further in view of Liao could include TLPS paste/material of Miyauchi in the solder joint including a continuous layer of intermetallic compounds (see, e.g., paragraph 15: “In an embodiment, the solder 106 may include a bulk intermetallic compound…that includes a first and second element…In yet another embodiment, the solder 106 may be substantially entirely intermetallic compounds…”) of Suh in order to assist in prevention of remelting of the connection during subsequent electronic assembly cycles.
Regarding claim 15, Suh in view of Gupta further in view of Liao fails to teach the first solder joint including the continuous layer of IMCs includes cured epoxy from a no-remelt solder around the continuous layer of IMCs.
Miyauchi (see, e.g., fig. 4), in a similar device to Suh in view of Gupta further in view of Liao, teaches a first solder joint including the cured epoxy from a no-remelt solder (see, e.g., paragraph 35 “A joining material 70 is used for connection. Joining material may preferably be made using a material such as solder, an electrically conductive adhesive, a transient liquid-phase sintering (TLP) material, for example.”)
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention that the first solder joint of Suh in view of Gupta further in view of Liao could include TLPS paste/material of Miyauchi in the solder joint including a continuous layer of intermetallic compounds (see, e.g., paragraph 15: “In an embodiment, the solder 106 may include a bulk intermetallic compound…that includes a first and second element…In yet another embodiment, the solder 106 may be substantially entirely intermetallic compounds…”) of Suh in order to assist in prevention of remelting of the connection during subsequent electronic assembly cycles.
Claims 4 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Suh in view of Gupta further in view of Liao and Hovis (US 20200373285 A1).
Regarding claim 4, Suh in view of Gupta further in view of Liao fails to teach the first solder joint has a melting point that is higher than the second solder joint.
Hovis (see, e.g., fig. 2), in a similar device to Suh, teaches a first solder joint has a melting point that is higher than other solder joints (see, e.g., paragraph 55 “Other techniques can be employed, such as using solder materials with different melting points for different sets of solder balls.”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention that the solder joints of Suh in view of Gupta further in view of Liao could possess different melting points, for the purpose of preventing desoldering in soldered locations during a secondary solder reflow process (see, e.g., paragraph 55 of Hovis).
Regarding claim 16, Suh in view of Gupta further in view of Liao fails to teach the first solder joint has a melting point that is higher than the second solder joint.
Hovis (see, e.g., fig. 2), in a similar device to Suh, teaches a first solder joint has a melting point that is higher than other solder joints (see, e.g., paragraph 55 “Other techniques can be employed, such as using solder materials with different melting points for different sets of solder balls.”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention that the solder joints of Suh in view of Gupta further in view of Liao could possess different melting points, for the purpose of preventing desoldering in soldered locations during a secondary solder reflow process (see, e.g., paragraph 55 of Hovis).
Claims 9 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Suh in view of Gupta further in view of Liao and Lee (US 20150035148 A1).
Regarding claim 9, Suh in view of Gupta further in view of Liao fails to teach the first solder joint including the continuous layer of IMCs is located in a via in the first substrate.
Lee (see, e.g., fig. 2), in a similar device to Suh in view of Gupta further in view of Liao, teaches a first solder joint (e.g., solder ball 215) is located in a via (e.g., conductive connecting portion 315) in the first substrate (e.g., interconnection part 101 or lower package substrate 110).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention that the via of Lee could be included to comprise the solder joint including the continuous layer of IMCs of Suh to achieve the expected result of increasing the contact area (see paragraph 76 of Lee) of the conductive portion, improving electrical connection stability.
Regarding claim 23, Lee (see, e.g., fig. 2), in a similar device to Suh in view of Gupta further in view of Liao, teaches a conductive via (e.g., conductive connecting portion 315) through at least one layer of a substrate (e.g., lower package substrate 110), wherein at least a portion of a first solder joint (e.g., solder ball 215) is coplanar with the conductive via (e.g., conductive connecting portion 315).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the via of Lee through a layer of the substrate of Suh in view of Gupta further in view of Liao to achieve the expected result of increasing the contact area (see paragraph 76 of Lee) of the conductive portion, improving electrical connection stability.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Suh in view of Gupta further in view of Liao and Yang (US 20130221521 A1).
Regarding claim 11, Suh (see, e.g., fig. 1), teaches most aspects of the instant invention, including the first solder joint (e.g., leftmost solder joint 106) that includes a continuous layer of IMCs from a respective conductive contact (e.g., solder pad 110 below each respective solder joint) of the first substrate (e.g., solder pad 110 of packaging substrate 108) to a respective conductive contact (e.g., solder pad 104 above each respective solder joint) of the second substrate (e.g., solder pad 104 of microprocessor die 102).
Suh in view of Gupta further in view of Liao, however, fails to teach that the number of the plurality of solder joints that include a continuous layer of IMCs is in a range of: one solder joint to 50% of the plurality of solder joints.
Yang (see, e.g., fig. 1C), in a similar device to Suh in view of Gupta further in view of Liao, teaches the solder joint (e.g., solder bump 108) that include a continuous layer of IMCs (see, e.g., claims 13 + claim 18: “wherein the solder bump contains…an IMC phase…”) is in a range of: one solder joint to 50% of the plurality of solder joints (claim 18 modifies a single solder bump’s IMC phase, leaving the remaining phases traditional).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to modify the structure of Suh in view of Gupta further in view of Liao to form the minority IMC solder joint to traditional solder joint ratio of Yang, in order to include the solder reflow benefits of the IMC solder joints in specific areas of the device, while saving on the cost of IMC solder formations by using primarily traditional electrical connectivity methods via regular solder joints.
Regarding claim 16, Suh in view of Gupta further in view of Liao fails to teach the first solder joint has a melting point that is higher than the second solder joint.
Hovis (see, e.g., fig. 2), in a similar device to Suh, teaches a first solder joint has a melting point that is higher than other solder joints (see, e.g., paragraph 55 “Other techniques can be employed, such as using solder materials with different melting points for different sets of solder balls.”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention that the solder joints of Suh in view of Gupta further in view of Liao could possess different melting points, for the purpose of preventing desoldering in soldered locations during a secondary solder reflow process (see, e.g., paragraph 55 of Hovis).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Suh in view of Gupta further in view of Liao and Buot (US 20220223529 A1).
Regarding claim 21, Suh (see, e.g., fig. 1) shows the second substrate comprises a die (see, e.g., paragraph 11 “…the device 100 includes a microprocessor die 102…”)
Suh in view of Gupta further in view of Liao, however, fails to explicitly show the second substrate comprises a bridge die.
Buot (see, e.g., fig. 7), in a similar device to Suh in view of Gupta further in view of Liao, teaches a bridge die is a known type of die (see, e.g., paragraph 64 “…may be implemented as a die (e.g., bridge die) or as a substrate…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the bridge die of Buot within the second substrate of Suh in view of Gupta further in view of Liao, as a bridge die was a well-known component at the time of filing the invention to serve as a type of die.
Claims 22 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Suh in view of Gupta further in view of Liao, Buot, and Tang (US 20210183794 A1).
Regarding claim 22, Suh in view of Gupta further in view of Liao and Buot fails to show an integrated circuit (IC) die over and coupled with the bridge die.
Tang (see, e.g., fig. 7B) teaches an IC die over and coupled with a bridge die (see, e.g., paragraph 103 “the dies 126a,126b… are a semiconductor bridge die…the dies 226a, 226b…application specific integrated circuit (ASIC) die” + fig. 7B, IC dies over and coupled with bridge dies).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the integrated circuit die of Tang over and coupled with the bridge die of Suh in view of Gupta further in view of Liao and Buot, in order to provide any necessary dies such as logic dies, memory dies, power management dies, et cetera (see, e.g., paragraph 49 of Tang), in connection with the bridge die.
Regarding claim 24, Suh in view of Gupta further in view of Liao and Buot shows the die (e.g., microprocessor die 102) comprises a first die.
Suh in view of Gupta further in view of Liao and Buot, however, fails to show a second die over and coupled with the first die.
Tang (see, e.g., fig. 7B) teaches an IC die over and coupled with a bridge die (see, e.g., paragraph 103 “the dies 126a,126b… are a semiconductor bridge die…the dies 226a, 226b…application specific integrated circuit (ASIC) die” + fig. 7B, IC dies over and coupled with bridge dies).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the integrated circuit die of Tang over and coupled with the first bridge die of Suh in view of Gupta further in view of Liao and Buot, in order to provide any necessary dies such as logic dies, memory dies, power management dies, et cetera (see, e.g., paragraph 49 of Tang), in connection with the bridge die.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should
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Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts to reach
the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on
(571) 272-1705.
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/Thomas McCoy/
________________________
Thomas McCoy
Patent Examiner
Art Unit 2814
571-272-0282
/WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814