Prosecution Insights
Last updated: April 19, 2026
Application No. 17/517,296

DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

Final Rejection §112
Filed
Nov 02, 2021
Examiner
PATERSON, BRIGITTE A
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Seoul Semiconductor Co. Ltd.
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
2y 11m
To Grant
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
283 granted / 371 resolved
+8.3% vs TC avg
Strong +23% interview lift
Without
With
+23.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
31 currently pending
Career history
402
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
45.1%
+5.1% vs TC avg
§102
30.1%
-9.9% vs TC avg
§112
22.2%
-17.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 371 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-15 and 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 recites “a distance between adjacent light emitters of the blue, green and red light emitters is greater than half the width of the light emitting diode chip of one of the blue, green and red light emitters”. However, the originally filed disclosure supports the claimed distance requirements for only between adjacent blue light emitters and further only when referring to the distance between adjacent blue light emitters on the third manufacturing substrate when being applied to the circuit board 200 in the bonding step (Figs. 2I-2J [0089-0091]). PNG media_image1.png 546 563 media_image1.png Greyscale The light emitter spacing of the completed display is neither depicted nor described as having the claimed distance between adjacent light emitters. Therefore, the claims are rejected as failing to comply with the written description requirement. PNG media_image2.png 251 537 media_image2.png Greyscale Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BRIGITTE A. PATERSON Primary Examiner Art Unit 2896 /BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Nov 02, 2021
Application Filed
May 22, 2025
Response after Non-Final Action
Sep 09, 2025
Non-Final Rejection — §112
Dec 08, 2025
Response Filed
Mar 06, 2026
Final Rejection — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12588352
ENERGY LEVELS AND DEVICE STRUCTURES FOR PLASMONIC OLEDS
2y 5m to grant Granted Mar 24, 2026
Patent 12588495
BONDING ALIGNMENT MARKS AT BONDING INTERFACE
2y 5m to grant Granted Mar 24, 2026
Patent 12583740
INTER-POLY CONNECTION FOR PARASITIC CAPACITOR AND DIE SIZE IMPROVEMENT
2y 5m to grant Granted Mar 24, 2026
Patent 12581709
TELLURIUM OXIDE, AND THIN FILM TRANSISTOR COMPRISING SAME AS CHANNEL LAYER
2y 5m to grant Granted Mar 17, 2026
Patent 12568866
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+23.4%)
2y 11m
Median Time to Grant
Moderate
PTA Risk
Based on 371 resolved cases by this examiner. Grant probability derived from career allow rate.

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