DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 04/27/2026 amendments of claims 1 and 18 have been noted and entered.
The 04/27/2026 addition of new claims 28-29 has been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 6-10, filed 04/27/2026, with respect to the rejection(s) of claim(s) 1-6, 8, 10, 12-13, 16-18 and 25-17 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Hashemi, US 20020149102 A1 (Hashemi).
New Grounds of Rejection
New grounds of rejection, prior art reference Hashemi, US 20020149102 A1 (Hashemi), appears below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-3, 5-6, 8, 17-18 and 27-29 are rejected under 35 U.S.C. 103 as being unpatentable over Pierson et al, US 6774315 B1 (Pierson) in view of Hu et al, US 20190295982 A1 (Hu) in further view of Daubenspeck et al, US 20100038780 A1 (Daubenspeck) in further view of Hashemi, US 20020149102 A1 (Hashemi).
Regarding claim 1; Pierson teaches a chip module, comprising:
a chip (Pierson: Fig (7): 23) having a front side and a rear side (Col.3 lines 20-50);
a chip carrier (3) having an upper side facing the chip (23);
a contact layer (7) formed of an electrically conductive material and arranged on the upper side of the chip carrier (3) between the rear side of the chip (23) and the upper side of the chip carrier (3);
an electrically conductive adhesive arranged on an upper side of the contact layer facing the chip, the electrically conductive adhesive connecting the upper side of the contact layer and the rear side of the chip,
the contact layer (7) has a plurality of regions (Plurality of Regions) electrically insulated from each other and each electrically connected to the chip by the electrically conductive adhesive,
at least two of the plurality of regions have a plated-through hole (Fig (1): 5) extending from the upper side of the chip carrier (3) to an underside of the chip carrier (3),
the contact layer (7) and the electrically conductive adhesive fill the plated-through hole (5);
an electrically non-conductive adhesive arranged between the chip carrier and the chip and connecting the upper side of the chip carrier to the rear side of the chip,
the electrically non- conductive adhesive is arranged on the contact layer and between the electrically conductive adhesive on the regions of the contact layer;
a passivation applied over at least a portion of the chip module, the passivation includes an underfill that is a polymer,
the underfill flows between the chip and the chip carrier to fill a space between the chip and the chip carrier and fix the chip to the chip carrier;
an electrical contact element arranged on both the upper side and the underside of the chip carrier; and
a bonding wire electrically connecting the front side of the chip to the electrical contact element.
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Pierson’s embodiment of Fig. (7) lacks an electrically conductive adhesive arranged on an upper side of the contact layer facing the chip, the electrically conductive adhesive connecting the upper side of the contact layer and the rear side of the chip, nor the electrically conductive adhesive filling the plated-through hole.
However, Pierson discloses in their specifications (see col 3 lines 46-50 of Pierson’s specifications: “For some applications, the copper plated vias could then be filled with a conductive adhesive composition, if necessary, but the arrangements shown in FIGS. 5 and 7 use a different approach.”). Given this description disclosed by Pierson and combining this description with Figs (1) and (7) of Pierson, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify the first embodiment disclose din Pierson by using an electrically conductive adhesive as suggested by Pierson to lead to both the contact layer (7) and the conductive adhesive filling the plated-through via and establishing an electrical connection between the chip (23) at the top of the carrier (3) and the bottom of the carrier and that such a choice of a conductive adhesive would be suitable for certain processing conditions making the process more efficient.
Pierson does not teach an electrically non-conductive adhesive arranged between the chip carrier and the chip and connecting the upper side of the chip carrier to the rear side of the chip, the electrically non- conductive adhesive is arranged on the contact layer and between the electrically conductive adhesive on the regions of the contact layer.
However, Hu teaches an electrically non-conductive adhesive (Hu: Fig(9): 300, [0062]: “… and the insulating medium 300 (adhesive film) is provided with an additional through hole communicating with the first openings 120c of the connection through holes 120a, 120b.”) arranged between the chip carrier (100) and the chip (200) and connecting the upper side of the chip carrier (100) to the rear side of the chip (200), the electrically non- conductive adhesive (300) is arranged on the contact layer (110a) and between the electrically conductive adhesive (400a, 400b) on the regions of the contact layer (110a).
Pierson and Hu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson by introducing the non-conductive adhesive disclosed in Hu to enhance the attachment of the chip to the chip carrier to avoid any possibility of mechanical damage if the device was to experience any mechanical stress.
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Pierson in view of Hu does not teach a passivation applied over at least a portion of the chip module, the passivation includes an underfill that is a polymer, the underfill flows between the chip and the chip carrier to fill a space between the chip and chip carrier and fix the chip to the chip carrier.
Daubenspeck teaches a passivation (Daubenspeck: Fig (5): 20) applied over at least a portion of the chip module (10), the passivation includes an underfill (20) that is a polymer, the underfill flows ([0030]) between the chip (10) and the chip carrier (22) to fill a space between the chip (10) and chip carrier (22) and fix the chip (10) to the chip carrier (22, [0030]).
Pierson in view of Hu and Daubenspeck are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu by adding the passivation underfill layer flowing between the chip and the chip carrier as disclosed in Duabenspeck to improve the insulation of the chip from the carrier and to enhance the adhesion of the chip to the carrier leading to a more reliable device.
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Pierson in view of Hu in further view of Daubenspeck does not teach an electrical contact element arranged on both the upper side and the underside of the chip carrier; and
a bonding wire electrically connecting the front side of the chip to the electrical contact element.
Hashemi teaches an electrical contact element (Hashemi: Fig (8): 837+864+847) arranged on both the upper side and the underside of the chip carrier (820); and
a bonding wire (860) electrically connecting the front side of the chip (812) to the electrical contact element (837+864+847).
Pierson in view of Hu in further view of Daubenspeck and Hashemi are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck by connecting the chip to the contact element as disclosed in Hashemi to facilitate establishing electrical connections between the different sides of the chip carrier leading to a more reliable device production process.
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Regarding claim 2; Pierson in view of Hu in further view Daubenspeck in further view of Hashemi teach all the limitations of the chip module of claim 1.
Further, Pierson teaches wherein the plurality of regions (Pierson: Annotated Fig (7) shared in this OA: Plurality of Regions) are at least three regions.
Regarding claim 3; Pierson in view of Hu in further view Daubenspeck in further view of Hashemi teach all the limitations of the chip module of claim 1.
However, Pierson does not teach wherein the electrically conductive adhesive does not electrically connect the regions of the contact layer.
Hu teaches wherein the electrically conductive adhesive (Hu: Fig (9): 400a, 400b) does not electrically connect the regions of the contact layer (110a).
Pierson and Hu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson by ensuring that the conductive adhesive does not electrically connect regions of the contact layer as disclosed in Hu to lower the chances of short circuits and improve the longevity and reliability of the electronic device.
Regarding claim 5; Pierson in view of Hu in further view Daubenspeck in further view of Hashemi teaches all the limitations of the chip module of claim 1.
Further, Pierson teaches wherein the chip (Pierson: Fig (5): 23) has a length and/or a width that is greater than a length and/or a width of the contact layer (7), and the chip (23) covers the contact layer (7).
Regarding claim 6; Pierson in view of Hu in further view Daubenspeck in further view of Hashemi teaches all the limitations of the chip module of claim 1.
Further, Pierson teaches wherein the chip (Pierson: Annotated Fig (7) shared in this OA: 23) and contact layer (7) are centered with respect to each other, a surface of the contact layer (7) is defined by a plurality of outer edges of the plurality of regions (Plurality of Regions)
Regarding claim 8; Pierson in view of Hu in further view Daubenspeck in further view of Hashemi teach all the limitations of the chip module of claim 1.
Further, Pierson teaches that the plated-through hole (Pierson: Fig (1): 5,6) has a soldering surface and/or a solder ball (29) on the underside of the chip carrier (3).
Regarding claim 17; Pierson in view of Hu in further view Daubenspeck in further view of Hashemi teaches all the limitations of the chip module of claim 1.
However, Pierson does not teach wherein the chip is one of a plurality of chips.
Hu teaches wherein the chip is one of a plurality of chips (Hu: [0027]: “… thereby improving the connection precision, achieving batch production of the second through holes and setting a plurality of chips in batches, and greatly improving production efficiency.”).
Pierson and Hu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson by using multiple chips as disclosed in Hu to improve the efficiency of the construction process and the density of the chips in the device.
Regarding claim 18; Pierson teaches a sensor, comprising:
a chip module including a chip (Pierson: Fig (7): 23) having a front side and a rear side (Col.3 lines 20-50);
a chip carrier (3) having an upper side facing the chip (23);
a contact layer (7) formed of an electrically conductive material and arranged on the upper side of the chip carrier (3) between the rear side of the chip (23) and the upper side of the chip carrier (3);
an electrically conductive adhesive arranged on an upper side of the contact layer facing the chip, the electrically conductive adhesive connecting the upper side of the contact layer and the rear side of the chip,
the contact layer (7) has a plurality of regions electrically insulated from each other and each electrically connected to the chip by the electrically conductive adhesive,
at least two of the plurality of regions have a plated-through hole (Fig (1): 5) extending from the upper side of the chip carrier (3) to an underside of the chip carrier (3),
the contact layer (7) and the electrically conductive adhesive fill the plated-through hole (5);
an electrically non-conductive adhesive arranged between the chip carrier and the chip and connecting the upper side of the chip carrier to the rear side of the chip,
the electrically non- conductive adhesive is arranged on the contact layer and between the electrically conductive adhesive on the regions of the contact layer;
a passivation applied over at least a portion of the chip module, the passivation includes an underfill that is a polymer,
the underfill flows between the chip and the chip carrier to fill a space between the chip and the chip carrier and fix the chip to the chip carrier,
an electrical contact element arranged on both the upper side and the underside of the chip carrier; and
a bonding wire electrically connecting the front side of the chip to the electrical contact element.
Pierson’s embodiment of Fig. (7) lacks an electrically conductive adhesive arranged on an upper side of the contact layer facing the chip, the electrically conductive adhesive connecting the upper side of the contact layer and the rear side of the chip, nor the electrically conductive adhesive filling the plated-through hole.
However, Pierson discloses in their specifications (see col 3 lines 46-50 of Pierson’s specifications: “For some applications, the copper plated vias could then be filled with a conductive adhesive composition, if necessary, but the arrangements shown in FIGS. 5 and 7 use a different approach.”). Given this description disclosed by Pierson and combining this description with Figs (1) and (7) of Pierson, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify the first embodiment disclose din Pierson by using an electrically conductive adhesive as suggested by Pierson to lead to both the contact layer (7) and the conductive adhesive filling the plated-through via and establishing an electrical connection between the chip (23) at the top of the carrier (3) and the bottom of the carrier and that such a choice of a conductive adhesive would be suitable for certain processing conditions making the process more efficient.
Pierson does not teach an electrically non-conductive adhesive arranged between the chip carrier and the chip and connecting the upper side of the chip carrier to the rear side of the chip, the electrically non- conductive adhesive is arranged on the contact layer and between the electrically conductive adhesive on the regions of the contact layer.
However, Hu teaches an electrically non-conductive adhesive (Hu: Fig(9): 300, [0062]: “… and the insulating medium 300 (adhesive film) is provided with an additional through hole communicating with the first openings 120c of the connection through holes 120a, 120b.”) arranged between the chip carrier (100) and the chip (200) and connecting the upper side of the chip carrier (100) to the rear side of the chip (200), the electrically non- conductive adhesive (300) is arranged on the contact layer (110a) and between the electrically conductive adhesive (400a, 400b) on the regions of the contact layer (110a).
Pierson and Hu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson by introducing the non-conductive adhesive disclosed in Hu to enhance the attachment of the chip to the chip carrier to avoid any possibility of mechanical damage if the device was to experience any mechanical stress.
Pierson in view of Hu does not teach a passivation applied over at least a portion of the chip module, the passivation includes an underfill that is a polymer, the underfill flows between the chip and the chip carrier to fill a space between the chip and chip carrier and fix the chip to the chip carrier.
Daubenspeck teaches a passivation (Daubenspeck: Fig (5): 20) applied over at least a portion of the chip module (10), the passivation includes an underfill (20) that is a polymer, the underfill flows ([0030]) between the chip (10) and the chip carrier (22) to fill a space between the chip (10) and chip carrier (22) and fix the chip (10) to the chip carrier (22, [0030]).
Pierson in view of Hu and Daubenspeck are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu by adding the passivation underfill layer flowing between the chip and the chip carrier as disclosed in Duabenspeck to improve the insulation of the chip from the carrier and to enhance the adhesion of the chip to the carrier leading to a more reliable device.
Pierson in view of Hu in further view of Daubenspeck does not teach an electrical contact element arranged on both the upper side and the underside of the chip carrier; and
a bonding wire electrically connecting the front side of the chip to the electrical contact element.
Hashemi teaches an electrical contact element (Hashemi: Fig (8): 837+864+847) arranged on both the upper side and the underside of the chip carrier (820); and
a bonding wire (860) electrically connecting the front side of the chip (812) to the electrical contact element (837+864+847).
Pierson in view of Hu in further view of Daubenspeck and Hashemi are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck by connecting the chip to the contact element as disclosed in Hashemi to facilitate establishing electrical connections between the different sides of the chip carrier leading to a more reliable device production process.
Regarding claim 27; Pierson in view of Hu in further view of Duabenspeck in further view of Hashemi teach all the limitations of chip module of claim 1.
However, Pierson in view of Hu in further view of Duabenspeck does not teach wherein the bonding wire is connected to one of the regions of the contact layer that does not have the electrically conductive adhesive.
Hashemi teaches wherein the bonding wire (Hashemi: Fig (8): 860) is connected to one of the regions of the contact layer (837+864+847) that does not have the electrically conductive adhesive.
Pierson in view of Hu in further view of Duabenspeck and Hashemi are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Duabenspeck by connecting the bonding wire to a region of the contact layer that does not contain conductive adhesive as disclosed in Hashemi to expand the reach of the electrical connections in the device allowing for more parts to be connected leading to a better performing device.
Regarding claim 28; Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi teaches all the limitations of the chip module of claim 1.
However, Pierson in view of Hu in further view of Daubenspeck does not teach wherein the contact element extends though the chip carrier, the contact element includes an upper contact surface arranged on the upper side of the chip carrier, a lower soldering surface arranged on the underside of the chip carrier, and a plated- through hole between the upper contact surface and the lower soldering surface, the plated- through hole electrically connects the upper contact surface to the lower soldering surface.
Hashemi teaches wherein the contact element (Hashemi: Fig (8): 837+864+847) extends though the chip carrier (820), the contact element (837+864+847) includes an upper contact surface (864) arranged on the upper side of the chip carrier (820), a lower soldering surface (847) arranged on the underside of the chip carrier (820), and a plated- through hole (hole containing 837) between the upper contact surface (864) and the lower soldering surface (847), the plated- through hole (hole containing 837) electrically connects the upper contact surface (864) to the lower soldering surface (847).
Pierson in view of Hu in further view of Daubenspeck and Hashemi are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck by using the contact element disclosed in Hashemi to facilitate establishing electrical connections between the top surface and bottom surface of the chip carrier leading to a more reliable device construction process.
Regarding claim 29; Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi teach all the limitations of the chip module of claim 28
Pierson in view of Hu in further view of Daubenspeck does not teach wherein the bonding wire electrically connects the front side of the chip to the upper contact surface, a solder ball is connected to the lower soldering surface.
Hashemi teaches wherein the bonding wire (Hashemi: Fig (8): 860) electrically connects the front side of the chip (812) to the upper contact surface (864), a solder ball (855) is connected to the lower soldering surface (847).
Pierson in view of Hu in further view of Daubenspeck and Hashemi are are considered analogous art. Thus, it would have been obvious, prior to the effective filing date f the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck by using a solder ball on the lower soldering surface as disclosed in Hashemi to facilitate connecting the chip carrier electrically to other components in the device making the device production process more reliable.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Pierson et al, US 6774315 B1 (Pierson) in view of Hu et al, US 20190295982 A1 (Hu) in further view of Daubenspeck et al, US 20100038780 A1 (Daubenspeck) in further view of Hashemi, US 20020149102 A1 (Hashemi) in further view of Watanabe et al, US 20210092835 A1 (Watanabe).
Regarding claim 16; Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi teach all the limitations of the chip module of claim 1.
However, Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi does not teach wherein the chip has a length greater than or equal to 1 mm and less than or equal to 200 mm, and/or the chip has a width greater than or equal to 1.5 mm and less than or equal to 200 mm.
Watanabe teaches wherein the chip has a length greater than or equal to 1 mm and less than or equal to 200 mm, and/or the chip has a width greater than or equal to 1.5 mm and less than or equal to 200 mm (Watanabe: [0064]: “… The dimensions of the first chip surface 21 are not particularly limited but may fall within the range from 3 mm×3 mm to 20 mm×20 mm, for example. That is to say, each side of the first chip surface 21 may have a length falling within the range from 3 mm to 20 mm, for example.”).
Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi and Watanabe are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi by using the dimensions of the chips disclosed in Watanabe to be able to use the technique disclosed in Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi with a variety of chips of different sizes to broaden the versatility of the technique making manufacturing chips more efficient.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Pierson et al, US 6774315 B1 (Pierson) in view of Hu et al, US 20190295982 A1 (Hu) as applied to claim 1 above, in further view of Daubenspeck et al, US 20100038780 A1 (Daubenspeck) in further view of Hashemi, US 20020149102 A1 (Hashemi) in further view of Fillion, US 20190304910 A1 (Fillion).
Regarding claim 10; Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi teach all the limitations of the chip module of claim 1.
Further, Pierson teaches wherein the electrically conductive adhesive is arranged between the plated-through hole (Pierson: Fig (1): 5,6) and the rear side of the chip (23)
However, Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi does not teach wherein the electrically conductive adhesive is arranged between the plated-through hole and the rear side of the chip.
Fillion teaches wherein the electrically conductive adhesive (Fillion: Annotated Fig (15) shared in this OA: 82) is arranged between the plated through-hole (44) and the rear side of the chip (74).
Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi and Fillion are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi by including the conductive adhesive layer disclosed in Fillion to increase the ductile properties of the bonding material making the bonds less brittle and less prone to damage under mechanical stress.
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Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Pierson et al, US 6774315 B1 (Pierson) in view of Hu et al, US 20190295982 A1 (Hu) in further view of Daubenspeck et al, US 20100038780 A1 (Daubenspeck) in further view of Hashemi, US 20020149102 A1 (Hashemi) in further view of Pueschner et al, US 20140021264 A1 (Pueschner).
Regarding claim 4; Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi teach all the limitations of the chip module of claim 1.
However, Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi does not teach wherein the chip has a length and/or a width that is less than a length and/or a width of the contact layer, and the contact layer protrudes beyond the chip.
Pueschner teaches that the chip (Pueschner: Fig (2A): 202) has a length and/or a width that is less than a length and/or a width of the contact layer (204, 205), and the contact layer (204, 205) protrudes beyond the chip (202).
Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi and Pueschner are considered analogous art given that they both disclose inventions in semiconductor device construction. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi by using the dimensions and configuration disclosed in Pueschner which is a known alternative that would have been expected to perform equally well for the benefit of ease of connecting the leads of the chip to their proper positions on the carrier.
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Claims 12-13 and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Pierson et al, US 6774315 B1 (Pierson) in view of Hu et al, US 20190295982 A1 (Hu) in further view of Daubenspeck et al, US 20100038780 A1 (Daubenspeck) in further view of Hashemi, US 20020149102 A1 (Hashemi) in further view of Ghahremani, US 20190293923 A1 (Ghahremani).
Regarding claim 12; Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi teach all the limitations of the chip module of claim 1.
However, Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi does not teach further comprising a housing arranged on the upper side of the chip carrier, the housing enclosing the chip and the contact layer.
Ghahremani teaches a housing (Ghahremani: Fig (2A): 202) arranged on the upper side of the chip carrier (201), the housing enclosing the chip (205) and the contact layer (206).
Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi and Ghahremani are considered analogous art given that they both disclose inventions in semiconductor device construction. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi by including a housing for the chip as disclosed by Ghahremani for the benefit of providing protection for the chip.
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Regarding claim 13; Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi in further view of Gharemani teach all the limitations of the chip module of claim 12.
However, Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi does not teach wherein the housing has an optical window on the front side of the chip.
Ghahremani teaches the housing (Ghahermani: Fig (2A): 202) has an optical window (203, [0081]) on the front side of the chip (205).
Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi and Ghahremani are considered analogous art given that they both disclose inventions in semiconductor device construction. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi by adding a housing such as the one disclosed in Ghahremani that includes an optical window for the benefit of expanding the diversity of uses of the chips to include the use of light as a signal for the operation of the chip.
Regarding claim 25; Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi in further view of Ghahremani teach all the limitations of the chip module of claim 12.
However, Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi does not teach wherein the housing is an epoxy-based potting.
Ghahremani teaches wherein the housing (Ghahermani: Fig (14): 1424) is an epoxy-based potting ([0124]: “… For example, the encapsulant may be 1424 a mold compound, a liquid epoxy, a gel, a soft epoxy, or a soft encapsulant, and may be silicone-based”).
Pierson in view Hu in further view of Daubenspeck in further view of Hashemi and Ghahermani are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi by using the epoxy encapsulant disclosed in Ghahermani to improve the protection of the device against mechanical damage.
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Regarding claim 26; Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi in further view of Ghahremani teach all the limitations of the chip module of claim 25.
However, Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi does not teach wherein the bonding wire is embedded in the housing.
Ghahremani teaches wherein the bonding wire (Ghahermani: Fig (14): 1407) is embedded in the housing (1424).
Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi and Ghahremani are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck in further view of Hashemi by embedding the bonding wire in the housing as disclosed in Ghahremani to increase the strength of the mechanical connection of the bonding wire to make it more resilient towards mechanical stress thus leading to a more reliable device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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