DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 01/16/2026 amendments of claims 1 and 18 are noted and entered.
The 01/16/2026 addition of claims 26-27 is noted and entered.
The 01/16/2026 cancellation of claim 15 is noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 6-9, filed 01/16/2026, with respect to the rejection(s) of claim(s) 1-6, 8, 10, 12-13, 15-18 and 25 under 35 U.S.C. 103 have been fully considered and are persuasive. However, the examiner would like to point out that the rejection of claim 15 was omitted from the Final Rejection filed on 11/26/2025 by accident, and not as an indication of containing allowable subject matter. Thus, the rejections below detail the examiner’s position regarding the amended claims of the instant application. Additionally, upon further consideration, a new ground(s) of rejection is made in view of Tamura et al, WO 2010035864 A1 (Tamura).
New Grounds for Rejection
New grounds for rejection, prior art reference Tamura et al, WO 2010035864 A1 (Tamura) appear below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6, 8, 17-18 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Pierson et al, US 6774315 B1 (Pierson) in view of Hu et al, US 20190295982 A1 (Hu) in further view of Daubenspeck et al, US 20100038780 A1 (Daubenspeck) in further view of Tamura et al, WO 2010035864 A1 (Tamura).
Regarding claim 1; Pierson teaches a chip module, comprising: a chip (23) having a front side and a rear side (Col.3 lines 20-50 and (23) in Figure (7)); a chip carrier (3) having an upper side facing the chip (23); a contact layer (7) formed of an electrically conductive material and arranged on the upper side of the chip carrier (3) between the rear side of the chip (23) and the upper side of the chip carrier (3); the contact layer (7) has a plurality of regions electrically insulated from each other, at least two of the plurality of regions have a plated-through hole (5) extending from the upper side of the chip carrier (3) to an underside of the chip carrier (3).
Pierson’s embodiment of Fig. (7) lacks an electrically conductive adhesive arranged on an upper side of the contact layer facing the chip, the electrically conductive adhesive connecting the upper side of the contact layer and the rear side of the chip, nor the electrically conductive adhesive filling the plated-through hole. However, Pierson discloses in their specifications (see col 3 lines 46-50 of Pierson’s specifications: “For some applications, the copper plated vias could then be filled with a conductive adhesive composition, if necessary, but the arrangements shown in FIGS. 5 and 7 use a different approach.”). Given this description disclosed by Pierson and combining this description with Figs (1) and (7) of Pierson, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify the first embodiment disclose din Pierson by using an electrically conductive adhesive as suggested by Pierson to lead to both the contact layer (7) and the conductive adhesive filling the plated-through via and establishing an electrical connection between the chip (23) at the top of the carrier (3) and the bottom of the carrier and that such a choice of a conductive adhesive would be suitable for certain processing conditions making the process more efficient.
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Pierson does not teach an electrically non-conductive adhesive arranged between the chip carrier and the chip and connecting the upper side of the chip carrier to the rear side of the chip, the electrically non- conductive adhesive is arranged on the contact layer and between the electrically conductive adhesive on the regions of the contact layer.
However, Hu teaches an electrically non-conductive adhesive (300) (see paragraph [0062] of the specifications of Hu: “[0062]… and the insulating medium 300 (adhesive film) is provided with an additional through hole communicating with the first openings 120c of the connection through holes 120a, 120b.”) arranged between the chip carrier (100) and the chip (200) and connecting the upper side of the chip carrier (100) to the rear side of the chip (200), the electrically non- conductive adhesive (300) is arranged on the contact layer (110a) and between the electrically conductive adhesive ((400a) and (400b)) on the regions of the contact layer (110a). Pierson and Hu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson by introducing the non-conductive adhesive disclosed in Hu to enhance the attachment of the chip to the chip carrier to avoid any possibility of mechanical damage if the device was to experience any mechanical stress.
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Pierson in view of Hu teach all the above disclosed subject matter.
However, Pierson in view of Hu does not teach a passivation applied over at least a portion of the chip module, the passivation includes an underfill that is a polymer, the underfill flows between the chip and the chip carrier to fill a space between the chip and chip carrier and fix the chip to the chip carrier.
Daubenspeck teaches a passivation (20) applied over at least a portion of the chip module (10), the passivation includes an underfill (20) that is a polymer, the underfill flows (see paragraph [0030] of Daubenspeck) between the chip (10) and the chip carrier (220 to fill a space between the chip (10) and chip carrier (22) and fix the chip (10) to the chip carrier (22) (see paragraph [0030] of the specifications of Daubenspeck). Pierson in view of Hu and Daubenspeck are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu by adding the passivation underfill layer flowing between the chip and the chip carrier as disclosed in Duabenspeck to improve the insulation of the chip from the carrier and to enhance the adhesion of the chip to the carrier leading to a more reliable device.
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Pierson in view of Hu in view of Daubenspeck teach all the above disclosed subject matter.
However, Pierson in view of Hu in further view of Daubenspeck does not teach an electrical contact element and a bonding wire electrically connecting the front side of the chip to the electrical contact element.
Tamura teaches an electrical contact element (Contact Element – see annotated fig (5) part 18 shared in this OA for convenience) and a bonding wire (4) electrically connecting the front side of the chip (2) to the electrical contact element (Contact Element – see annotated fig (5) part 18 shared in this OA). Pierson in view of Hu in further view of Daubenspeck and Tamura are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck by introducing the contact element and the bonding wire disclosed in Tamura to make establishing an electrical connection between the front face of the chip and the rest of the device easier leading to a more efficient device production process.
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Regarding claim 2; Pierson in view of Hu in further view Daubenspeck in further view of Tamura teach all the limitations of claim 1.
Further, Pierson teaches wherein the plurality of regions are at least three regions (see Figs (5) and (7) of Pierson).
Regarding claim 3; Pierson in view of Hu in further view Daubenspeck in further view of Tamura teach all the limitations of claim 1.
However, Pierson and Duabnespeck and Tamura do not teach wherein the electrically conductive adhesive does not electrically connect the regions of the contact layer.
Hu teaches wherein the electrically conductive adhesive ((400a) and (400b)) does not electrically connect the regions of the contact layer (110a). Pierson and Daubenspeck and Tamura and Hu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson and Daubenspeck and Tamura by ensuring that the conductive adhesive does not electrically connect regions of the contact layer as disclosed in Hu to lower the chances of short circuits and improve the longevity and reliability of the electronic device.
Regarding claim 5; Pierson in view of Hu in further view Daubenspeck in further view of Tamura teach all the limitations of claim 1.
Further, Pierson teaches wherein the chip (23) has a length and/or a width that is greater than a length and/or a width of the contact layer (7), and the chip (23) covers the contact layer (7) (see Fig (5) of Pierson).
Regarding claim 6; Pierson in view of Hu in further view Daubenspeck in further view of Tamura teach all the limitations of claim 1.
Further, Pierson teaches wherein the chip (23) and contact layer (7) are centered with respect to each other, a surface of the contact layer (7) is defined by a plurality of outer edges of the plurality of regions (see Fig (5) of Pierson).
Regarding claim 8; Pierson in view of Hu in further view Daubenspeck in further view of Tamura teach all the limitations of claim 1.
Further, Pierson teaches that the plated-through hole (5)+(6) has a soldering surface and/or a solder ball (29) on the underside of the chip carrier (3).
Regarding claim 17; Pierson in view of Hu in further view Daubenspeck in further view of Tamura teach all the limitations of claim 1.
However, Pierson and Daubenspeck and Tamura do not teach wherein the chip is one of a plurality of chips.
Hu teaches wherein the chip is one of a plurality of chips (see paragraph [0027] of the specification of Hu: “[0027]… thereby improving the connection precision, achieving batch production of the second through holes and setting a plurality of chips in batches, and greatly improving production efficiency.”). Pierson and Daubenspeck and Tamura and Hu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson and Daubenspeck and Tamura by using multiple chips as disclosed in Hu to improve the efficiency of the construction process and the density of the chips in the device.
Regarding claim 18; Pierson teaches a chip module including a chip (23) having a front side and a rear side (Col.3 lines 20-50), a chip carrier (3) having an upper side facing the chip (Figs (5) and (7)), a contact layer formed (7) of an electrically conductive material (claim 4) and arranged on the upper side of the chip carrier (3) between the rear side of the chip (23) and the upper side of the chip carrier (3);
Pierson’s embodiment appears to show the contact layer (7) has a plurality of regions electrically insulated from each other and each electrically connected to the chip by the electrically conductive adhesive. However, the feature is shown elsewhere as well, such as Pierson’s ((5) in Fig. 5) which discloses separate connection points for the electric leads of the chip. Therefore, it would have been obvious, prior to the effective filing date of the instant application, to a person of ordinary skill in the art, to modify the first embodiment of Pierson to have the contact leads electrically isolated from each other as disclosed in other embodiments in Pierson so that the leads can receive different signals ensuring the proper functionality of the device.
Pierson’s embodiment of Fig. (7) lacks an electrically conductive adhesive arranged on an upper side of the contact layer facing the chip, the electrically conductive adhesive connecting the upper side of the contact layer and the rear side of the chip, nor the electrically conductive adhesive filling the plated-through hole. However, Pierson discloses in their specifications (see col 3 lines 46-50 of Pierson’s specifications: “For some applications, the copper plated vias could then be filled with a conductive adhesive composition, if necessary, but the arrangements shown in FIGS. 5 and 7 use a different approach.”). Given this description disclosed by Pierson and combining this description with Figs (1) and (7) of Pierson, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify the first embodiment disclose din Pierson by using an electrically conductive adhesive as suggested by Pierson to lead to both the contact layer (7) and the conductive adhesive filling the plated-through via and establishing an electrical connection between the chip (23) at the top of the carrier (3) and the bottom of the carrier and that such a choice of a conductive adhesive would be suitable for certain processing conditions making the process more efficient.
Pierson does not teach an electrically non-conductive adhesive arranged between the chip carrier and the chip and connecting the upper side of the chip carrier to the rear side of the chip, the electrically non- conductive adhesive is arranged on the contact layer and between the electrically conductive adhesive on the regions of the contact layer.
However, Hu teaches an electrically non-conductive adhesive (300) (see paragraph [0062] of the specifications of Hu: “[0062]… and the insulating medium 300 (adhesive film) is provided with an additional through hole communicating with the first openings 120c of the connection through holes 120a, 120b.”) arranged between the chip carrier (100) and the chip (200) and connecting the upper side of the chip carrier (100) to the rear side of the chip (200), the electrically non- conductive adhesive (300) is arranged on the contact layer (110a) and between the electrically conductive adhesive ((400a) and (400b)) on the regions of the contact layer (110a). Pierson and Hu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson by introducing the non-conductive adhesive disclosed in Hu to enhance the attachment of the chip to the chip carrier to avoid any possibility of mechanical damage if the device was to experience any mechanical stress.
Pierson in view of Hu teach all the above disclosed subject matter.
However, Pierson in view of Hu does not teach a passivation applied over at least a portion of the chip module, the passivation includes an underfill that is a polymer between the chip and the chip carrier that fills a space and fixes between the chip and the chip carrier.
Daubenspeck teaches a passivation (20) applied over at least a portion of the chip module (10), the passivation includes an underfill (20) that is a polymer, the underfill flows (see paragraph [0030] of Daubenspeck) between the chip (10) and the chip carrier (220 to fill a space between the chip (10) and chip carrier (22) and fix the chip (10) to the chip carrier (22) (see paragraph [0030] of the specifications of Daubenspeck). Pierson in view of Hu and Daubenspeck are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu by adding the passivation underfill layer flowing between the chip and the chip carrier as disclosed in Duabenspeck to improve the insulation of the chip from the carrier and to enhance the adhesion of the chip to the carrier leading to a more reliable device.
Pierson in view of Hu in view of Daubenspeck teach all the above disclosed subject matter.
However, Pierson in view of Hu in further view of Daubenspeck does not teach an electrical contact element and a bonding wire electrically connecting the front side of the chip to the electrical contact element.
Tamura teaches an electrical contact element (Contact Element – see annotated fig (5) part 18 shared in this OA for convenience) and a bonding wire (4) electrically connecting the front side of the chip (2) to the electrical contact element (Contact Element – see annotated fig (5) part 18 shared in this OA). Pierson in view of Hu in further view of Daubenspeck and Tamura are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck by introducing the contact element and the bonding wire disclosed in Tamura to make establishing an electrical connection between the front face of the chip and the rest of the device easier leading to a more efficient device production process.
Regarding claim 27; Pierson in view of Hu in further view of Duabenspeck in further view of Tamura teach all the limitations of claim 1.
However, Pierson in view of Hu in further view of Duabenspeck does not teach wherein the bonding wire is connected to one of the regions of the contact layer that does not have the electrically conductive adhesive.
Tamura teaches wherein the bonding wire (4) is connected to one of the regions of the contact layer (Contact Element – see annotated Fig (5) part 18 of Tamura shared in this OA) that does not have the electrically conductive adhesive. Pierson in view of Hu in further view of Duabenspeck and Tamura are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Duabenspeck by connecting the bonding wire to a region of the contact layer that does not contain conductive adhesive to expand the reach of the electrical connections in the device allowing for more parts to be connected leading to a better performing device.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Pierson et al, US 6774315 B1 (Pierson) in view of Hu et al, US 20190295982 A1 (Hu) in further view of Daubenspeck et al, US 20100038780 A1 (Daubenspeck) in further view of Tamura et al, WO 2010035864 A1 (Tamura) in further view of Watanabe et al, US 20210092835 A1 (Watanabe)
Regarding claim 16; Pierson in view of Hu in further view of Daubenspeck in further view of Tamura teach all the limitations of claim 1.
However, Pierson in view of Hu in further view of Daubenspeck in further view of Tamura does not teach wherein the chip has a length greater than or equal to 1 mm and less than or equal to 200 mm, and/or the chip has a width greater than or equal to 1.5 mm and less than or equal to 200 mm.
Watanabe teaches wherein the chip has a length greater than or equal to 1 mm and less than or equal to 200 mm, and/or the chip has a width greater than or equal to 1.5 mm and less than or equal to 200 mm (see paragraph [0064] of the specification of Watanabe: “… The dimensions of the first chip surface 21 are not particularly limited but may fall within the range from 3 mm×3 mm to 20 mm×20 mm, for example. That is to say, each side of the first chip surface 21 may have a length falling within the range from 3 mm to 20 mm, for example.”). Pierson in view of Hu in further view of Daubenspeck in further view of Tamura and Watanabe are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck in further view of Tamura by using the dimensions of the chips disclosed in Watanabe to be able to use the technique disclosed in Pierson in view of Hu in further view of Daubenspeck in further view of Tamura with a variety of chips of different sizes to broaden the versatility of the technique making manufacturing chips more efficient.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Pierson et al, US 6774315 B1 (Pierson) in view of Hu et al, US 20190295982 A1 (Hu) as applied to claim 1 above, in further view of Daubenspeck et al, US 20100038780 A1 (Daubenspeck) in further view of Tamura et al, WO 2010035864 A1 (Tamura) in further view of Fillion, US 20190304910 A1 (Fillion).
Regarding claim 10; Pierson in view of Hu in further view of Daubenspeck in further view of Tamura teach all the limitations of claim 1.
Further, Pierson teaches with the plated-through hole (5)+(6) and the rear side of the chip (23)
However, Pierson in view of Hu in further view of Daubenspeck in further view of Tamura does not teach wherein the electrically conductive adhesive is arranged between the plated-through hole and the rear side of the chip.
Fillion teaches the chip module of claim 1 wherein the electrically conductive adhesive (82) is arranged between the contact surface (52) (which goes through a via through-hole (44) and the contact pad (76) of the passive chip above the via. Pierson in view of Hu in further view of Daubenspeck in further view of Tamura and Fillion are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck in further view of Tamura by including the conductive adhesive layer disclosed in Fillion to increase the ductile properties of the bonding material making the bonds less brittle and less prone to damage under mechanical stress.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Pierson et al, US 6774315 B1 (Pierson) in view of Hu et al, US 20190295982 A1 (Hu) in further view of Daubenspeck et al, US 20100038780 A1 (Daubenspeck) in further view of Tamura et al, WO 2010035864 A1 (Tamura) in further view of Pueschner et al, US 20140021264 A1 (Pueschner).
Regarding claim 4; Pierson in view of Hu in further view of Daubenspeck in further view of Tamura teach all the limitations of claim 1.
However, Pierson in view of Hu in further view of Daubenspeck in further view of Tamura does not teach the dimensions of the chip being smaller than the contact layer.
Pueschner teaches that the chip has a length and/or a width that is less than a length and/or a width of the contact layer, and the contact layer protrudes beyond the chip (215 and 205 in Fig. 2A above). Pierson in view of Hu in further view of Daubenspeck in further view of Tamura and Pueschner are considered analogous art given that they both disclose inventions in semiconductor device construction. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck in further view of Tamura by using the dimesions and configuration disclosed in Pueschner which is a known alternative that would have been expected to perform equally well for the benefit of ease of connecting the leads of the chip to their proper positions on the carrier.
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Claims 12-13 and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Pierson et al, US 6774315 B1 (Pierson) in view of Hu et al, US 20190295982 A1 (Hu) in further view of Daubenspeck et al, US 20100038780 A1 (Daubenspeck) in further view of Tamura et al, WO 2010035864 A1 (Tamura) in further view of Ghahremani, US 20190293923 A1 (Ghahremani).
Regarding claim 12; Pierson in view of Hu in further view of Daubenspeck in further view of Tamura teach all the limitations of claim 1.
However, Pierson in view of Hu in further view of Daubenspeck in further view of Tamura does not teach further comprising a housing arranged on the upper side of the chip carrier, the housing enclosing the chip and the contact layer.
Ghahremani teaches a housing (202) arranged on the upper side of the chip carrier (201), the housing enclosing the chip and the contact layer (abstract and 202 in Fig. 2A). Pierson in view of Hu in further view of Daubenspeck in further view of Tamura and Ghahremani are considered analogous art given that they both disclose inventions in semiconductor device construction. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck in further view of Tamura by including a housing for the chip as disclosed by Ghahremani for the benefit of providing protection for the chip.
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Regarding claim 13; Pierson in view of Hu in further view of Daubenspeck in further view of Tamura in further view of Gharemani teach all the limitations of claim 12.
However, Pierson in view of Hu in further view of Daubenspeck in further view of Tamura does not teach wherein the housing has an optical window on the front side of the chip.
Ghahremani teaches the housing (202) has an optical window (203) on the front side of the chip (205) (see also paragraph 81 and 203 in Figure 2A). Pierson in view of Hu in further view of Daubenspeck in further view of Tamura and Ghahremani are considered analogous art given that they both disclose inventions in semiconductor device construction. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck in further view of Tamura by adding a housing such as the one disclosed in Ghahremani that includes an optical window for the benefit of expanding the diversity of uses of the chips to include the use of light as a signal for the operation of the chip.
Regarding claim 25; Pierson in view of Hu in further view of Daubenspeck in further view of Tamura in further view of Ghahremani teach all the limitations of claim 12.
However, Pierson in view of Hu in further view of Daubenspeck in further view of Tamura does not teach wherein the housing is an epoxy-based potting.
Ghahremani teaches wherein the housing (1424) is an epoxy-based potting (see paragraph [0124] of the specifications of Ghahermani: “[0124]… For example, the encapsulant may be 1424 a mold compound, a liquid epoxy, a gel, a soft epoxy, or a soft encapsulant, and may be silicone-based”). Pierson in view Hu in further view of Daubenspeck in further view of Tamura and Ghahermani are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck in further view of Tamura by using the epoxy encapsulant disclosed in Ghahermani to improve the protection of the device against mechanical damage.
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Regarding claim 26; Pierson in view of Hu in further view of Daubenspeck in further view of Tamura in further view of Ghahremani teach all the limitations of claim 25.
However, Pierson in view of Hu in further view of Daubenspeck and Ghahremani does not teach wherein the bonding wire is embedded in the housing.
Tamura teaches wherein the bonding wire (4) is embedded in the housing (3). Pierson in view of Hu in further view of Daubenspeck and Ghahremani and Tamura are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Pierson in view of Hu in further view of Daubenspeck and Ghahremani by embedding the bonding wire in the housing as disclosed in Tamura to increase the strength of the mechanical connection of the bonding wire to make it more resilient towards mechanical stress thus leading to a more reliable device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
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/MOATAZ KHALIFA/Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815