CTFR 17/522,342 CTFR 100840 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim and Specification Status The Examiner acknowledges the amendments to claims 1, 6, 9 and 16 in the Applicant’s response dated 12 February 2026. The claim amendments have been addressed below. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-6, 8-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ehren Mannebach et. al (US 2020/0219970 A1; hereinafter “Mannebach ” ) in view of Chung-Liang Hsinchu Cheng (US 2022/0293750 A1; hereinafter “Cheng”) . Regarding Claim 1 , Mannebach teaches an integrated circuit comprising: a base dielectric layer (392, Fig. 3D, para [0070] describes a dielectric layer being formed on an etch stop layer) a semiconductor device over the base dielectric layer (Fig. 3D, semiconductor device stack as seen pictured (see annotated Fig. 3D below)) and including a semiconductor material extending between a source region and a drain region (350A-350C and 360A-360C, Fig. 3A – Fig. 3D, para [0057] describes oxide nanowires, para [0063] describes a source or drain structure at ends of the first and second vertical arrangement of nanowires), and a sub fin beneath the semiconductor material (302, Fig. 3A-3D, para [0065] describes a fin structure wherein the nanowires are formed over (see annotated Fig. 3D below); a first dielectric layer adjacent to the sub fin of the semiconductor device (320A, Fig. 3A, para [0055] describes a trench isolation layer 320A which is adjacent to the sub fin 302) and a conductive contact in the base dielectric layer and contacting the source region or the drain region from beneath the source region or the drain region (396, Fig. 3D, para [0064] describes conductive contact structures coupled to the source or drain structures); wherein the sub fin includes a second dielectric layer (398, Fig. 3D, para [0070] describes an etch stop layer which may functionally be a second dielectric layer). PNG media_image1.png 700 700 media_image1.png Greyscale Mannebach fails to explicitly disclose wherein the sub fin includes a semiconductor layer, wherein the semiconductor layer is over the second dielectric layer, and a bottom surface of the second dielectric layer is directly on a dielectric region. However, Cheng discloses a similar integrated circuit, wherein the sub fin (SF, annotated Fig. 3H depicts a sub fin SF below a fin shaped portion of a semiconductor device 101) includes a semiconductor layer (120 and SL, annotated Fig. 3H, para [0043] describes semiconductor nanosheets 120 wherein a lowermost nanosheet comprises a semiconductor layer SL of the sub fin SF), wherein the semiconductor layer is over the second dielectric layer (SL and 131, Fig. 3D and annotated Fig. 3H, para [0048] describes a bottom dielectric layer 131 wherein semiconductor layer SL is over the second dielectric layer 131 as depicted in annotated Fig. 3H), and a bottom surface of the second dielectric layer is directly on a dielectric region (DR and 131, annotated Fig. 3H depicts wherein a bottom surface of the second dielectric layer 131 is on a dielectric region DR of a base dielectric layer 166 that extends into the fin structure). PNG media_image2.png 499 418 media_image2.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Mannebach with Cheng to further disclose a semiconductor device comprising a sub fin further comprising a semiconductor layer over a second dielectric layer, and a bottom surface of the second dielectric layer is directly on a dielectric region in order to provide the advantage of providing a dielectric region comprised of a material that may act as a bonding layer between an underlying base dielectric layer and a dielectric layer of a sub fin that is below a lowermost semiconductor layer (Cheng, para [0091]). Regarding Claim 2 , the combination of Mannebach and Cheng teaches the integrated circuit of claim 1, wherein the semiconductor material comprises one or more semiconductor nanoribbons (Mannebach, 350A-350D, 360A-360D, Fig. 3A-3D, para [0061] describes a vertical arrangement of nanowires 350A, 350B, 350C and oxide nanowires 360A, 360B, 360C, which serve the same function as the semiconductor nanoribbons of the instant application (see annotated Fig. 3D above)). Regarding Claim 3 , the combination of Mannebach and Cheng teaches the integrated circuit of claim 1, wherein the semiconductor material comprises a fin shape that extends above a top surface of the first dielectric layer (Mannebach, 350A-350D, 360A-360D, annotated Fig. 3D, para [0065] describes wherein the first vertical arrangement of nanowires is over a fin, can be seen extending above a top surface of the first dielectric layer). Regarding Claim 4 , the combination of Mannebach and Jacob teaches the integrated circuit of claim 1, wherein the semiconductor layer (Cheng, 120 and SL, annotated Fig. 3H, para [0043] describes semiconductor nanosheets 120 wherein a lowermost nanosheet comprises the semiconductor layer SL wherein the semiconductor nanosheets may be comprised of an Si or SiGe material) comprises a same material as the semiconductor material (Mannebach, para [0028] describes wherein nanowires of the present disclosure may be Si or SiGe nanowires wherein upon combining Mannebach with Cheng the nanowires and semiconductor layer would be comprised of a same material). Regarding Claim 5 , the combination of Mannebach and Cheng teaches the integrated circuit of claim 1, wherein the semiconductor layer is a single-crystalline semiconductor material (Cheng, 120 and SL, annotated Fig. 3H, para [0043] describes semiconductor nanosheets 120 wherein a lowermost nanosheet comprises the semiconductor layer SL wherein the semiconductor nanosheets may be a same material as a second semiconductor layer 116 wherein para [0031] describes second semiconductor layer 116 may be monocrystalline silicon). Regarding Claim 6 , the combination of Mannebach and Jacob teaches the integrated circuit of claim 1, wherein the source region or the drain region contacts the second dielectric layer and the semiconductor layer (Mannebach, para [0075] describes using a partial source or drain in reference to Fig. 3D, wherein the source or drain are formed in the openings of the nanowire/nanoribbon further putting them in contact with the semiconductor layer upon combining Mannebach with Cheng. Furthermore, it is described that deep trench formation on one of the source or drain side enables direct contact to a backside interconnect level which comprises the second dielectric layer of Mannebach, enabling contact of the source and/or drain region with the second dielectric layer and semiconductor layer through the backside interconnect layer (see annotated Fig. 3D II below) and further wherein source and drain regions 130 of Cheng contact the semiconductor layer SL and second dielectric layer 131 as shown in annotated Fig. 3H), and the dielectric region is part of the base dielectric layer (Cheng, DR and 166, annotated Fig. 3H, para [0073] describes a base dielectric layer 166 comprising the dielectric region DR wherein the dielectric region DR may be a layer resulting from an ALD process as described in para [0073] or may be an SiCN layer deposited first prior to a subsequent silicon oxide deposition for the remaining portion of the base dielectric layer 166 as described in para [0091]). PNG media_image3.png 615 701 media_image3.png Greyscale Regarding Claim 8 , the combination of Mannebach and Jacob teaches a printed circuit board comprising the integrated circuit of claim 1 (Mannebach, 1004, Fig. 10, para [0165], describes the processor 1004 of the computing device 1000 including the integrated circuit die which may include the embodiments of the present disclosure, wherein the processor is coupled to the board 1002 which can be a printed circuit board). Regarding Claim 9 , Mannebach teaches an electronic device, comprising: a base dielectric layer (392, Fig. 3D, para [0070] describes a dielectric layer being formed on an etch stop layer (see annotated Fig. 3D above)); a chip package comprising one or more dies (1004, Fig. 10, para [0165], describes the processor 1004 of the computing device 1000 including the integrated circuit die which may include the embodiments of the present disclosure), at least one of the one or more dies comprising a semiconductor device (Fig. 3D, semiconductor device stack as seen pictured) including a semiconductor material extending between a source region and a drain region (350A-350C and 360A-360C, Fig. 3A – Fig. 3D, para [0057] describes oxide nanowires, para [0063] describes a source or drain structure at ends of the first and second vertical arrangement of nanowires), and a sub fin beneath the semiconductor material (302, Fig. 3A-3D, para [0065] describes a fin structure wherein the nanowires are formed over (see annotated Fig. 3D above)); a first dielectric layer adjacent to the sub fin of the semiconductor device (320A, Fig. 3A, para [0055] describes a trench isolation layer 320A which is adjacent to the sub fin 302); and a conductive contact extending through an entire thickness of the base dielectric layer and in contact with the source region or the drain region from beneath the source region or the drain region (396, Fig. 3D, para [0064] describes conductive contact structures couples to the source or drain structures, and can be seen extending through an entire thickness of the base dielectric layer (see annotated Fig. 3D above)); wherein the sub fin includes a second dielectric layer (398, Fig. 3D, para [0070] describes an etch stop layer which may functionally be a second dielectric layer). Mannebach fails to explicitly disclose wherein the sub fin includes a semiconductor layer, and a dielectric region beneath the second dielectric layer, wherein the semiconductor layer is over the second dielectric layer, and wherein a bottom surface of the second dielectric layer is directly on the dielectric region. However, Cheng discloses a similar integrated circuit, wherein the sub fin (SF, annotated Fig. 3H depicts a sub fin SF below a fin shaped portion of a semiconductor device 101) includes a semiconductor layer (120 and SL, annotated Fig. 3H, para [0043] describes semiconductor nanosheets 120 wherein a lowermost nanosheet comprises a semiconductor layer SL of the sub fin SF), and a dielectric region beneath the second dielectric layer (DR and 131, annotated Fig. 3H, para [0048] describes a bottom dielectric layer 131 and annotated Fig. 3H depicts wherein a dielectric region DR is beneath the second dielectric layer 131) wherein the semiconductor layer is over the second dielectric layer (SL and 131, Fig. 3D and annotated Fig. 3H depicts wherein semiconductor layer SL is over the second dielectric layer 131), and wherein a bottom surface of the second dielectric layer is directly on the dielectric region (DR and 131, annotated Fig. 3H depicts wherein a bottom surface of the second dielectric layer 131 is on a dielectric region DR of a base dielectric layer 166 that extends into the fin structure). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Mannebach with Cheng to further disclose a semiconductor device comprising a sub fin further comprising a semiconductor layer over a second dielectric layer, and a bottom surface of the second dielectric layer is directly on a dielectric region in order to provide the advantage of providing a dielectric region comprised of a material that may act as a bonding layer between an underlying base dielectric layer and a dielectric layer of a sub fin that is below a lowermost semiconductor layer (Cheng, para [0091]). Regarding Claim 10 , the combination of Mannebach and Cheng teaches the electronic device of claim 9, wherein the semiconductor material comprises one or more semiconductor nanoribbons (Mannebach, 350A-350D, 360A-360D, Fig. 3A-3D, para [0061] describes a vertical arrangement of nanowires 350A, 350B, 350C and oxide nanowires 360A, 360B, 360C, which serve the same function as the semiconductor nanoribbons of the instant application (see annotated Fig. 3D above)). Regarding Claim 11 , the combination of Mannebach and Cheng teaches the electronic device of claim 9, wherein at least a portion of the sub fin is formed from the base dielectric layer (Mannebach, para [0070] describes wherein at least a portion of substrate 302 may be replaced with a base dielectric 392 wherein a portion of sub fin 302 would therefore be formed from base dielectric layer 392 below second dielectric layer 398). Regarding Claim 12 , the combination of Mannebach and Cheng teaches the electronic device of claim 9, wherein the semiconductor layer is a single-crystalline semiconductor material (Cheng, 120 and SL, annotated Fig. 3H, para [0043] describes semiconductor nanosheets 120 wherein a lowermost nanosheet comprises the semiconductor layer SL wherein the semiconductor nanosheets may be a same material as a second semiconductor layer 116 wherein para [0031] describes second semiconductor layer 116 may be monocrystalline silicon). Regarding Claim 13 , the combination of Mannebach and Cheng teaches the electronic device of claim 9, wherein the source region or the drain region contacts the second dielectric layer and the semiconductor layer (Mannebach, para [0075] describes using a partial source or drain in reference to Fig. 3D, wherein the source or drain are formed in the openings of the nanowire/nanoribbon further putting them in contact with the semiconductor layer upon combining Mannebach with Cheng. Furthermore, it is described that deep trench formation on one of the source or drain side enables direct contact to a backside interconnect level which comprises the second dielectric layer of Mannebach, enabling contact of the source and/or drain region with the second dielectric layer and semiconductor layer through the backside interconnect layer (see annotated Fig. 3D II below) and further wherein source and drain regions 130 of Cheng contact the semiconductor layer SL and second dielectric layer 131 as shown in annotated Fig. 3H). Regarding Claim 15 , the combination of Mannebach and Jacob teaches the electronic device of claim 9, further comprising a printed circuit board, wherein the chip package is attached to the printed circuit board (Mannebach, 1004, Fig. 10, para [0165], describes the processor 1004 of the computing device 1000 including the integrated circuit die which may include the embodiments of the present disclosure, wherein the processor is coupled to the board 1002 which can be a printed circuit board) . 07-21-aia AIA Claim s 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ehren Mannebach et. al (US 2020/0219970 A1; hereinafter “Mannebach ” ) in view of Chung-Liang Hsinchu Cheng (US 2022/0293750 A1; hereinafter “Cheng”) and in further view of Ajey P. Jacob et al. (US 2016/0071979 A1; hereinafter “Jacob”) . Regarding Claim 7, the combination of Mannebach and Cheng teaches the integrated circuit of claim 1, wherein the semiconductor layer has a thickness between about 10 nm and about 30 nm (Cheng, 120 and SL, annotated Fig. 3H, para [0047] describes wherein the semiconductor nanosheets 120 comprising the semiconductor layer SL may have a thickness between 2 and 20 nm wherein a thickness of 20 nm would fall within the range of 10 nm to about 30 nm). Mannebach and Cheng fail to explicitly disclose the integrated circuit of claim 1, wherein the second dielectric layer has a thickness between about 10 nm and about 20 nm. However, Jacob teaches a similar integrated circuit, wherein the second dielectric layer has a thickness between about 10 nm and about 20 nm (Jacob, 220, 225, 270. Fig. 2F, para [0025] describes wherein the implantation process 220 “may be a low energy implantation through the fin to a desirable depth below the fin surface (e.g., ~5-20 nm below the surface of the fin), resulting in an ion implant region 225 which is then converted into a dielectric layer 270, such as in the second dielectric layer of the instant application, further resulting in a second dielectric layer of about 5 nm to 20 nm). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Mannebach and Cheng with Jacob to further disclose a semiconductor device comprising a second dielectric layer having a thickness between about 10 nm and about 20 nm in order to provide the advantage of providing a dielectric region with adequate thickness so as to reduce punch through and leakage current between the source and drain (Jacob, para [0034]). Regarding Claim 14, the combination of Mannebach and Cheng teaches the integrated circuit of claim 9, wherein the semiconductor layer has a thickness between about 10 nm and about 30 nm (Cheng, 120 and SL, annotated Fig. 3H, para [0047] describes wherein the semiconductor nanosheets 120 comprising the semiconductor layer SL may have a thickness between 2 and 20 nm wherein a thickness of 20 nm would fall within the range of 10 nm to about 30 nm). Mannebach and Cheng fail to explicitly disclose the integrated circuit of claim 1, wherein the second dielectric layer has a thickness between about 10 nm and about 20 nm. However, Jacob teaches a similar integrated circuit, wherein the second dielectric layer has a thickness between about 10 nm and about 20 nm (Jacob, 220, 225, 270. Fig. 2F, para [0025] describes wherein the implantation process 220 “may be a low energy implantation through the fin to a desirable depth below the fin surface (e.g., ~5-20 nm below the surface of the fin), resulting in an ion implant region 225 which is then converted into a dielectric layer 270, such as in the second dielectric layer of the instant application, further resulting in a second dielectric layer of about 5 nm to 20 nm). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Mannebach and Cheng with Jacob to further disclose a semiconductor device comprising a second dielectric layer having a thickness between about 10 nm and about 20 nm in order to provide the advantage of providing a dielectric region with adequate thickness so as to reduce punch through and leakage current between the source and drain (Jacob, para [0034]) . 07-21-aia AIA Claim s 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Aaron D. Lilak et. al (US 2020/0294998 A1; hereinafter “Lilak”) in view of Chung-Liang Hsinchu Cheng (US 2022/0293750 A1; hereinafter “Cheng”) . Regarding Claim 16, Lilak discloses an integrated circuit comprising: a first semiconductor device (104, Fig. 1A, para [0013] describes a lower device region 104) including a first semiconductor material extending between a first source region and a first drain region (116A, Fig. 1A, para [0013] and para [0017] describe first nanowires 116A comprising semiconductor materials between a first source region 124A and a first drain region 124A), a first gate structure around the first semiconductor material (122A and 120A, Fig. 1A, para [0013] describes a lower gate structure 122A and 120A wrapped around first semiconductor material 116A); a second semiconductor device located vertically over the first semiconductor device (108, Fig. 1A, para [0013] describes an upper device region 108) and including a second semiconductor material extending between a second source region and a second drain region (116B, Fig. 1A, para [0013] and para [0017] describe second nanowires 116B comprising semiconductor materials between second drain region 124B and second source region 124B), and a second gate structure around the second semiconductor material (122B and 120B, Fig. 1A, para [0013] describes an upper gate structure 122B and 120B wrapped around second semiconductor material 116B); a gate isolation layer between the first gate structure and the second gate structure (106, annotated Fig. 1A, para [0013] describes an isolation region 106 comprising a gate isolation layer between the first gate structure and second gate structure); a first conductive contact in contact with the first source region or the first drain region from beneath the first source region or the first drain region (138, Fig. 1A, para [0013] and para [0028] describe source/drain contacts in contact with first source and drain regions 124A from beneath the first source region and the first drain region 124A in a backside contact region 103); and a second conductive contact in contact with the second source region or the second drain region from above the second source region or the second drain region (125, annotated Fig. 1A, para [0013] describes frontside contacts provided on the second source and second drain regions 124B). PNG media_image4.png 552 744 media_image4.png Greyscale Lilak fails to explicitly disclose a sub fin beneath the first semiconductor material and including a semiconductor layer over a dielectric layer, the sub fin further including a dielectric region beneath the dielectric layer, such that the dielectric layer is directly on a surface of the dielectric region. However, Cheng teaches a similar integrated circuit comprising a sub fin (SF, annotated Fig. 3H depicts a sub fin SF below a fin shaped portion of a semiconductor device 101) beneath the first semiconductor material (120 and SM, Fig. 2B and annotated Fig. 3H, para [0043] describes semiconductor nanosheets 120) and including a semiconductor layer (120 and SL, annotated Fig. 3H, para [0043] describes semiconductor nanosheets 120 wherein a lowermost nanosheet comprises a semiconductor layer SL of the sub fin SF) over a dielectric layer (SL and 131, Fig. 3D and annotated Fig. 3H, para [0048] describes a bottom dielectric layer 131 wherein semiconductor layer SL is over the second dielectric layer 131 as depicted in annotated Fig. 3H), the sub fin further including a dielectric region beneath the dielectric layer (DR and 131, annotated Fig. 3H depicts wherein a dielectric region DR of a base dielectric layer 166 that is beneath a dielectric layer 131), such that the dielectric layer is directly on a surface of the dielectric region (DR and 131, annotated Fig. 3H depicts wherein a bottom surface of the second dielectric layer 131 is directly on an upper surface of the dielectric region DR). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Mannebach with Cheng to further disclose a semiconductor device comprising a sub fin further comprising a semiconductor layer over a second dielectric layer, and a bottom surface of the second dielectric layer is directly on a dielectric region in order to provide the advantage of providing a dielectric region comprised of a material that may act as a bonding layer between an underlying base dielectric layer and a dielectric layer of a sub fin that is below a lowermost semiconductor layer (Cheng, para [0091]). Regarding Claim 17, the combination of Lilak and Cheng teaches the integrated circuit of claim 16, wherein the first semiconductor material and the second semiconductor material each comprises one or more semiconductor nanoribbons (Lilak, 116A and 116B, Fig. 1A, para [0013] describes upper and lower nanowires, wherein one or more of each can be seen pictured in Fig. 1A). Regarding Claim 18, the combination of Lilak and Cheng teaches the integrated circuit of claim 16, wherein the semiconductor layer is a single-crystalline semiconductor material (Cheng, 120 and SL, annotated Fig. 3H, para [0043] describes semiconductor nanosheets 120 wherein a lowermost nanosheet comprises the semiconductor layer SL wherein the semiconductor nanosheets may be a same material as a second semiconductor layer 116 wherein para [0031] describes second semiconductor layer 116 may be monocrystalline silicon). Regarding Claim 19, the combination of Lilak and Cheng teaches the integrated circuit of claim 16, wherein the first source region or the first drain region contacts the dielectric layer and the semiconductor layer (Cheng, 130, SL and 131, annotated Fig. 3H, para [0050] describes source and drain regions 130 in contact the semiconductor layer SL and second dielectric layer 131 as shown in annotated Fig. 3H) . 07-21-aia AIA Claim s 20 is rejected under 35 U.S.C. 103 as being unpatentable over Aaron D. Lilak et. al (US 2020/0294998 A1; hereinafter “Lilak”) in view of Chung-Liang Hsinchu Cheng (US 2022/0293750 A1; hereinafter “Cheng”) and in further view of Ajey P. Jacob et al. (US 2016/0071979 A1; hereinafter “Jacob”) . Regarding Claim 20, the combination of Lilak and Cheng teaches the integrated circuit of claim 16, wherein the semiconductor layer has a thickness between about 10 nm and about 30 nm (Cheng, 120 and SL, annotated Fig. 3H, para [0047] describes wherein the semiconductor nanosheets 120 comprising the semiconductor layer SL may have a thickness between 2 and 20 nm wherein a thickness of 20 nm would fall within the range of 10 nm to about 30 nm). Lilak and Cheng fail to explicitly disclose the integrated circuit of claim 1, wherein the second dielectric layer has a thickness between about 10 nm and about 20 nm. However, Jacob teaches a similar integrated circuit, wherein the second dielectric layer has a thickness between about 10 nm and about 20 nm (Jacob, 220, 225, 270. Fig. 2F, para [0025] describes wherein the implantation process 220 “may be a low energy implantation through the fin to a desirable depth below the fin surface (e.g., ~5-20 nm below the surface of the fin), resulting in an ion implant region 225 which is then converted into a dielectric layer 270, such as in the second dielectric layer of the instant application, further resulting in a second dielectric layer of about 5 nm to 20 nm). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Lilak and Cheng with Jacob to further disclose a semiconductor device comprising a second dielectric layer having a thickness between about 10 nm and about 20 nm in order to provide the advantage of providing a dielectric region with adequate thickness so as to reduce punch through and leakage current between the source and drain (Jacob, para [0034]). Response to Arguments Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion 07-40 AIA Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898 Application/Control Number: 17/522,342 Page 2 Art Unit: 2898 Application/Control Number: 17/522,342 Page 3 Art Unit: 2898 Application/Control Number: 17/522,342 Page 4 Art Unit: 2898 Application/Control Number: 17/522,342 Page 5 Art Unit: 2898 Application/Control Number: 17/522,342 Page 6 Art Unit: 2898 Application/Control Number: 17/522,342 Page 7 Art Unit: 2898 Application/Control Number: 17/522,342 Page 8 Art Unit: 2898 Application/Control Number: 17/522,342 Page 9 Art Unit: 2898 Application/Control Number: 17/522,342 Page 10 Art Unit: 2898 Application/Control Number: 17/522,342 Page 11 Art Unit: 2898 Application/Control Number: 17/522,342 Page 12 Art Unit: 2898 Application/Control Number: 17/522,342 Page 13 Art Unit: 2898 Application/Control Number: 17/522,342 Page 14 Art Unit: 2898 Application/Control Number: 17/522,342 Page 15 Art Unit: 2898 Application/Control Number: 17/522,342 Page 16 Art Unit: 2898 Application/Control Number: 17/522,342 Page 17 Art Unit: 2898
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