Prosecution Insights
Last updated: May 29, 2026
Application No. 17/526,072

LIGHT EMITTING DIODES HAVING A PLURALITY OF LIGHT EMITTING CELLS

Non-Final OA §103
Filed
Nov 15, 2021
Priority
Nov 30, 2016 — RE 10-2016-0161006 +4 more
Examiner
MIYOSHI, JESSE Y
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Seoul Viosys Co. Ltd.
OA Round
6 (Non-Final)
57%
Grant Probability
Moderate
6-7
OA Rounds
0m
Est. Remaining
76%
With Interview

Examiner Intelligence

Grants 57% of resolved cases
57%
Career Allowance Rate
272 granted / 480 resolved
-11.3% vs TC avg
Strong +19% interview lift
Without
With
+19.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
32 currently pending
Career history
537
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
76.2%
+36.2% vs TC avg
§102
15.3%
-24.7% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 480 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 1-9, 11-20 have been considered but are moot in view of the new grounds of rejection. Applicant argues that Emura discloses 17 and 16 are vertically aligned and there is no lateral offsets or staggered edges between the insulation layers and the light emitting element and does not teach the amended limitations. Examiner respectfully disagrees. As can be seen from the claim limitations, the claims do not recite which edges of the claimed elements are “inward of and spaced further from an edge of the first insulator.” As shown below in the labeled fig. 1B shows the edges of each element to read on the claims. Previous rejection has been maintained and is updated to include the amended portions. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-5, 7-9, 11, 12, and 14-20, is/are rejected under 35 U.S.C. 103, as best understood, as being unpatentable over Kamada et al. (US PGPub 2017/0030549; hereinafter “Kamada”) in view of Emura et al. (US PGPub 2017/0186915; hereinafter “Emura”). Re claim 1: Kamada teaches (e.g. figs. 1 and 9) a light emitting device (surface light source 100; e.g. paragraph 32), comprising: a support (base 10; e.g. paragraph 32); light emitters (light emitting elements 20; e.g. paragraph 32) disposed on the support (10), and wherein the light emitting device (100) further includes a first optic (lens 30; e.g. paragraph 32) disposed on the support (10) to be in contact with the support (10) and surrounding the light emitter (20). Kamada is silent as to explicitly teaching the light emitters include a light emitter includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer having a second conductivity type different from the first conductivity type; an active layer disposed between the first semiconductor layer and the second semiconductor layer; an ohmic layer disposed on the second semiconductor layer and in electrically contact with the second semiconductor layer; a first electrode electrically connected to the first semiconductor layer; a second electrode electrically connected to the second semiconductor layer; a first insulator covering the first electrode and the second electrode and including a first opening and a second opening exposing the first electrode and the second electrode, respectively; a second insulator disposed between the second semiconductor layer and the first insulator, an edge of the second insulator being located inward of and spaced farther from an edge of the first insulator than an edge of the light emitter; and a first pad and a second pad that are respectively electrically connected to the first electrode and the second electrode exposed through the first opening and the second opening of the first insulator, wherein the second insulator includes a first surface and a second surface opposite to the first surface, and wherein the second insulator includes a first portion and a second portion that have different thicknesses from each other and are disposed on a surface of the ohmic layer to be in contact with the ohmic layer, a thickness of the fist portion and a thickness of the second portion being distances between the first surface and the second surface in the first portion and the second portion in a vertical direction. Emura teaches (e.g. figs. 1A-C and labeled fig. 1B below) the light emitters include a light emitter (light emitting element 1; e.g. paragraph 36) includes: a first semiconductor layer (12n) having a first conductivity type (n-type layer 12n); a second semiconductor layer (12p) having a second conductivity type (p-type layer 12p) different from the first conductivity type; an active layer (12a) disposed between the first semiconductor layer (12n) and the second semiconductor layer (12p); an ohmic layer (13) disposed on the second semiconductor layer (12p) and in electrically contact with the second semiconductor layer (12p); a first electrode (149) electrically connected to the first semiconductor layer (12n); a second electrode (141) electrically connected to the second semiconductor layer (12p); a first insulator (17; e.g. paragraph 36) covering the first electrode (149) and the second electrode (141) and including a first opening (opening in 17 for 18n; hereinafter “1O”) and a second opening (opening in 17 for 18p; hereinafter “2O”) exposing the first electrode (149) and the second electrode (141), respectively; a second insulator (16; e.g. paragraph 36) disposed between the second semiconductor layer (12p) and the first insulator (17), an edge (edge labeled “2E” below) of the second insulator (16) being located inward of and spaced farther from an edge (edge labeled “1E” below) of the first insulator (17) than an edge (edge labeled “LEE” below) of the light emitter (1); and a first pad (18n) and a second pad (18p) that are respectively electrically connected to the first electrode (149) and the second electrode (141) exposed through the first opening (1O) and the second opening (2O) of the first insulator (17), wherein the second insulator (16) includes a first surface (upper surface of 16 above 13; hereinafter “1S”) and a second surface (upper surface of 16 of the portion of 16 which is in contact with the side surface of 13; hereinafter “2S”) opposite to the first surface (1S), and wherein the second insulator (16) including a first portion (portion of 16 proximate sidewalls of 13; hereinafter “1P”) and a second portion (horizontal portions of 16 over 13; hereinafter “2P”) that have different thicknesses from each other and are disposed on a surface of the ohmic layer (13) to be in contact with the ohmic layer (13), a thickness of the fist portion (1P) and a thickness of the second portion (2P) being distances between the first surface (1S) and the second surface (2S) in the first portion (1P) and the second portion (2P) in a vertical direction. PNG media_image1.png 724 778 media_image1.png Greyscale It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the light emitting element as taught by Emura in the device of Kamada since Kamada lacks any detail as to the structure of the light emitting element. The light emitting element of Emura provides a known structure which has improved light extraction efficiency and would improve the efficiency of the device of Kamada. Re claim 2: Kamada teaches the light emitting device of claim 1, further comprising a second optic (reflection film is preferably formed on the base 10; e.g. paragraph 49) is disposed between two light emitters (20) that are adjacent each other and having a shape extending along a surface of the support (10). Re claim 3: Kamada teaches the light emitting device of claim 1, wherein the first optic (30) includes a convex segment (30 has lobes of convex portion). Re claim 4: Kamada teaches the light emitting device of claim 1, wherein the light emitters (20) are arranged to be apart from one another by a predetermined distance (see predetermined distance as shown in fig. 14). Re claim 5 Kamada teaches the light emitting device of claim 1, wherein the first optic (30) includes a top surface that is apart from the support (10) Re claim 7: Kamada in view of Emura teaches the light emitting device of claim 1, wherein the second insulator (16) has a third opening (opening in 16 of Emura exposing upper surface of 12p within region 102; hereinafter “3O”) exposing the second semiconductor layer (12p of Emura in region 102 as shown in fig. 1C is exposed insomuch as fig. 29 of the instant application exposes 27 under 39a since the ohmic layer 31 is provided above the second semiconductor layer 27), the third opening (3O of Emura) not overlapping with the second opening (2O of Emura) of the first insulator (17 of Emura). Re claim 8: Kamada in view of Emura teaches the light emitting device of claim 7, wherein the first portion of the second insulator (1P of 16 of Emura) that contacts with the ohmic layer (13 of Emura) has a thickness different from the second portion of the second insulation layer (2P of 16 of Emura). Re claim 9: Kamada in view of Emura teaches the light emitting device of claim 1, wherein an edge of the second insulator (16 of Emura) extends in a direction away from an edge of the first semiconductor layer (12n of Emura) such that the edge of the second insulator (16 of Emura) is disposed on a side (in region of 12c of Emura) of the first semiconductor layer (12n of Emura). Re claim 11: Kamada teaches (e.g. figs. 1 and 9) a light emitting device (surface light source 100; e.g. paragraph 32), comprising: a support (base 10; e.g. paragraph 32); a light emitter (light emitting elements 20; e.g. paragraph 32); a first light guide region (lens 30; e.g. paragraph 32) disposed on the support (10) and surrounding the light emitter (20); and a second light guide region (reflection film is preferably formed on the base 10; e.g. paragraph 49) disposed on the support (10) to be on a side of the first light guide region (30) and having a height different from a height of the first light guide region (30). Kamada is silent as to explicitly teaching the light emitter including a first semiconductor layer disposed on the support, an active layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the active layer, and an ohmic layer disposed on the second semiconductor layer and in electrically contact with the second semiconductor layer; a first pad electrode electrically connected to the first semiconductor layer; a second pad electrode electrically connected to the second semiconductor layer; a first insulator covering the first pad electrode and the second pad electrode and including a plurality of openings exposing upper surfaces of the first pad electrode and the second pad electrode; a second insulator disposed between the second semiconductor layer and the first insulator, an edge of the second insulator being located inward of and spaced farther from an edge of the first insulator than an edge of the light emitter; a first bump pad and a second bump pad that are electrically connected to the first pad electrode and the second pad electrode exposed through the plurality of openings of the first insulator, wherein the second insulator includes a first surface and a second surface opposite to the first surface, and wherein the second insulator includes a first portion and a second portion that have different thicknesses from each other and are disposed on a surface of the ohmic layer to be in contact with the ohmic layer, a thickness of the fist portion and a thickness of the second portion being distances between the first surface and the second surface in the first portion and the second portion in a vertical direction. Emura teaches (e.g. figs. 1A-C and labeled fig. 1B below) the light emitter including a first semiconductor layer (12n) disposed on the support (10 of Kamada), an active layer (12a) disposed on the first semiconductor layer (12n), and a second semiconductor layer (12p) disposed on the active layer (12a), and an ohmic layer (13) disposed on the second semiconductor layer (12p) and in electrically contact with the second semiconductor layer (12p); a first pad electrode (149) electrically connected to the first semiconductor layer (12n); a second pad electrode (141) electrically connected to the second semiconductor layer (12p); a first insulator (17; e.g. paragraph 36) covering the first pad electrode (149) and the second pad electrode (141) and including a plurality of openings (see plural openings in fig. 1A similar to 149) exposing upper surfaces of the first pad electrode (149) and the second pad electrode (141); a second insulator (16; e.g. paragraph 36) disposed between the second semiconductor layer (12p) and the first insulator (17), an edge (edge labeled “2E” below) of the second insulator (16) being located inward of and spaced farther from an edge (edge labeled “1E” below) of the first insulator (17) than an edge (edge labeled “LEE” below) of the light emitter (1); a first bump pad (18n) and a second bump pad (18p) that are electrically connected to the first pad electrode (149) and the second pad electrode (141) exposed through the plurality of openings of the first insulator (17), wherein the second insulator (16) includes a first surface (upper surface of 16 above 13; hereinafter “1S”) and a second surface (upper surface of 16 of the portion of 16 which is in contact with the side surface of 13; hereinafter “2S”) opposite to the first surface (1S), and wherein the second insulator (16) includes a first portion (portion of 16 proximate openings 16n; hereinafter “1P”) and a second portion (horizontal portions of 16; hereinafter “2P”) that have different thicknesses from each other and are disposed on a surface of the ohmic layer (13) to be in contact with the ohmic layer (13), a thickness of the fist portion (1P) and a thickness of the second portion (2P) being distances between the first surface (1S) and the second surface (2S) in the first portion (1P) and the second portion (2P) in a vertical direction. It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the light emitting element as taught by Emura in the device of Kamada since Kamada lacks any detail as to the structure of the light emitting element. The light emitting element of Emura provides a known structure which has improved light extraction efficiency and would improve the efficiency of the device of Kamada. Re claim 12: Kamada teaches the light emitting device of claim 11, wherein a side view profile of the first light guide region (100) has a curved shape (lens 100 has a curved shape, as can be seen in fig. 30 of Kamada). Re claim 14: Kamada in view of Emura teaches the light emitting device of claim 1, wherein the second insulator (16) includes an additional opening (opening in 16 of Emura exposing upper surface of 12p within region 102 for 142) not overlapping with at least one of the plurality of openings of the first insulator (17 of Emura). Re claim 15: Kamada in view of Emura teaches the light emitting device of claim 1, wherein an edge of the second insulator (16 of Emura) extends in a direction away from an edge of the first semiconductor layer (12n of Emura) such that the edge of the second insulator (16 of Emura) is disposed on a side (in region of 12c of Emura) of the first semiconductor layer (12n of Emura). Re claim 16: Kamada teaches (e.g. figs. 1 and 9) a light emitting device (surface light source 100; e.g. paragraph 32) comprising: a support (base 10; e.g. paragraph 32); a plurality of light emitters (light emitting elements 20; e.g. paragraph 32) disposed on the support (10) and apart from one another; and first optics (lens 30; e.g. paragraph 32) disposed to surround the light emitters (20), each first optic (30) including a top surface with a convex curvature (convex surface of 30) and being in contact with the support (10). Kamada is silent as to explicitly teaching each light emitter includes: a first semiconductor layer having a first conductivity type; an active layer disposed over the first semiconductor layer; a second semiconductor layer disposed over the active layer and having a second conductivity type different from the first conductivity type; an ohmic layer disposed on the second semiconductor layer and in electrically contact with the second semiconductor layer; a first pad electrode electrically connected to the first semiconductor layer; a second pad electrode electrically connected to the second semiconductor layer; a first insulator covering the first pad electrode and the second pad electrode, the first insulator including a plurality of openings exposing upper surfaces of the first pad electrode and the second pad electrode, respectively; a second insulator disposed between the second semiconductor layer and the first insulator, an edge of the second insulator being located inward of and spaced farther from an edge of the first insulator than an edge of the light emitter; a first pad and a second pad that are electrically connected to the first pad electrode and the second pad electrode exposed through the plurality of openings of the first insulator, wherein the second insulator includes a first surface and a second surface opposite to the first surface, and wherein the second insulator includes a first portion and a second portion that have different thicknesses from each other and are disposed on a surface of the ohmic layer to be in contact with the ohmic layer, a thickness of the fist portion and a thickness of the second portion being distances between the first surface and the second surface in the first portion and the second portion in a vertical direction. Emura teaches (e.g. figs. 1A-C and labeled fig. 1B below) each light emitter includes: a first semiconductor layer (12n) having a first conductivity type (n-type layer 12n); an active layer (12a) disposed over the first semiconductor layer (12n); a second semiconductor layer (12p) disposed over the active layer (12a) and having a second conductivity type (p-type layer 12p) different from the first conductivity type; an ohmic layer (13) disposed on the second semiconductor layer (12p) and in electrically contact with the second semiconductor layer (12p); a first pad electrode (149) electrically connected to the first semiconductor layer (12n); a second pad electrode (141) electrically connected to the second semiconductor layer (12p); a first insulator (17) covering the first pad electrode (149) and the second pad electrode (141), the first insulator (17) including a plurality of openings (openings 149 and similar openings as shown in fig. 1A) exposing upper surfaces of the first pad electrode (149) and the second pad electrode (141), respectively; a second insulator (16; e.g. paragraph 36) disposed between the second semiconductor layer (12p) and the first insulator (17), an edge (edge labeled “2E” below) of the second insulator (16) being located inward of and spaced farther from an edge (edge labeled “1E” below) of the first insulator (17) than an edge (edge labeled “LEE” below) of the light emitter (1); and a first pad (18n) and a second pad (18p) that are electrically connected to the first pad electrode (149) and the second pad electrode (141) exposed through the plurality of openings of the first insulator (17), wherein the second insulator (16) includes a first surface (upper surface of 16 above 13; hereinafter “1S”) and a second surface (upper surface of 16 of the portion of 16 which is in contact with the side surface of 13; hereinafter “2S”) opposite to the first surface (1S), and wherein the second insulator (16) includes a first portion (portion of 16 proximate openings 16n; hereinafter “1P”) and a second portion (horizontal portions of 16; hereinafter “2P”) that have different thicknesses from each other and are disposed on a surface of the ohmic layer (13) to be in contact with the ohmic layer (13), a thickness of the fist portion (1P) and a thickness of the second portion (2P) being distances between the first surface (1S) and the second surface (2S) in the first portion (1P) and the second portion (2P) in a vertical direction. It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the light emitting element as taught by Emura in the device of Kamada since Kamada lacks any detail as to the structure of the light emitting element. The light emitting element of Emura provides a known structure which has improved light extraction efficiency and would improve the efficiency of the device of Kamada. Re claim 17: Kamada teaches the light emitting device of claim 16, further comprising: an additional optical element (reflection film is preferably formed on the base 10; e.g. paragraph 49) disposed between two light emitters (20) and having a shape extending along a surface of the support (10). Re claim 18: Kamada teaches the light emitting device of claim 16, wherein at least one of the first optics (30) has a height further away from the support (10) as compared to the additional optical element (reflection film is preferably formed on the base 10; e.g. paragraph 49). Re claim 19: Kamada teaches the light emitting device of claim 16, wherein a portion of the second insulator (16 of Emura) that contacts with the ohmic layer (13 of Emura) has a thickness different from another portion of the second insulator (16 of Emura). Re claim 20: Kamada in view of Emura teaches the light emitting device of claim 16, wherein an edge of the second insulator (16 of Emura) extends in a direction away from an edge of the first semiconductor layer (12n of Emura) such that the edge of the second insulator (16 of Emura) is disposed on a side (in region of 12c of Emura) of the first semiconductor layer (12n of Emura). Claim(s) 6 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kamada in view of Emura as applied to claims 1 and 11, respectively above, and further in view of Kim et al. (US PGPub 2013/0105845; hereinafter “Kim”). Re claims 6 and 13: Kamada in view of Emura teaches substantially the entire structure as recited in claims 1 and 11, except explicitly teaching the first insulator includes a distributed Bragg reflector including SiO2 and TiO2 that are repeatedly stacked on above another. Kim teaches (e.g. figs. 14 and 15) the first insulator (140-2; e.g. paragraph 90) includes a distributed Bragg reflector including SiO2 and TiO2 (TiO2 and SiO2 layers are stacked to make the DBR; e.g. paragraph 63) that are repeatedly stacked on above another. It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the Bragg reflector as taught by Kim in the device of Kamada in view of Emura in order to have the predicable result of further increasing light extraction by having an upper dielectric layer which also reflects light in addition to the reflection layers of Emura. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US PGPub 2016/0172560 fig. 5 and US PGPub 2016/0372630 fig. 3B shows what may be what Applicant may have intended to claim. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached on 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JESSE Y MIYOSHI/ Primary Examiner, Art Unit 2898
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Prosecution Timeline

Show 10 earlier events
May 15, 2025
Request for Continued Examination
May 16, 2025
Response after Non-Final Action
Sep 10, 2025
Non-Final Rejection mailed — §103
Dec 08, 2025
Response Filed
Feb 10, 2026
Final Rejection mailed — §103
Apr 09, 2026
Response after Non-Final Action
May 06, 2026
Request for Continued Examination
May 11, 2026
Response after Non-Final Action

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Prosecution Projections

6-7
Expected OA Rounds
57%
Grant Probability
76%
With Interview (+19.0%)
3y 7m (~0m remaining)
Median Time to Grant
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