DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Group I, Species 3, was elected.
Amendment filed September 11, 2025 is acknowledged. Claims 1, 5 and 9 have been amended. Non-elected Inventions and/or Species, Claims 3, 9-11 and 20-22 have been withdrawn from consideration. Claims 1, 3-5, 9-11, 13-15 and 18-22 are pending.
Action on merits of the Elected Invention I and Species 3, claims 1, 4-5, 13-15 and 18-19 follows.
Declaration under 37 CFR 1.132
The Declaration under 37 CFR 1.132 filed September 11, 2025 is insufficient to overcome the rejection of claims 1, 4-5, 13-15 and 18-19 based upon KOBAYASHI ‘054 and WILLMEROTH ‘927 as set forth in the last Office action because: in view of WILLMEROTH, the gate structure is a planar-type where the bottommost surface of the gate structure and the topmost surface of the epitaxial layer are coplanar.
There is no evidence in the specification, that the trench gate device 700 (FIG. 7D) is performed worse or better than the planar gate device 300A (FIG. 3A).
Note that, the example, in the Declaration, the device lacks “floating doped region”, which is the most important feature of the invention.
The “Example” and “Comparative Example” do not have “floating doped region”, while the devices of both KOAYASHI and WILLMEROTH clearly having “floating doped region.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 4-5, 13-15 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over KOBAYASHI (US. Pub. No. 2006/0244054) in view of WILLMEROTH et al. (US. Pub. No. 20090159927) both of record.
With respect to claim 1, KOBAYASHI teachers a power semiconductor device, as claimed including:
an epitaxial layer (2) having a first conductive type (n);
a first well region (3 left) having a second conductive type (p) and extending from a surface of the epitaxial layer (2) into the epitaxial layer;
a second well region (3 right) having the second conductive type (p), extending from the surface of the epitaxial layer (2) into the epitaxial layer, and separated from the first well region (3 left);
a floating doped region (11) having the second conductive type (p), located in the epitaxial layer (2) and between the first well region (3 left) and the second well region (3 right), and separated from the first well region and the second well region;
a first doped region (4 left) having the first conductive type (n) and extending from the surface of the epitaxial layer into the first well region (3 left);
a second doped region (4 right) having the first conductive type (n) and extending from the surface of the epitaxial layer into the second well region (3 right);
a third doped region (12, left) having the second conductive type (p), located in the epitaxial layer (2), and connected to the first well region (3 left);
a fourth doped region (12, right) having the second conductive type (p), located in the epitaxial layer (2), and connected to the second well region (3 right) so that the floating doped region (11) is located between the third doped region (12 left) and the fourth doped region (12 right); and
a gate structure (6) located on the epitaxial layer (2), adjacent to the first doped region (4 left) and the second doped region (4 right), and at least partially overlapped with the floating doped region (11),
wherein each of sidewalls of the third doped region (12 left) and the fourth doped region (12 right) are wavy. (See FIGs. 1, 5).
Thus, KOBAYASHI is shown to teach all the features of the claim with the exception of explicitly disclosing a bottommost surface of the gate structure and the topmost surface of the epitaxial layer are coplanar.
However, WILLMEROTH teaches a power semiconductor device including:
a gate structure (G, 5/6) located on the epitaxial layer (9), adjacent to first doped region (n+ left) and second doped region (n+ right), and at least partially overlapped with floating doped region (13),
wherein a bottommost surface of the gate structure and the topmost surface of the epitaxial layer (9) are coplanar. (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the power semiconductor device of KOBAYASHI having the bottommost surface of the gate structure and the topmost surface of the epitaxial layer being coplanar as taught by WILLMEROTH for the same intended purpose of obtaining high source-drain breakdown voltage and low on-resistance.
With respect to claim 4, the floating doped region (11) of KOBAYASHI has a first ion implantation region (11) contacting the gate structure (7) and a second ion implantation region (11) respectively separated from the gate structure (7) and the first ion implantation region (11). (See [0045]).
With respect to claim 5, in view of WILLMEROTH, the gate structure further comprises:
a gate dielectric layer (6) located on the surface of the epitaxial layer (9) and adjacent to the first doped region (n+ left) and the second doped region (n+ right); and
a gate electrode (5) located on the gate dielectric layer (6) and electrically isolated from the epitaxial layer (9) through the gate dielectric layer (6),
wherein a bottommost surface of the gate dielectric layer (6) and the topmost surface of the epitaxial layer (9) are coplanar.
With respect to claim 13, the floating doped region (11) of KOBAYASHI comprises a plurality of implantation regions.
With respect to claim 14, the plurality of ion implantation regions (11) of KOBAYASHI are separated from each other.
With respect to claim 15, the plurality of ion implantation regions of KOBAYASHI comprise:
a first ion implantation region (11) disposed below and being in contact with the gate structure (7);
a second ion implantation region (11) below and separated from the first ion implantation region by a non-zero distance;
a third ion implantation region (11) below and separated from the second ion implantation region (11) by a non-zero distance; and
a fourth ion implantation region (11) below and separated from the third ion implantation region (11) by a non-zero distance. (See [0045]).
With respect to claim 18, the first ion implantation region and an upper portion of the second ion implantation region (11) of KOBAYASHI are laterally between the first well region (3 left) and the second well region (3 right).
With respect to claim 19, a lower portion of the second ion implantation region (11), the third ion implantation region (11) and the fourth ion implantation region (11) of KOBAYASHI are laterally between the third doped region (12 left) and the fourth doped region (12 right).
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/Primary Examiner, Art Unit 2893