DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/6/2026 has been entered.
Response to Arguments
Claim Rejections – 35 USC 101
Applicant's arguments filed 2/6/2026 have been fully considered but they are not persuasive.
Applicant asserts “a processor having a precision limited by hardware of the processor” and precision results are generated “having greater precision than the precision limited by the hardware of the processor” integrates the claim to a practical application because it allows processors to generate higher precision results via programming. Examiner respectfully disagrees. The claim recites the equivalent of applying the programming of handling data with precision greater than the precision the processor hardware is capable of, instead of a particular arrangement of processor hardware. Thus, the improvement of allowing processors to generate higher precision results is a consequence of applying the judicial exception, however the judicial exception alone cannot provide the improvement. See MPEP 2106.05(a). Therefore, the claim is not integrated in a practical application.
Applicant asserts that the claim is an improvement in the functioning of a computer or other technology or technical field because the processor is able to generate results “having greater precision than the precision limited by the hardware of the processor.” Examiner respectfully disagrees. As discussed above, the claim recites applying the judicial exception on to a precision limited processor, and thus allows said processor to generate higher precision results. However, the judicial exception alone cannot provide the improvement.
Applicant asserts the invention implements a judicial exception with, or in conjunction with, a particular machine or manufacture integral to the claim because the processor with limited precision is integral to the claim. Examiner respectfully disagrees. The precision limited processor is recited at a high level of generality, and is merely recited to apply the judicial exception. It is not that the precision limited processor is integral to the claim, but the judicial exception, when applied, improves any precision limited processors to generate higher precision results.
Applicant asserts newly added claims 31-35 further show the claim as a whole integrating the judicial exception into a practical application. Examiner respectfully disagrees. As to claims 31-32, 34-35, the claims recite “wherein the greater precision matrix multiplications are to be executed during training…” (emphasis added). The phrase “are to be executed” is interpreted as intended use, as the claim language does not explicitly require the matrix multiplications to be executed during training or application of a neural network. Intended use cannot integrate a judicial exception. See MPEP 2106.04(d)(2). As to claim 33, the claim recites “wherein the greater precision matrix multiplications are executed during training…” (emphasis added). Claim 33 explicitly recites the matrix multiplications are executed during training or application of a neural network, and thus not intended use. However, “during training or application of a neural network” are additional elements wherein the claim recites the equivalent of the judicial exception and “apply it” to “training or application of a neural network”. Therefore, the newly added claims do not integrate the judicial exception into a practical application.
Prior Art Rejections
New grounds of rejections are made in view of the change of scope of current claim language against the claim language filed 7/23/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 7, 13, 19, 25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 7, 13, 19, 25 recite “generate… precision results having greater precision than the precision limited by the hardware of the processor” (emphasis added). “Precision limited by the hardware of the processor” is interpreted to mean processor hardware that is restricted to data that is not larger than a certain precision, which may include precision limited hardware for functions such as data storage, data transmission, and system input/output ports. However, applicant’s specification, such as [0045], [0049], only discloses precision limited by the arithmetic hardware of the processor. Applicant’s specification does not seem to disclose processors that are limited by the precision of hardware other than arithmetic circuitry.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-35 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Claims 25-30, 35 will be addressed first.
Regarding claim 25, at Step 1, the claim is directed to a system, which is a statutory category of invention (machine).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
A system, comprising: one or more processors to execute one or more matrix operations, with a processor having a precision limited by hardware of the processor, on one or more scaled precision operands (mathematical relationship) wherein the one or more precision operands are generated based, at least in part, on applying one or more scaling factors to one or more difference values (mathematical process and/or mental process, observation and evaluation assisted with pen and paper);
generate one or more unscaled precision results having a greater precision than the precision limited (mathematical relationship) by the hardware of the processor, wherein one or more scaled precision operands having a greater precision than the precision than the precision limited (mathematical relationship) by the hardware of the processor are to be generated by applying one or more reverse scaling factors to one or more results of the one or more matrix operations(mathematical process and/or mental process, observation and evaluation assisted with pen and paper);
and memory for storing the one or more unscaled precision results.
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitations “system, comprising: one or more processors” and “processor having a precision limited by hardware of the processor” are recited at a high level of generality and are merely the equivalent of reciting “apply it” with the judicial exception. The limitation “memory for storing” is an insignificant extra-solution activity of storing data. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception As set forth in step 2A prong 2 analysis, the function of “memory for storing” is recognized by the courts as well-understood routine and conventional. See MPEP 2106.05(d)(II). Furthermore, the “system, comprising: one or more processors” and “processor having a precision limited by hardware of the processor” are the equivalent of adding the words “apply it” to the judicial exception and are mere instructions to implement the abstract idea on a computer. Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The claim is not eligible.
Regarding claim 26, it is directed to the mathematical concept and/or mental process of “performing one or more decomposition operations”. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Regarding claim 27, it is directed to the mathematical concept and/or mental process of performing decompositions of values by rounding, subtracting, and applying a scaling factor. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Regarding claim 28, it is directed to the mathematical concept and/or mental process of performing matrix operations values of a different format. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Regarding claim 29, it is directed to the mathematical concept and/or mental process of applying a “the one or more reverse scaling factors to one or more results” of the matrix operations. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Regarding claim 30, it is directed to the mathematical concept and/or mental process of applying one of a plurality of scaling factors to one or more terms used for the matrix operations. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Regarding claim 35, it recites of intended use of the matrix multiplication and is thus the limitation is not required.
Nevertheless, under Step 2A Prong 2, the claim recites additional element “during training or during application of a neural network”. The additional element does not integrate the abstract ideas into a practical application because the application “during training or during application of a neural network” is recited at a high level of generality and does not impose any meaningful limits on practicing the abstract idea. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The claim is not eligible.
Regarding claims 1-6, 31 the claims are directed to a processor that implements the same or similar features as the system of claims 25-30, 35, respectively, and are therefore rejected for at least the same reasons therein.
Regarding claims 7-12, 32 the claims are directed to a system that implements the same or similar features as the system of claims 25-30, 35, respectively, and are therefore rejected for at least the same reasons therein.
Regarding claims 13-18, 33 the claims are directed to a method that implements the same or similar features as the system of claims 25-30, 35, respectively, and are therefore rejected for at least the same reasons therein.
Regarding claims 19-24, 34 the claims are directed to a non-transitory machine-readable medium that implements the same or similar features as the system of claims 26-30, 35, respectively, and are therefore rejected for at least the same reasons therein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
System claims 25-30, 35 will be addressed first.
Claims 1-35 are rejected under 35 U.S.C. 103 as being unpatentable over Kayiran et al. (US 20230098421 A1, hereinafter “Kayiran”) in view of Garegrat et al. (US 20190324723 A1, hereinafter “Garegrat”) in further view of Lin et al. (US 20220334798 A1, hereinafter “Lin”). All references provided in list of references cited by Examiner mailed 4/23/2025. The Wikipedia page for floating-point arithmetic, hereinafter “Wikipedia”, is used to support common knowledge in the art.
As per claim 25, Kayiran teaches a system, comprising: memory for storing the one or more unscaled precision results (Kayiran: Fig. 1; [0052]).
However, while Kayiran discloses arithmetic on decomposed floating-point values, Kayiran does not explicitly disclose the arithmetic being matrix mathematical operations. Thus, Kayiran does not teach one or more processors to execute one or more matrix operations, with a processor having precision limited by hardware of the processor, on one or more scaled precision operands are generated based, at least in part, on applying one or more scaling factors to one or more difference values; generate one or more unscaled precision results having a greater precision than the precision limited by the hardware of the processor, wherein one or more scaled precision operands having greater precision than the precision limited by the hardware of the processor are to be generated by applying one or more reverse scaling factors to one or more results of the one or more matrix operations.
Garegrat teaches one or more processors to execute one or more matrix operations, with a processor having precision limited by hardware of the processor (Garegrat: Fig. 3B; [0043]), on one or more scaled precision operands are generated based, at least in part, on applying one or more scaling factors to one or more difference values (Garegrat: Fig. 3A, of note element 312; [0040] – [0041], first data format corresponding to scaled precision operand, second data format corresponding to unscaled precision operand; [0021]; wherein “(bfloat)a” operation corresponds to a rounding operation; “am” being based on the difference of “a – ah” corresponds to the difference value, and subtracting the exponent value of floating-point number, additionally shown in Kayiran Fig. 3, is equivalent to left shifting the number, as evidentiary from Wikipedia, and thus corresponds to scaling the number).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the ALU of Kayiran with the teachings of Garegrat. One would have been motivated to combine these references because both references disclose arithmetic using decomposed floating-point values, and combining prior art elements according to known methods to yield predictable results (multiplication of matrices of values).
However, while Kayiran/Garegrat discloses accumulating partial products (Kayiran: [0040]-[0041]. Garegrat: Fig. 3B; [0043]), Kayiran does not explicitly disclose values used to align the partial products in a reversed manner relative to decomposing. Thus, Kayiran/Garegrat does not teach generate one or more unscaled precision results having a greater precision than the precision limited by the hardware of the processor, wherein one or more scaled precision operands having greater precision than the precision limited by the hardware of the processor are to be generated by applying one or more reverse scaling factors to one or more results of the one or more matrix operations.
Lin teaches generate one or more unscaled precision results having a greater precision than the precision limited by the hardware of the processor, wherein one or more scaled precision operands having greater precision than the precision limited by the hardware of the processor are to be generated by applying one or more reverse scaling factors to one or more results of the one or more matrix operations (Lin: Fig. 9, exponent adjustment logic, exponent bias values, and accumulator; [0218]; [0025]-[0026], wherein adjusting the computation result is based on the exponent bias value; furthermore, as shown in Wikipedia, floating point addition, or accumulation, aligns the exponent values to the larger value, which is equivalent to right shifting the lower floating-point number, and thus corresponds to a reverse scaling of the smaller number).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the ALU of Kayiran with the exponent adjustment logic of Lin. One would have been motivated to combine these references because both references disclose arithmetic using decomposed floating-point values, and combining prior art elements according to known methods to yield predictable results (how to combine computation results in the lower precision).
As per claim 26, Kayiran/Garagrat/Lin further teaches the system of claim 25, wherein the one or more processors are further to determine the one or more scaled precision operands by performing one or more decomposition operations on one or more input values having the greater precision (Garagrat: Fig. 1, [0021]).
As per claim 27, Kayiran/Garegrat/Lin further teaches the system of claim 26, wherein the one or more processors are further to perform multiple decompositions for individual input values, wherein respective decompositions include rounding a prior value to a decomposed value, subtracting the decomposed value from the prior value to obtain a difference value, then applying a scaling factor to the difference value (Garegrat: [0021], wherein “(bfloat)a” operation corresponds to a rounding operation; “am” being based on the difference of “a – ah” corresponds to the difference value; and subtracting the exponent value of floating-point number is equivalent to left shifting the number, as evidentiary from Wikipedia, and thus corresponds to scaling the number).
As per claim 28, Kayiran/Garegrat/Lin further teaches the system of claim 27, wherein the one or more processors are further to perform the one or more matrix operations using the decomposed values from each of the multiple decompositions (Garegrat: Fig. 3B; [0043]; Fig. 3A; [0040] – [0041]).
As per claim 29, Kayiran/Garegrat/Lin further teaches the system of claim 27, wherein the one or more processors are further to apply a reverse scaling factor to one or more results of the one or more matrix operations in order to generate the one or more unscaled precision results having the greater precision (Lin: Fig. 9, exponent adjustment logic, exponent bias values, and accumulator; [0218]; [0025]-[0026], wherein adjusting the computation result is based on the exponent bias value; furthermore, as shown in Wikipedia, floating point addition, or accumulation, aligns the exponent values to the larger value, which is equivalent to right shifting the lower floating-point number, and thus corresponds to a reverse scaling of the smaller number).
As per claim 30, Kayiran/Garegrat/Lin further teaches the system of claim 25, wherein the scaling factor is applied to one or more terms of a mathematical equation used for the one or more matrix mathematical operations, and wherein the scaling factor can be one of a plurality of scaling factors used for the one or more matrix operations (Kayiran: Fig. 3; [0028]. Garegrat: [0018] – [0019] the scaling of am is different from al as they are different exponents relative to the original higher precision format).
As per claim 35, Kayiran/Garegrat/Lin further teaches The system of claim 25, wherein the greater precision matrix multiplications are to be executed during training or during application of a neural network so as to exceed the level of precision of the hardware used to perform the matrix multiplications (Kayiran: [0001]. Garegrat: [0029]).
As per claims 1-6, 31, the claims are directed to a processor that implements the same or similar features as the system of claims 25-30, 35, respectively, and are therefore rejected for at least the same reasons therein.
As per claims 7-12, 32, the claims are directed to a system that implements the same or similar features as the system of claims 25-30, 35, respectively, and are therefore rejected for at least the same reasons therein.
As per claims 13-18, 33, the claims are directed to a method that implements the same or similar features as the system of claims 25-30, 35, respectively, and are therefore rejected for at least the same reasons therein.
As per claims 19-24, 34, if the claims were amended to satisfy Step 1, the claims implement the same or similar features as the system of claims 25-30, 35, respectively, and would therefore be rejected for at least the same reasons therein.
Conclusion
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182