DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-2, 4, 7, 22-23, 25-28, and 30-31 are pending in this office action and presented for examination. Claims 1-2, 4, 7, 22-23, 25-28, and 30-31 are newly amended by the response received March 16, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-2, 4, 7, 22-23, 25-28, and 30-31 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitation “determining activity data including samples associated with the stall state” in lines 5-6. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [00220]) does not appear to provide support for activity data including samples. For example, the original disclosure (e.g., paragraphs [00218], [00220], [00221]) does not appear to provide support for activity data including both samples associated with the stall state as well as another element that is distinct from the samples associated with the stall state, which is a scenario encompassed by the claim language in view of the open-ended “including” language.
Claim 1 recites the limitation “determining activity data including samples associated with the stall state, wherein the samples are resolved down to one or more stall reasons selected from one or more of instruction dependencies, pipeline stalls, or send stalls, wherein the activity data includes reason counts for counting occurrences of stalling activities” in lines 5-9. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [00218], [00220], [00221]) does not appear to provide support for determining reason counts for counting occurrences of stalling activities including samples associated with the stall state, wherein the samples are resolved down to one or more stall reasons selected from one or more of instruction dependencies, pipeline stalls, or send stalls.
Claim 1 recites the limitation “the processing circuitry to: sample a stall state associated with at least one processing resource of the processing circuitry, wherein sampling includes determining activity data including samples associated with the stall state, wherein the samples are resolved down to one or more stall reasons selected from one or more of instruction dependencies, pipeline stalls, or send stalls, wherein the activity data includes reason counts for counting occurrences of stalling activities” in lines 3-9. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [00215]-[00216]) does not appear to provide support for sampling a particular stall state including determining activity data including multiple samples associated with the stall state, wherein the multiple samples are resolved down to multiple stall reasons, wherein the activity data includes multiple reason counts for counting multiple occurrences of multiple stalling activities.
Claims 2, 4, and 7 are rejected for failing to alleviate the rejections of claim 1 above.
Claim 2 recites the limitation “the processing circuitry is coupled to or hosts control logic circuitry having hardware control logic circuitry, and wherein the processing circuitry is further to: receive an instruction pointer address and the activity data including the reason counts for counting occurrences of stalling activities” in lines 2-6. Claim 1, upon which claim 2 is dependent, recites the limitation “activity data including samples associated with the stall state, wherein the samples are resolved down to one or more stall reasons selected from one or more of instruction dependencies, pipeline stalls, or send stalls” in lines 6-8. However, the original disclosure (e.g., paragraphs [00218], [00221], [00226]) does not appear to provide support for the processing circuitry (in each of an embodiment where the processing circuitry is coupled to control logic circuitry, and an embodiment where the processing circuitry hosts control logic circuitry) receiving an instruction pointer address and samples associated with the stall state, wherein the samples are resolved down to one or more stall reasons selected from one or more of instruction dependencies, pipeline stalls, or send stalls. It is also generally unclear as to what entity in the original disclosure is intended to provide support for the recited “processing circuitry”, in context.
Claim 4 recites the limitation “wherein the processing circuitry is further to store the stall state when threads are allocated on a processing resource with no instruction being executed for a chosen clock cycle that is sampled, wherein the processing circuitry is further to discard the stall state for the chosen clock cycle if the processing resource is idle or executing an instruction” in lines 1-5. However, the original disclosure (e.g., paragraph [00215]) does not appear to provide support for this limitation.
Claim 7 recites the limitation “The apparatus of claim 1 … wherein the processing circuitry is coupled to a memory, the processing circuitry comprising one or more of graphics processing circuitry or application processing circuitry” in lines 1-9. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 12) does not appear to provide support for an apparatus which “compris[es]” the processing circuitry which “compris[es]” “graphics processing circuitry”. It is also generally unclear as to what entity in the original disclosure is intended to provide support for the recited “processing circuitry”, in context.
Claim 22 recites the limitation “determining activity data including samples associated with the stall state” in lines 4-5. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [00220]) does not appear to provide support for activity data including samples. For example, the original disclosure (e.g., paragraphs [00218], [00220], [00221]) does not appear to provide support for activity data including both samples associated with the stall state as well as another element that is distinct from the samples associated with the stall state, which is a scenario encompassed by the claim language in view of the open-ended “including” language.
Claim 22 recites the limitation “determining activity data including samples associated with the stall state, wherein the samples are resolved down to one or more stall reasons selected from one or more of instruction dependencies, pipeline stalls, or send stalls, wherein the activity data includes reason counts for counting occurrences of stalling activities” in lines 4-8. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [00218], [00220], [00221]) does not appear to provide support for determining reason counts for counting occurrences of stalling activities including samples associated with the stall state, wherein the samples are resolved down to one or more stall reasons selected from one or more of instruction dependencies, pipeline stalls, or send stalls.
Claim 22 recites the limitation “sampling, by processing circuitry of a computing device, a stall state associated with at least one processing resource of processing resources of the processing circuitry, the processing resources to process instructions, wherein sampling includes determining activity data including samples associated with the stall state, wherein the samples are resolved down to one or more stall reasons selected from one or more of instruction dependencies, pipeline stalls, or send stalls, wherein the activity data includes reason counts for counting occurrences of stalling activities” in lines 2-8. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [00215]-[00216]) does not appear to provide support for sampling a particular stall state including determining activity data including multiple samples associated with the stall state, wherein the multiple samples are resolved down to multiple stall reasons, wherein the activity data includes multiple reason counts for counting multiple occurrences of multiple stalling activities.
Claims 23 and 25-26 are rejected for failing to alleviate the rejections of claim 22 above.
Claim 23 recites the limitation “the processing circuitry is coupled to or hosts control logic circuitry comprising hardware control logic circuitry, wherein the processing circuitry to receive an instruction pointer address and the activity data including the reason counts for counting occurrences of stalling activities” in lines 2-5. Claim 22, upon which claim 23 is dependent, recites the limitation “activity data including samples associated with the stall state, wherein the samples are resolved down to one or more stall reasons selected from one or more of instruction dependencies, pipeline stalls, or send stalls” in lines 5-7. However, the original disclosure (e.g., paragraphs [00218], [00221], [00226]) does not appear to provide support for the processing circuitry (in each of an embodiment where the processing circuitry is coupled to control logic circuitry, and an embodiment where the processing circuitry hosts control logic circuitry) receiving an instruction pointer address and samples associated with the stall state, wherein the samples are resolved down to one or more stall reasons selected from one or more of instruction dependencies, pipeline stalls, or send stalls. It is also generally unclear as to what entity in the original disclosure is intended to provide support for the recited “processing circuitry”, in context.
Claim 25 recites the limitation “storing the stall state when threads are allocated on a processing resource with no instruction being executed for a chosen clock cycle that is sampled, and discarding the stall state for the chosen clock cycle if the processing resource is idle or executing an instruction” in lines 1-5. However, the original disclosure (e.g., paragraph [00215]) does not appear to provide support for this limitation.
Claim 26 recites the limitation “the processing circuitry is coupled to a memory, the processing circuitry comprising graphics processing circuitry” in lines 6-8. In addition, claim 22, upon which claim 26 is dependent, recites “processing circuitry of a computing device” in line 2. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 12) does not appear to provide support for an apparatus which “compris[es]” the processing circuitry which “compris[es]” “graphics processing circuitry”. It is also generally unclear as to what entity in the original disclosure is intended to provide support for the recited “processing circuitry”, in context.
Claim 27 recites the limitation “determining activity data including samples associated with the state” in lines 6-7. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [00220]) does not appear to provide support for activity data including samples. For example, the original disclosure (e.g., paragraphs [00218], [00220], [00221]) does not appear to provide support for activity data including both samples associated with the stall state as well as another element that is distinct from the samples associated with the stall state, which is a scenario encompassed by the claim language in view of the open-ended “including” language.
Claim 27 recites the limitation “determining activity data including samples associated with the stall state, wherein the samples are resolved down to one or more stall reasons selected from one or more of instruction dependencies, pipeline stalls, or send stalls, wherein the activity data includes reason counts for counting occurrences of stalling activities” in lines 6-10. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [00218], [00220], [00221]) does not appear to provide support for determining reason counts for counting occurrences of stalling activities including samples associated with the stall state, wherein the samples are resolved down to one or more stall reasons selected from one or more of instruction dependencies, pipeline stalls, or send stalls.
Claim 27 recites the limitation “sampling, by processing circuitry of the computing device, a stall state associated with at least one processing resource of processing resources of the processing circuitry, the processing resources to process instructions, wherein sampling includes determining activity data including samples associated with the stall state, wherein the samples are resolved down to one or more stall reasons selected from one or more of instruction dependencies, pipeline stalls, or send stalls, wherein the activity data includes reason counts for counting occurrences of stalling activities” in lines 4-10. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [00215]-[00216]) does not appear to provide support for sampling a particular stall state including determining activity data including multiple samples associated with the stall state, wherein the multiple samples are resolved down to multiple stall reasons, wherein the activity data includes multiple reason counts for counting multiple occurrences of multiple stalling activities.
Claim 27 recites the limitation “At least one non-transitory computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising: sampling … wherein sampling includes determining …” in lines 1-6. However, the original disclosure (e.g., paragraph [00173]) does not appear to provide support for this limitation.
Claims 28 and 30-31 are rejected for failing to alleviate the rejections of claim 27 above.
Claim 28 recites the limitation “the processing circuitry is coupled to or hosts control logic circuitry having hardware control logic circuitry, wherein the processing circuitry is further to receive an instruction pointer address and the activity data including the reason counts for counting occurrences of stalling activities” in lines 2-6. Claim 27, upon which claim 28 is dependent, recites the limitation “activity data including samples associated with the stall state, wherein the samples are resolved down to one or more stall reasons selected from one or more of instruction dependencies, pipeline stalls, or send stalls” in lines 7-9. However, the original disclosure (e.g., paragraphs [00218], [00221], [00226]) does not appear to provide support for the processing circuitry (in each of an embodiment where the processing circuitry is coupled to control logic circuitry, and an embodiment where the processing circuitry hosts control logic circuitry) receiving an instruction pointer address and samples associated with the stall state, wherein the samples are resolved down to one or more stall reasons selected from one or more of instruction dependencies, pipeline stalls, or send stalls. It is also generally unclear as to what entity in the original disclosure is intended to provide support for the recited “processing circuitry”, in context.
Claim 30 recites the limitation “wherein the operations further comprise storing the stall state when threads are allocated on a processing resource with no instruction being executed for a chosen clock cycle that is sampled, and discarding the stall state for the chosen clock cycle if the processing resource is idle or executing an instruction” in lines 2-5. However, the original disclosure (e.g., paragraph [00215]) does not appear to provide support for this limitation.
Claim 31 recites the limitation “wherein the processing circuitry is coupled to a memory, the processing circuitry comprising graphics processing circuitry” in lines 7-8. In addition, claim 27, upon which claim 31 is dependent, recites “processing circuitry of the computing device” in line 4. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 12) does not appear to provide support for an apparatus which “compris[es]” the processing circuitry which “compris[es]” “graphics processing circuitry”. It is also generally unclear as to what entity in the original disclosure is intended to provide support for the recited “processing circuitry”, in context.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 4, 7, 22-23, 25-28, and 30-31 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the processing circuitry to: sample a stall state associated with at least one processing resource of the processing circuitry” in lines 3-5. However, this limitation has insufficient antecedent basis in the claims. While “processing circuitry” was previously recited in claim 1, line 2, processing circuitry that in particular is to sample a stall state associated with at least one processing resource of the processing circuitry was not previously recited. In addition, the aforementioned limitation does not appear to have a grammatical predicate. For the purposes of this office action, Examiner is interpreting this limitation as if the “to: sample” language in claim 1, lines 3-4, is preceded by “is”.
Claim 1 recites the limitation “a stall state associated with at least one processing resource” in lines 4-5. However, it is indefinite as to whether a given stall state is associated with multiple processing resources (in the scenario in which “at least one” is “more than one”), or whether multiple processing resources are respectively associated with multiple stall states.
Claim 1 recites the limitation “at least one processing resource of the processing circuitry” in lines 4-5. However, it is indefinite as to whether the aforementioned “at least one processing resource” is being implicitly conveyed to be a member of “processing resources” as recited in claim 1, line 2. For the purposes of this office action, Examiner is taking such to be the case.
Claim 1 recites the limitation “wherein sampling includes determining activity data” in lines 5-6. However, the metes and bounds of this limitation are indefinite. For example, it is unclear as to whether the sampling of claim 1, line 5, is the same as the sampl[ing] of claim 1, line 4, and whether the sampling of claim 1, line 5, is also performed by the processing circuitry of claim 1, line 3.
Claim 1 recites the limitation “wherein the samples are resolved down to one or more stall reasons” in lines 6-7. However, at least in part due to the passive language, there is no indication about how the recited function is performed, as the recited function does not follow from the structure recited in the claim, i.e. the processing resources or the processing circuitry. As such, it is unclear whether the function requires some other structure or is simply a result of operating the machine in a certain manner. Specifying a particular structure that performs the recited function, provided such an amendment is supported by the original disclosure, would inform one of ordinary skill in the art of the metes and bounds of the functional limitation.
Claims 2, 4, and 7 are rejected for failing to alleviate the rejections of claim 1 above.
Claim 2 recites the limitation “a processing resource comprises a hardware processing resource” in lines 1-2. However, it is indefinite as to whether the recited processing resource is implicitly being recited to be part of the processing resources recited in claim 1, line 2, and indefinite as to whether the recited processing resource is part of the recited apparatus of claim 2, line 1.
Claim 2 recites the limitation “further includes a stall reason” in lines 6-7. However, it is indefinite as to whether this stall reason is part of, or distinct from, “reason counts for counting occurrences of stalling activity” as recited in claim 1, line 9.
Claim 2 recites the limitation “one or more states” in line 7. However, it is indefinite as to whether these states are the same as, or different from, that which is recited in claim 1, lines 4-5 (“a stall state associated with at least one processing resource of the processing circuitry”).
Claim 2 recites the limitation “the one or more of the processing resources associated with a cache unit” in lines 7-8. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 4 recites the limitation “wherein the processing circuitry is further to store the stall state when threads are allocated on a processing resource with no instruction being executed for a chosen clock cycle that is sampled, wherein the processing circuitry is further to discard the stall state for the chosen clock cycle if the processing resource is idle or executing an instruction” in lines 1-5. However, the metes and bounds of this limitation are indefinite. For example, it is unclear as to whether the stall state is both stored and then, subsequently, discarded, or whether the stall state is either stored or discarded. For example, it is unclear as to whether the recited processing resource is being implicitly recited to be a processing resource of the processing resources of claim 1, line 2.
Claim 4 recites the limitation “the stall state for the chosen clock cycle” in line 4. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 7 recites the limitation “the activity data further comprises a synch stall field for a stall or delay between threads to reach a common point, an instruction fetch field for an instruction fetch from memory that is stalled, a scoreboard field for a stall based on a data dependency, a send stall field for a send bus bandwidth limit for a processing resource, a pipe stall field for a stall within a pipeline, and an internal stall field for a stall caused from a memory bank collision” in lines 1-6. Claim 1, upon which claim 7 is dependent, recites the limitation “wherein the activity data includes reason counts for counting occurrences of stalling activities” in lines 8-9. However, the metes and bounds of the aforementioned limitation of claim 7 are indefinite in the context of the aforementioned limitation of claim 1. For example, it is indefinite as to whether the synch stall field, the instruction fetch field, the scoreboard field, the send stall field, the pipe stall field, and the internal stall field of claim 7 are a part of, or distinct from, the “reason counts for counting occurrences of stalling activities” as recited in claim 1, line 9. On one hand, claim 7 uses “further” language; on the other hand, the disclosure appears to indicate that the aforementioned fields correspond to the reason counts for counting occurrences of stalling activities.
Claim 7 recites the limitation “a memory” in line 7. However, it is indefinite as to whether this is the same memory as, or different memory from, “memory” as recited in claim 7, line 3. If the same, antecedent basis language should be used for clarity.
Claim 22 recites the limitation “a stall state associated with at least one processing resource” in lines 2-3. However, it is indefinite as to whether a given stall state is associated with multiple processing resources (in the scenario in which “at least one” is “more than one”), or whether multiple processing resources are respectively associated with multiple stall states.
Claim 22 recites the limitation “sampling” in line 4. However, it is indefinite as to whether this sampling is the same as, or different from, the “sampling” recited in claim 22, line 2. If the same, antecedent basis language should be used for clarity.
Claims 23 and 25-26 are rejected for failing to alleviate the rejections of claim 22 above.
Claim 23 recites the limitation “a processing resource comprises a hardware processing resource” in lines 1-2. However, it is indefinite as to whether the recited processing resource is implicitly being recited to be part of the processing resources recited in claim 22, line 3, and indefinite as to whether the recited processing resource is part of the processing circuitry of claim 22, line 2, and/or the computing device of claim 22, line 2.
Claim 23 recites the limitation “further includes a stall reason” in line 6. However, it is indefinite as to whether this stall reason is part of, or distinct from, “reason counts for counting occurrences of stalling activity” as recited in claim 22, line 8.
Claim 23 recites the limitation “one or more states” in line 6. However, it is indefinite as to whether these states are the same as, or different from, that which is recited in claim 22, lines 2-3 (“a stall state associated with at least one processing resource of processing resources of the processing circuitry”).
Claim 23 recites the limitation “the one or more of the processing resources associated with a cache unit” in lines 6-7. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 25 recites the limitation “storing the stall state when threads are allocated on a processing resource with no instruction being executed for a chosen clock cycle that is sampled, and discarding the stall state for the chosen clock cycle if the processing resource is idle or executing an instruction” in lines 1-5. However, the metes and bounds of this limitation are indefinite. For example, it is unclear as to whether the stall state is both stored and then, subsequently, discarded, or whether the stall state is either stored or discarded. For example, it is unclear as to whether the recited processing resource is being implicitly recited to be a processing resource of the processing resources of claim 22, line 4.
Claim 25 recites the limitation “the stall state for the chosen clock cycle” in lines 3-4. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 26 recites the limitation “the activity data further comprises a synch stall field for a stall or delay between threads to reach a common point, an instruction fetch field for an instruction fetch from memory that is stalled, a scoreboard field for a stall based on a data dependency, a send stall field for a send bus bandwidth limit for a processing resource, a pipe stall field for a stall within a pipeline, and an internal stall field for a stall caused from a memory bank collision” in lines 1-6. Claim 22, upon which claim 26 is dependent, recites the limitation “wherein the activity data includes reason counts for counting occurrences of stalling activities” in lines 7-8. However, the metes and bounds of the aforementioned limitation of claim 26 are indefinite in the context of the aforementioned limitation of claim 22. For example, it is indefinite as to whether the synch stall field, the instruction fetch field, the scoreboard field, the send stall field, the pipe stall field, and the internal stall field of claim 26 are a part of, or distinct from, the “reason counts for counting occurrences of stalling activities” as recited in claim 22, line 8. On one hand, claim 26 uses “further” language; on the other hand, the disclosure appears to indicate that the aforementioned fields correspond to the reason counts for counting occurrences of stalling activities.
Claim 26 recites the limitation “a memory” in line 7. However, it is indefinite as to whether this is the same memory as, or different memory from, “memory” as recited in claim 26, line 3. If the same, antecedent basis language should be used for clarity.
Claim 27 recites the limitation “a stall state associated with at least one processing resource” in lines 4-5. However, it is indefinite as to whether a given stall state is associated with multiple processing resources (in the scenario in which “at least one” is “more than one”), or whether multiple processing resources are respectively associated with multiple stall states.
Claim 27 recites the limitation “sampling” in line 6. However, it is indefinite as to whether this sampling is the same as, or different from, the “sampling” recited in claim 27, line 4. If the same, antecedent basis language should be used for clarity.
Claims 28 and 30-31 are rejected for failing to alleviate the rejections of claim 27 above.
Claim 28 recites the limitation “The non-transitory computer-readable medium of claim 27” in line 1. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 28 recites the limitation “a processing resource comprises a hardware processing resource” in line 2. However, it is indefinite as to whether the recited processing resource is implicitly being recited to be part of the processing resources recited in claim 27, line 5, and indefinite as to whether the recited processing resource is part of the processing circuitry of claim 27, line 4, and/or the computing device of claim 27, line 4.
Claim 28 recites the limitation “further includes a stall reason” in line 6. However, it is indefinite as to whether this stall reason is part of, or distinct from, “reason counts for counting occurrences of stalling activity” as recited in claim 27, line 10.
Claim 28 recites the limitation “one or more states” in line 7. However, it is indefinite as to whether these states are the same as, or different from, that which is recited in claim 27, lines 4-5 (“a stall state associated with at least one processing resource of processing resources of the processing circuitry”).
Claim 28 recites the limitation “the one or more of the processing resources associated with a cache unit” in lines 7-8. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 30 recites the limitation “The non-transitory computer-readable medium of claim 27” in line 1. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 30 recites the limitation “storing the stall state when threads are allocated on a processing resource with no instruction being executed for a chosen clock cycle that is sampled, and discarding the stall state for the chosen clock cycle if the processing resource is idle or executing an instruction” in lines 2-5. However, the metes and bounds of this limitation are indefinite. For example, it is unclear as to whether the stall state is both stored and then, subsequently, discarded, or whether the stall state is either stored or discarded. For example, it is unclear as to whether the recited processing resource is being implicitly recited to be a processing resource of the processing resources of claim 27, line 5.
Claim 30 recites the limitation “the stall state for the chosen clock cycle” in line 4. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 31 recites the limitation “The non-transitory computer-readable medium of claim 27” in line 1. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 31 recites the limitation “the activity data further comprises a synch stall field for a stall or delay between threads to reach a common point, an instruction fetch field for an instruction fetch from memory that is stalled, a scoreboard field for a stall based on a data dependency, a send stall field for a send bus bandwidth limit for a processing resource, a pipe stall field for a stall within a pipeline, and an internal stall field for a stall caused from a memory bank collision” in lines 2-7. Claim 27, upon which claim 31 is dependent, recites the limitation “wherein the activity data includes reason counts for counting occurrences of stalling activities” in lines 9-10. However, the metes and bounds of the aforementioned limitation of claim 31 are indefinite in the context of the aforementioned limitation of claim 27. For example, it is indefinite as to whether the synch stall field, the instruction fetch field, the scoreboard field, the send stall field, the pipe stall field, and the internal stall field of claim 31 are a part of, or distinct from, the “reason counts for counting occurrences of stalling activities” as recited in claim 27, line 10. On one hand, claim 31 uses “further” language; on the other hand, the disclosure appears to indicate that the aforementioned fields correspond to the reason counts for counting occurrences of stalling activities.
Claim 31 recites the limitation “a memory” in line 7. However, it is indefinite as to whether this is the same memory, or different memory, than “memory” as recited in claim 31, line 4. If the same, antecedent basis language should be used for clarity.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 4, and 7 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Regarding claims 1, 4, and 7, these claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claim(s) can be interpreted as software per se and thus can be made without an actual hardware apparatus. While the claim(s) do recite circuitry, paragraph [00173] discloses: ‘One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor. For example, the machine- readable medium may include instructions which represent various logic within the processor. When read by a machine, the instructions may cause the machine to fabricate the logic to perform the techniques described herein. Such representations, known as "IP cores," are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model on fabrication machines that manufacture the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein’. As such, Examiner recommends inserting the limitation “hardware” in an appropriate part of the claim and all relevant places in further dependent claims (e.g., replacing the limitation “processing circuitry” with the limitation “hardware processing circuitry”).
Response to Arguments
Applicant on page 7 argues: “Claim 2 has been amended, without prejudice, and accordingly, Applicant respectfully requests the withdrawal of the rejection of claim 2.”
In view of the aforementioned amendment, the previously presented objection of claim 2 is withdrawn.
Applicant on page 7 argues: ‘With respect to claim 1, "determine activity data ... with the state" is found all over the Specification; in particular, in paragraphs 115, 220, 262.’
However, the aforementioned paragraphs do not appear to provide support for the specific aspects of the relevant limitation that are noted in the associated rejection. For example, the aforementioned paragraphs do not appear to provide support for activity data including samples. If Applicant maintains that the cited paragraphs provide support for the specific aspects of the relevant limitation that are noted in the associated rejection, Examiner recommends that Applicant further explain how particular portions of the aforementioned paragraphs provide support for particular language in the relevant limitation.
Applicant on page 8 argues: ‘With respect to claim 1, "control logic circuitry to sample a stall state" is stated in paragraphs [00206] and [00215].’
Examiner notes that the associated rejection was not directed to the particular limitation "control logic circuitry to sample a stall state" — sans further associated limitations — not being supported by the original disclosure. Examiner further submits that the aforementioned paragraphs do not appear to provide support for the specific aspects of the overall cited limitation that are noted in the associated rejection. If Applicant maintains that the cited paragraphs provide support for the specific aspects of the overall cited limitation that are noted in the associated rejection, Examiner recommends that Applicant further explain how particular portions of the aforementioned paragraphs provide support for particular language in the overall cited limitation.
Applicant on page 8 argues: “The Specification at paragraph [00206] discloses: "The present design includes hardware to periodically sample a stall state of each processing resource (e.g., processing unit, processing engine, execution resource, execution unit (EU) 508A-N, 509A-N, 600, 852A-B, stream processors, streaming multiprocessor (SM), graphics multiprocessors 1925, 1950, multi-core groups 1965A-1965N, compute unit, compute unit of graphics core next) in the GPU; moreover, each sample is resolved down to one of a small number of possible stall reasons (e.g., Instruction Dependency, Pipeline Stall, Send Stall, etc.)."
However, while paragraph [00206] does disclose hardware to periodically sample a stall state of each processing resource, Examiner notes that an associated written description rejection was not directed to the particular limitation "control logic circuitry to sample a stall state" — sans further associated limitations — not being supported by the original disclosure. Examiner notes that paragraph [00206] does not appear to provide support for sampling a [particular] stall state including determining activity data including [multiple] samples associated with the stall state, wherein the [multiple] samples are resolved down to [multiple] stall reasons, wherein the activity data includes [multiple] reason counts for counting [multiple] occurrences of multiple stalling activities. If Applicant maintains that the cited paragraph provides support for the specific aspects of the relevant limitation that are noted in the associated rejection, Examiner recommends that Applicant further explain how particular portions of the aforementioned paragraph provide support for particular language in the relevant limitation.
Applicant on page 8 argues: ‘Paragraph [00220] discloses: "The activity data may relate to stalls and reason counts for stalling activity, instruction types, pipeline utilization, thread utilization, and shader activity.”’
However, Examiner submits that this portion of paragraph [00220] does not provide support for, for example, the activity data “including samples”, or sampling “a stall state” including determining activity data including [multiple] samples associated with the stall state, wherein the [multiple] samples are resolved down to [multiple] stall reasons, wherein the activity data includes [multiple] reason counts for counting [] occurrences of [multiple] stalling activities. If Applicant maintains that the cited paragraph provides support for the specific aspects of the relevant limitation that are noted in the associated rejection, Examiner recommends that Applicant further explain how particular portions of the aforementioned paragraph provide support for particular language in the relevant limitation.
Applicant on page 8 argues: “Similarly, other terms and processes are disclosed in the Specification. Claim 22 and 27 contain similar limitations as those of claim 1 and accordingly, these notes also apply to claims 22 and 27.”
Examiner’s responses to arguments above with respect to claim 1 are likewise applicable to the arguments directed to claims 22 and 27.
Applicant on page 9 argues: “Although Applicant respectfully and strenuously disagrees with the Examiner's assertions regarding the pending claims with respect the rejections under 35 USC112, for the sake of clarity and promoting this matter to allowance, Applicant proposes amendments to the pending claims, without prejudice. Claims 1-2, 4, 7, 22-23, 25-28 and 30-31 have been amended, without prejudice. Accordingly, for at least the reasons set forth above, Applicant respectfully requests the withdrawal of the rejection of claims 1-2, 4, 7, 22-23, 25-28 and 30-31.”
Various previously presented rejections of the claims under 35 U.S.C. §112(a) and 35 U.S.C. §112(b) are withdrawn in view of the amendments to the claims. However, other previously presented rejections of the claims under 35 U.S.C. §112(a) and 35 U.S.C. §112(b) remain applicable, and in various cases the amendments to the claims introduce additional issues under 35 U.S.C. §112(a) and 35 U.S.C. §112(b) — see the Claim Rejections - 35 USC § 112 section above.
Applicant on page 9 argues: “Claims 1, 4, 7, 27-28 and 30-31 stand rejected under 35 USC §101 because the claimed invention is directed to non-statutory subject matter. Claims 1, 22, and 27 have been amended, without prejudice. Accordingly, for at least the reasons set forth above, Applicant respectfully requests the withdrawal of the rejection of claims 1, 22, and 27 and their dependent claims.”
In view of relevant amendments to claims 27-28 and 30-31, the associated rejections under 35 USC §101 are withdrawn. However, the rejections of claims 1, 4, and 7 under 35 USC §101 remain applicable, as the amendments to claims 1, 4, and 7 do not appear to relate to Examiner’s specific rationale for the aforementioned rejections, and no arguments appear to be directed to Examiner’s specific rationale for the aforementioned rejections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH E VICARY/ Primary Examiner, Art Unit 2183