DETAILED ACTION
Claims 8, 10-11, 14, 16-17, 19-20, and 28-46 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 20, 2025, has been entered.
Information Disclosure Statement
In the IDS submitted on November 17, 2025, applicant cited a lengthy 236-page document without citing relevant portions/pages. To consider this document, the examiner has keyword searched demultiplexer/de-multiplexer and considered portions including these words. If applicant is aware of a relevant portion(s) of this document that should be drawn to the examiner’s attention, applicant is requested to point to such portion(s).
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Drawings
Replacement FIGs.1, 3B, 4, 5, and 8, submitted on May 20, 2025, are objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(l), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. The drawings are pixelated because applicant did not use true black (RGB = 000), despite the drawings appearing black to the naked eye. This has been confirmed by the examiner after inspecting the color content of applicant’s submitted pdf file. Replacement drawings were filed in black on January 21, 2025, and are not pixelated. The dithering used to convert applicant's grayscale image to black and white will add white pixels to try to estimate applicant's "gray" color, and the final drawings may not print properly or may print with reduced quality. Therefore, applicant must be sure to use only black and white. Applicant may try the following process to correct the color content:
1. Open the drawings PDF file with Adobe Acrobat Pro DC (a similar Adobe product may work, but the examiner has only tested this in Adobe Acrobat Pro DC);
2. Click “File” and then click “Print”;
3. Select “Adobe PDF” as the printer. If not available, “Microsoft Print to PDF” may also work, though this has not been tested. If neither option is available, this process may not be applicable, and applicant should try to find an alternate way to print in only black and white.
4. Uncheck “Print in grayscale (black and white)”;
5. Uncheck “Save ink/toner”;
6. Click “Advanced”;
7. Under “Color Management”, for the “Color Profile” field, select “Black & White” near the bottom of the list. The examiner also had “Treat grays as K-only grays” checked, and “Preserve Black” checked.
8. Click “OK” and then click “Print”. The resulting PDF should comprise only black and white drawings. Please review the final drawings for potential unintended consequences of this process.
NOTE: The examiner notes that this particular process is customized to this particular set of drawings. It may not work on other sets of drawings in other applications. If applicant is unable to perform the above conversion, the examiner would be willing to perform the conversion and email the resulting pdf file to applicant for formal filing once all other objections are resolved, provided an Authorization for Internet Communications (PTO/SB/439) is on record (see MPEP 502.03).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 45 objected to because of the following informalities:
In line 3, replace “corresponding” with --first--.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitations are:
In claim 8, “one or more processing elements to perform an execution of a layer in a neural network by processing first input data and second input data”. From claim 10 and paragraph 117, a processing element is interpreted to encompass a multiplier-accumulator (MAC) circuit, and equivalents thereof.
In claims 34 and 42, “performing, by one or more processing elements, an execution of a layer of a neural network by processing first input data and second input data”. A processing element is similarly interpreted as set forth above.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 28, 40, and 46 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Referring to claims 28, 40, and 46, the examiner has been unable to find support for a number bits in the configuration register depending on a number of the data banks in the one or more register files. Applicant has pointed to paragraph [0198] of the specification for support. This paragraph states that “[i]t may depend on the total number of bits in the elastic RF register”. However, it is not clear what “it” is referring to, nor is it clear that the elastic RF register is the configuration register 502. The paragraph reads as if the number of bits in the elastic RF register depends on the number of banks K. While FIG.5 could be interpreted to include a one-to-one correspondence between parameters and banks, this was not explicitly disclosed, nor is it inherent or implied in the original disclosure. A single parameter could instead be going to all the banks in FIG.5, or perhaps there is one parameter for every two banks. Also, FIG.5 shows multiple registers. Thus, there may be just one parameter per register such that there is one register and one parameter per bank. As such, unless applicant can point the examiner to clear support, applicant’s claims contain new matter that must be canceled.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “infrequently” in claim 19 is a relative term which renders the claim indefinite. The term “infrequently” is not defined by the claim, the specification in paragraph [0038]) does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. That is, the examiner is not clear on where the line is drawn between infrequent and not infrequent, and ones of ordinary skill in the art may disagree on such a line. As such, the scope of “infrequently” is unclear.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8, 10-11, 14, 17, 19-20, and 28-46 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Pineda et al., EP 3388981 A1.
Referring to claim 8, Pineda has taught an apparatus (FIG.3), comprising:
one or more processing elements to perform an execution of a layer in a neural network by processing first input data and second input data (FIG.3, PE array, which comprises multiple processing elements (PEs), each including a multiplier-accumulator circuit (FIG.7)) to provide one or more neuron layers for a neural network (see FIG.7 and the description thereof along with paragraphs [0026]-[0030], for instance. The PEs act as neurons performing multiply-accumulate (MACC) operations for CNN layers, for instance);
one or more register files communicatively coupled to the one or more processing elements (see FIG.6, some combination of RF1, RF2, RF3, RF4, and registers 624 may make up one or more register files connected to the PEs 622), the one or more register files comprising data banks for storing the first input data and the second input data (from FIG.6, the data banks may be at least a portion of the registers 624, which can store various input data based on control applied to the various mux/selection circuits. For instance, bank 4 (numbered ‘4’ in FIG.6) can store any of four different input data items depending on control provided to the mux under bank 4. The claimed first and second input data are broad and could encompass any of a number of data items in FIG.6, or groups of data items. For instance, from FIG.5, 546, first data may include X00 and second data may include X06, but only X06 (of these two inputs) is stored by bank 4); and
a configuration register (FIG.3, “Config. Registers”) to store configuration parameters (paragraph [0041]), the configuration parameters having programmable values and corresponding to a different ones of the data banks (from paragraph [0041], the parameters comprise numerous programmable settings, which configure the operation of Figure 6, including control of the data banks),
wherein a first data bank is coupled to a demultiplexer that is coupled to a first processing element (from FIG.6, bank 4 is coupled to the demultiplexer to the immediate left of bank 4, which is in turn coupled to a first processing element (which could be PE3, via indirect coupling, or any of the elements to the left of bank 4 to which the demultiplexer is directly coupled. For instance, bank 33 or the two directly multiplexers coupled directed to the demultiplexer, alone or in some combination, could be the first processing element. Note the examiner has not claimed the first processing element in a way that would distinguish from a register or multiplexer), the demultiplexer receiving data from the first data bank (again, from FIG.6, the demultiplexer to the left of bank 4 receives data from bank 4), the first processing element receiving data from the demultiplexer (again, from FIG.6, when the first processing element is at least one of 33, the multiplexer to the left of 33, or the multiplexer to the left of 32, the first processing element receives data directly from the multiplexer. When the first processing element is PE3, this element also receives data from the demultiplexer indirectly via bank 3), wherein a programmable value of a first configuration parameter for the first data bank indicates whether the first data bank stores the first input data or the second input data during the execution of the layer in the neural network. (as stated above, a programmable value will cause data bank 4 to store the first data or the second data (which may be two of the data items entering the mux below data bank 4)).
Referring to claim 10, Pineda has taught the apparatus of claim 8, wherein a processing element comprising a multiplier-accumulator (MAC) (see FIG.7, which multiplies values at 758 and accumulates values at 764).
Referring to claim 11, Pineda has taught the apparatus of claim 8, wherein the first data bank is arranged between a multiplexer and the demultiplexer on a data path, wherein the multiplexer or the demultiplexer is to receive the first configuration parameter and to operate based on the first configuration parameter (from FIG.6, first data bank 4 is between the multiplexer immediately underneath bank 4 and a demultiplexer to the immediate left of bank 4. Again, a configuration parameter is used to control the selections by the multiplexer/demultiplexer so as to create a data path through which data flows).
Referring to claim 14, Pineda has taught the apparatus of claim 8, wherein the one or more register files comprise at least one data bank dedicated for storing one of the first input data and the second input data (from FIG.6, taking bank 4 as an example, when the multiplexer selects data to be stored in bank 4 for that cycle, bank 4 is dedicated to storing the selected data and no other data for that cycle. For instance, from FIG.5, bank 4, would be dedicated to storing X06 in the first cycle, which is the data that goes to the last PE).
Referring to claim 17, Pineda has taught the apparatus of claim 8, wherein the data banks are for further storing output data of the layer in the neural network (under a first interpretation of Pineda’s FIG.6, the input data stored in a data bank, e.g. data bank 4, is also output data of the layer, since the data is output to PE4, which executes the layer. Any of the other registers in 624 store output data for similar reasoning. Finally, at least parts of the RFs may be deemed banks (or parts thereof), and outputs generated by the PEs are routed to the RFs as seen in FIG.6).
Referring to claim 19, Pineda has taught the apparatus of claim 8, wherein the programmable value of the first configuration parameter is configured to account for stationary data, the stationary data comprising data that change infrequently within the layer, wherein the stationary data is the first input data or the second input data (the parameter accounts for data stationarity because the data is stationary within registers 624. For instance, 546 shows that the parameter controls some data, e.g. X02, X04, X06, etc., to be loaded into registers 624 and then be shifted within registers 624 to go to another PE (thus, it is stationary in registers 624 for some time). The data itself does not change, i.e., each originates from a source and maintains its value on its way to a destination PE).
Referring to claim 20, Pineda has taught the apparatus of claim 8, wherein the programmable value of the first configuration parameter is configured to account for one or more dimensions of a tensor of the layer in the neural network (all data is at least a rank-0 tensor and, thus, the parameter accounts for such values (e.g. by propagating a rank-0 tensor through various multiplexers, etc.)).
Referring to claim 28, Pineda has taught the apparatus of claim 8, wherein a number of bits in the configuration register depends on a number of the data banks in the one or more register files (from FIG.6, the banks in 624 require various controls to select various data for storage or shifting to the left, etc. Thus, a number of parameters in the configuration register that allow for all of the controls to be realized would be implemented).
Referring to claim 29, Pineda has taught the apparatus of claim 8, wherein the programmable value of the first configuration parameter is encoded by multiple bits (multiple bits are required to perform all of the individual bank/mux controls in FIG.6, 624. For instance, the mux below bank 4 has four inputs and thus requires two bits to select one of the four inputs).
Referring to claim 30, Pineda has taught the apparatus of claim 8, wherein the programmable value of the first configuration parameter is specific to the layer in the neural network, and the first configuration parameter has a different programmable value for a different layer in the neural network (see paragraph [0041]. The parameter that controls the data inputted into the PEs for convolution is specific to a feature extraction layer 216. Another parameter may indicate a number of neurons in the classification stage 218).
Referring to claim 31, Pineda has taught the apparatus of claim 11, wherein the first configuration parameter is provided to the multiplexer or the demultiplexer (see FIG.6, where a control parameter would be sent to multiplexers/demultiplexers to control the flow of data through the banks and to the PEs).
Referring to claim 32, Pineda has taught the apparatus of claim 11, wherein the multiplexer is on a write path of first data bank (see FIG.6 and note the multiplexer under bank 4, which controls which data is written to bank 4), and the demultiplexer is on a read path of the first data bank (see FIG.6 and note the demultiplexer to the left of bank 4, which sends data read from bank 4 to the left to another bank/register).
Referring to claim 33, Pineda has taught the apparatus of claim 17, wherein the programmable value of the first configuration parameter further indicates whether the first data bank stores the output data during the execution of the layer in the neural network (since the data inputted into a bank is also data outputted from the bank (i.e., input data = output data), and the parameter controls which input data is stored in a bank, the parameter also controls which output data is stored in the bank).
Claims 34-41 are rejected for similar reasoning as claims 8, 11, 31-32, 17, 33, 28, and 30 respectively.
Claim 42 is rejected for similar reasoning as claim 8. Note that Pineda also sets forth one or more non-transitory computer-readable media storing instructions executable to perform the claimed operations (see paragraphs [0084]-[0085]).
Claim 43 is rejected for similar reasoning set forth in the rejections of claims 11 and 32.
Claim 44 is rejected for similar reasoning as claim 31.
Claim 45 is rejected for similar reasoning set forth in the rejections of claims 17 and 33.
Claim 46 is rejected for similar reasoning as claim 28.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Pineda.
Referring to claim 16, Pineda has taught the apparatus of claim 8, but has not taught wherein a number of bytes of a data bank is between 1 and 128. However, changing the size of the input data stored in the banks is deemed a routine expedient that lacks patentability. See MPEP 2144.02, including section (IV)(A). Each particular size of data has advantages and disadvantages, with larger data requiring more storage while also allowing for representation of a wider range of numbers than smaller data, which requires less storage. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pineda such that a number of bytes of a data bank is between 1 and 128, e.g. that a given data bank in Pineda could store at least one byte of input data at a time.
Response to Arguments
Applicant argues that the prior art has not taught the claims as amended.
For the reasoning set forth in the rejection of claim 8 above, the examiner respectfully disagrees.
Conclusion
The following prior art previously or currently made of record and not relied upon is considered pertinent to applicant's disclosure:
Fowers, 2018/0341483, has taught neural network operations using multiple processing elements coupled to multiple register files that may store different data types (vectors, matrices, floating-point, fixed-point, etc.). Various data is routed to the register files through multiplexers and demultiplexers (e.g. see FIG.2). The examiner notes that this document is particularly relevant to applicant’s claims and applicant is asked to take this document into account when formulating a response (including amendments).
Kwon, 2022/0035629, has taught an array of MAC units performing deep learning operations, where a register within the MAC units could receive different inputs.
Phelps, 2018/0336164, has taught a multiplexer to load a first weight or a second weight from separate input lines into a register within a MAC unit (e.g. FIG.3).
Chinya, 2020/0410327 (as cited by applicant), has taught a schedule-aware tensor distribution module with dedicated input, output, and weight register banks and multiplexer/demultiplexer circuitry used to load the banks (FIGs.4-5). The examiner notes that this document is particularly relevant to applicant’s claims and applicant is asked to take this document into account when formulating a response (including amendments).
Liu, 2022/0383081, has taught a flexible-scheduling machine learning accelerator with dedicated input, output, and weight register banks. The accelerator is dynamically configured to execute each layer. This document is also deemed particularly relevant.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/David J. Huisman/Primary Examiner, Art Unit 2183
Prosecution Insights