DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 43 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 43 recites the limitation "each magnetoresistive device of the plurality of magnetoresistive devices comprises a magnetoresistive stack, a bottom electrode, and a top electrode" in lines 1-3 is unclear. Are a magnetoresistive stack, a bottom electrode, and a top electrode the same with or different from a magnetoresistive stack, a bottom electrode, and a top electrode as previously claimed in claim 36.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-22, 24-25, 27, 29, 31-32 and 36-43 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2019/0013353 as disclose in previous office action).
As for claim 21, Lee et al. disclose in Fig. 1 and the related text an integrated circuit device comprising:
a plurality of vertically stacked metal layers (fig. 1), including a first metal layer 152/110 and a second metal layer 154/156/116/118;
a plurality of via layers 108/150/140/160, including a first via layer 108/150 and second via layer 140/160, the first via layer 108/150 between the first metal layer and the second metal layer (fig. 1), and the second metal layer 154/156/116/118 between the first via layer and the second via layer (Fig. 1);
a logic portion comprising logic circuits 102 including the first metal layer 110/152, the second metal layer 154/156/116/118, and the first via layer 108/150, the logic portion filled with a first interlayer dielectric (ILD) layer (left 112/122/120) (Fig. 1);
a memory portion 104 including the first metal layer 110/152, the second metal layer 154/156/116/118, the first via layer 108/150, and the second via layer 140/160, the memory portion filled with a second ILD layer (right 112/122/120); and
a plurality of magnetoresistive devices 116/118, wherein each magnetoresistive device of the plurality of magnetoresistive devices provided in the second metal layer of the memory portion (fig. 1), wherein a first magnetoresistive device 116/118, of the plurality of magnetoresistive devices, comprises a top electrode 134, a magnetoresistive stack 128/130/132, and a bottom electrode 116, is provided in the memory portion, and has a height that is substantially the same as a height of a feature of the logic circuits within the second metal layer 154/156 (Fig. 1),
wherein (a portion of) the first ILD layer (left 120) and (a portion of) the second ILD layer (right 120) are made from the same material such that the material ([0041] and [0043]) extends from a top surface of the first metal layer 110/152 to a bottom surface of the first metal layer in both the logic portion and the memory portion and (thermally/electrically) contacts the first magnetoresistive device (fig. 1).
As for claim 22, Lee et al. disclose the device of claim 21, wherein each of the plurality of magnetoresistive devices 116/118 includes an encapsulant 126.
As for claim 24, Lee et al. disclose the device of claim 23, wherein a combined height of a via 140 within the memory portion of the second via layer and a magnetoresistive device 116/118 of the plurality of magnetoresistive devices is substantially the same as a combined height of a feature of the logic circuits within the second metal layer 154/156 and a via 160 within the logic portion of the second via layer (FIG. 1A).
As for claim 25, Lee et al. disclose the device of claim 23, wherein a via 160 within the logic portion of the second via layer has substantially the same height as a via 140 within the memory portion of the second via layer (FIG. 1A).
As for claim 27, Lee et al. disclose device of claim 26, wherein each magnetoresistive device 116/118 of the plurality of magnetoresistive devices lands on a corresponding via 108 within the memory portion of the first via layer, and each magnetoresistive device 116/118 has a width greater than a width of the corresponding via 108 (FIG. 1A).
As for claim 29, Lee et al. disclose in Fig. 1 and the related text an integrated circuit device comprising:
a plurality of vertically stacked metal layers, including a first metal layer 154/156/116/118;
a plurality of via layers 108/150/140/160, including a first via layer 108/150 and a second via layer 140/160, wherein the first metal layer 154/156/116/118 is between the first via layer 108/150 and the second via layer 140/160;
a logic portion 102 comprising logic circuits including the first metal layer, the first via layer, and the second via layer (fig. 1);
a memory portion 104 including the first metal layer, the first via layer, and the second via layer (fig. 1);
a plurality of magnetoresistive devices 116/118, wherein each magnetoresistive device 116/118 of the plurality of magnetoresistive devices comprises a top electrode 134, a magnetoresistive stack 128/130/132, and a bottom electrode 116 is within the memory portion and between the first via layer and the second via layer (fig. 1); and
an interlayer dielectric (ILD) layer 112/122/120/136/142 provided in the memory portion, wherein a combined height of a magnetically free region 128, a magnetically fixed region 132, and an intermediate region 130 of at least one magnetoresistive device of the plurality of magnetoresistive devices, is less than or equal to a height of the first metal layer (fig. 1), and
wherein the ILD layer 112/122/120/136/142 extends across the first via layer (Fig. 1), from a top surface of the first metal layer to a bottom surface of the first metal layer in both the logic portion and the memory portion (Fig. 1), and across the second via layer, and contacts the at least one magnetoresistive device (fig. 1); and
wherein a feature of the logic circuits 102 within the first metal layer 154/156 has a height that is substantially the same as a height of the at least one magnetoresistive device 116/118 of the plurality of magnetoresistive devices (Fig. 1).
As for claim 31, Lee et al. disclose the device of claim 29, further comprising a second metal layer 138/158, wherein the logic circuits further include the second metal layer 158; and vias 160 within the logic portion of the second via layer, connect the first metal layer to the second metal layer (fig. 1).
As for claim 32, Lee et al. disclose the device of claim 31, wherein the memory portion further includes the second metal layer 116/118; and wherein a height of a via 140 within the memory portion of the second via layer is substantially the same as a height of a via 160 within the logic portion of the second via layer (fig. 1).
As for claim 36, Lee et al. disclose in Fig. 1 and the related text an integrated circuit device comprising:
a plurality of vertically stacked metal layers (fig. 1), including a first metal layer 154/156/116/118;
a plurality of via layers, including a first via layer 108/150 and a second via layer 140/160, wherein the first metal layer is between the first via layer and the second via layer (fig. 1);
a logic portion 102 comprising logic circuits including the first metal layer, the first via layer, and the second via layer (fig. 1), the logic portion filled with a first interlayer dielectric (ILD) layer (left 112/122/120/136/142);
a memory portion 104 including the first metal layer, the first via layer, and the second via layer (fig. 1), the memory portion filled with a second ILD layer (left 112/122/120/136/142); and
a plurality of magnetoresistive devices 116/118, wherein each magnetoresistive device of the plurality of magnetoresistive devices is provided in the first metal layer (fig. 1), wherein a first magnetoresistive device, of the plurality of magnetoresistive devices, wherein a first magnetoresistive device 116/118, of the plurality of magnetoresistive devices, comprises a top electrode 134, a magnetoresistive stack 128/130/132, and a bottom electrode 116, and is provided in the memory portion (fig. 1) and wherein a height of the first magnetoresistive device 116/118 has substantially the same height as the first metal layer 154/156; and
wherein a via 150 within the logic portion of the first via layer has substantially the same height as a via 108 within the memory portion of the first via layer (fig. 1), and
wherein the first ILD layer (left 112/122/120/136/142) and the second ILD layer (right 112/122/120/136/142) are made from the same material ([0041] and [0043]) such that the material extends from a top surface of the first metal layer to a bottom surface of the first metal layer in both the logic portion and the memory portion and (thermally/electrically) contacts the first magnetoresistive device (fig. 1).
As for claim 37, Lee et al. disclose the device of claim 36, wherein a via 160 within the logic portion of the second via layer has substantially the same height as a via 140 within the memory portion of the second via layer (fig. 1).
As for claim 38, Lee et al. disclose the device of claim 36, wherein at least one magnetoresistive device 116/118 of the plurality of magnetoresistive devices includes a synthetic antiferromagnetic structure, a synthetic ferromagnetic structure, or both [0039].
As for claim 39, Lee et al. disclose the device of claim 36, wherein a height of the first via layer 108/150 is at least about one-third of a height of the first metal layer (fig. 1).
As for claim 40, Lee et al. disclose the device of claim 36, wherein a height of the first metal layer 154/156/116/118 is greater than a combined height of the first via layer 108/150 and the second via layer 140/160 (fig. 1).
As for claim 41, Lee et al. disclose the device of claim 21, wherein each magnetoresistive device 116/118 of the plurality of magnetoresistive devices comprises a magnetoresistive stack 128/130/132, a bottom electrode 116, and a top electrode 134.
As for claim 42, Lee et al. disclose the device of claim 29, wherein each magnetoresistive device 116/118 of the plurality of magnetoresistive devices comprises a magnetoresistive stack 128/130/132, a bottom electrode 116, and a top electrode 134.
As for claim 43, Lee et al. disclose the device of claim 36, wherein each magnetoresistive device 116/118 of the plurality of magnetoresistive devices comprises a magnetoresistive stack 128/130/132, a bottom electrode 116, and a top electrode 134.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 33-35 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Manfrini et al. (US 2020/0176379, as recited in previous office action).
As for claims 33-35, Lee et al. disclose the device of claim 32, except: a third metal layer; and a third via layer between the first metal layer and the third metal layer; where the logic circuits further include the third metal layer and the third via layer; and the memory portion further includes the third metal layer and the third via layer, wherein a width of the at least one magnetoresistive device is less than a width of a via within the memory portion of the third via layer, and wherein a height of a via within a memory portion of the third via layer is substantially the same as a height of a via within the third via layer of the logic circuits.
Manfrini et al. teach in Fig. 5 and the related text a third metal layer 508a/508b; and a third via layer (upper via that form under 508a/508b) between a first metal layer 114b and the third metal layer 508a/508b; wherein a logic circuits 506 further include the third metal layer 508b and the third via layer (right upper via); and the memory portion 504 further includes the third metal layer 508a and the third via layer (left upper via), wherein a height of a via within a memory portion of the third via layer is substantially the same as a height of a via within the third via layer of the logic circuits (fig. 5).
Lee et al. and Manfrini et al. are analogous art because they both are directed memory device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chuang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chuang et al. to include the limitations, as taught by Manfrini et al. in order to improve interconnections.
Lee et al. in view of Manfrini et al. teach a width of (any portion of) the at least one magnetoresistive device is less than a width of a via within the memory portion of the third via layer.
Response to Arguments
Applicant's response filed on 02/11/2026 is acknowledged and is answered as follows.
Applicant’s arguments, see pgs. 9-11, with respect to claim 21, 29 and 36 that Lee et al. do not teach “a first magnetoresistive device, of the plurality of magnetoresistive devices, comprises a top electrode, a magnetoresistive stack, and a bottom electrode have been fully considered but they are not persuasive in view of the following reasons.
Lee et al. teach in [0039] a conductive layer 116 comprises metal, therefore conductive layer considers as a bottom electrode.
Fig. 1 of Lee et al. teaches a first magnetoresistive device 116/118 comprises a top electrode 134, a magnetoresistive stack 128/130/132, and a bottom electrode 116.
Therefore, Lee et al. still disclosed the claimed invention.
In view of the foregoing reasons, the Examiner believes that all Applicant’s arguments and remarks are addressed. The Examiner has determined that the previous Office Action is still proper based on the above responses. Therefore, the rejections are sustained and maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811