DETAILED ACTION
This non-final action is responsive to communications: RCE filed on 12/29/2025.
Applicant amended claim 1; added new claims 15-20; cancelled none. Claims 1-20 are pending. Claim 1 is independent.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/29/2025 has been entered.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Information Disclosure Statement IDS
IDS filed on 12/29/25 has been considered.
Notice of Pre-AIA or AIA Status
4. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
5. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
6. Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
10. Claims 1-14, 18, and 20 is/are rejected under 35 U.S.C. 103 as being obvious over Hoang (US 2020/0311523 A1), in view of Hsu et al. (US 2018/0165573 A1).
Regarding independent claim 1, Hoang teaches a neural network array (Abstract, Fig. 5: 326) comprising:
a plurality of vertical strings (“vertical nand strings”, see Fig. 16 nand strings) in a three-dimensional (3D) non-volatile memory array (para [0047], para [0049], para [0079], Fig. 5-Fig. 19),
each vertical string (Fig. 16: nand strings) having a drain select gate transistor (Fig. 16: DSL transistor) connected to a plurality of non- volatile memory cells that are connected in series along a vertical channel (Fig. 16, para [0047]: “vertical nand string” structure. See also e.g. Fig. 16), and
wherein each non-volatile memory cell (Fig. 16: cell pairs) functions as a synapse and represents a synaptic weight (Fig. 16: W) based on a threshold voltage (Vt) or resistance of the non-volatile memory cell (para [0066], see Fig. 9-Fig. 13);
a plurality of output nodes (Fig. 16: output terminals), each output node connected to receive output signals from a plurality of drain terminals of the drain select gates (see Fig. 16, para [0081]: see DSL transistor coupling);
a plurality of input nodes, each input node connected to provide input signals to a plurality of gate terminals of the drain select gates (Fig. 16: DSL gates and signals); and
a plurality of weight select signals connected to the plurality of memory cells in each string (Fig. 16 and para [0080]: logic input), respectively, and
wherein each weight select signal provides a selected voltage to a selected non-volatile memory cell to cause the selected non-volatile memory cell to conduct current according to a selected characteristic of the selected non-volatile memory cell (para [0071]-para [0073]; Fig. 12, Fig. 14: Icell).
Hoang is silent with respect to each weight signal connected to one non-volatile memory cell to cause non-volatile memory cell to conduct current.
Hsu teaches a neural network array (Fig. 11, para [0006]-para [0007]: “…three-dimensional (3D) neutral network array…”; Fig. 22F) comprising:
a plurality of strings (see e.g., Fig. 22F: 2214a, 2214b is a string and 2215a, 2215b is a string),
wherein each non-volatile memory cell functions as a synapse (para [0007]: “synapse”);
a plurality of weight select signals connected to the plurality of memory cells in each string, respectively (Fig. 22F: IN0…INm, INB0…INBm connected to gates of cells), and
wherein each weight select signal (Fig. 22F: IN0…INm, INB0…INBm) provides a selected voltage to a selected non-volatile memory cell to cause the selected non-volatile memory cell to conduct current (para [0129], para [0130]: current pass condition based on applied voltage) according to a selected characteristic of the selected non-volatile memory cell (in context of para [0129], para [0130]: current pass condition based on threshold).
Hoang and Hsu are in the same field of endeavor since Hsu teaches a neural network array (Fig. 11 nand device. See para [0006]-para [0007]: “…three-dimensional (3D) neutral network array…”; see Fig. 22F) comprising: a plurality of strings (see Fig. 11 and e.g., Fig. 22F: 2214a, 2214b is a string and 2215a, 2215b is a string), each string having a drain select gate transistor (Fig. 22F: 2218a and 2218b) connected to a plurality of non-volatile memory cells and wherein each non-volatile memory cell functions as a synapse (para [0007]: “synapse”). Thus, they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the array of Hoang by Hsu’s teachings to include a plurality of strings and nand cells such that each weight signal connected to one non-volatile memory cell to cause non-volatile memory cell to conduct current. Motivation would be to improve accuracy of computation by incorporating array structure, have debug/ test capability of catching error during computation (Hsu para [0061]).
Regarding claim 2, Hoang and Hsu teach the neural network array of claim 1. Hsu teaches wherein the selected characteristic is a voltage threshold (Vt) of the selected non-volatile memory cell (Hsu para [0008], para [0059]. See Also Hoang Fig. 9-Fig. 11).
Regarding claim 3, Hoang and Hsu teach the neural network array of claim 1. Hsu teaches wherein the output nodes are connected to positive and negative inputs of a comparator circuit to implement positive and negative synapse weights (See para [0129], para [0124], Fig. 22F, Fig. 22A: “…VA and VB are connected to the positive and negative inputs of the comparator, respectively, the synapses on …represent 'positive weight' and the synapses on …represents 'negative weight'…)
Regarding claim 4, Hoang and Hsu teach the neural network array of claim 1. Hsu teaches wherein the input nodes receive the input signals and complementary input signals to implement positive and negative synapse weights (see para [0129], para [0124]).
Regarding claim 5, Hoang and Hsu teach the neural network array of claim 1. Hsu teaches wherein each non-volatile memory cell is a 3D resistive memory cell (see para [0062], para [0009]).
Regarding claim 6, Hoang and Hsu teach the neural network array of claim 5. Hsu teaches wherein the selected characteristic is a resistance value of the selected non-volatile memory cell (para [0129], para [0130]: threshold of selector diode).
Regarding claim 7, Hoang and Hsu teach the neural network array of claim 5. Hsu teaches wherein each 3D resistive memory cell comprises a resistive random-access memory (RRAM) device (see para [0062], para [0009]: resistive memory employed).
Regarding claim 8, Hoang and Hsu teach the neural network array of claim 5. Hsu teaches wherein each 3D resistive memory cell comprises a phase change memory (PCM) devices (para [0062]).
Regarding claim 9, Hoang and Hsu teach the neural network array of claim 5. Hsu teaches wherein each 3D resistive memory cell comprises a threshold device (para [0007], para [0009]).
Regarding claim 10, Hoang and Hsu teach the neural network array of claim 9. Hsu teaches wherein the threshold device comprises a diode (Fig. 22F: selector diode and associated threshold employed per cell).
Regarding claim 11, Hoang and Hsu teach the neural network array of claim 1. Hsu teaches wherein the neural network array is configured as a three-dimensional (3D) memory array (para [0062]).
Regarding claim 12, Hoang and Hsu teach the neural network array of claim 1. Hsu teaches wherein a plurality of the neural network arrays are connected together to form a multiple-layer neural network (Fig. 23C), and wherein output nodes of one neural network layer are connected to input nodes of another neural network layer (para [0137]-para [0138] in context of Fig. 23B, Fig. 23C).
Regarding claim 13, Hoang and Hsu teach the neural network array of claim 12. Hsu teaches wherein output nodes of a last neural network layer are connected in a feedback configuration to input nodes of a first neural network layer to form a close-loop neural network (claimed limitations are broad and encompasses teachings of para [0106], Fig 14F, Fig. 4G).
Regarding claim 14, Hoang and Hsu teach the neural network array of claim 12. Hsu teaches wherein output nodes of any first selected neural network layer are selectively connected in a feedback configuration to input nodes of any second selected neural network layer to form a close-loop neural network (claimed limitations are broad and encompasses teachings of para [0106], Fig 14F, Fig. 4G).
Regarding claim 18, Hoang and Hsu teach the neural network array of claim 1. Hsu teaches wherein the non-volatile memory cells comprise resistive memory cells including a resistive layer and a selector device, and the selected characteristic is a resistance value adjusted during training (para [0062], Fig. 22F suggests the limitation in context of neural network and required training).
Regarding claim 20, Hoang and Hsu teach the neural network array of claim 1. Hoang teaches wherein the array is configured to implement analog neural networks by applying analog input voltages to the input nodes and using multiple threshold voltage levels in the non-volatile memory cells to represent analog synaptic weights (para [0065], para [0080], Fig. 16 configuration).
Allowable Subject Matter
Claims 15-17, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims:
15. The neural network array of claim 1, further comprising circuitry configured to perform direct in-array training by applying target voltages to the output nodes and propagating the target voltages through selected non-volatile memory cells to adjust the selected characteristic of the selected non-volatile memory cells.
16. The neural network array of claim 15, wherein the direct in-array training includes forward propagation using input signals applied to the input nodes and back- propagation using target voltages applied to the output nodes or bit lines connected thereto.
17. The neural network array of claim 1, wherein a plurality of the neural network arrays share a single synapse array and are configured to simulate multiple neural network layers by sequentially selecting different sets of weight select signals and feeding back outputs as inputs.
19. The neural network array of claim 1, further comprising source lines connected to the strings, wherein during back-propagation, target voltages are propagated from the output nodes through selected cells to the source lines to generate targets for previous layers.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant has not argued substantively against dependent claim specific limitations and previous rejections are being relied upon.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: Yoshida (US 2022/0137926 A1): Fig. 16 and associated disclosure applicable for all claims.
Bhardwaj (US 2020/0174864 A1): Fig. 1-Fig. 5 disclosure applicable for all claims.
It is suggested that applicant consider all prior arts made of record.
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825