Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/31/2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 10-12, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. US 2019/0189055 A1 to Zhang et al. (Zhang), U.S. Patent Application Publication No. US 2020/0320933 A1 to Zhou et al. (Zhou), U.S. Patent Application Publication No. US 2018/0069069 A1 to Ebisuno et al. (Ebisuno), and U.S. Patent Application Publication No. US 2020/0143741 A1 to Tsuboi et al. (Tsuboi).
As to claim 1, Zhang discloses a display device (Fig. 1, Par. 139), comprising: a plurality of pixels (Fig. 1, Par. 136) each including: a first driving transistor (D2) including a first electrode (1 of D2) connected to a first node (2 of T4) (Fig. 1, Pars. 66-67), a second electrode (2 of D2) connected to a second node (to 1 of T7 and T3) (Fig. 1, Par. 67), and a gate electrode connected to a third node to (at P) (Fig. 1, Par.67); a second driving transistor (D1) including a first electrode (1 of D1) connected to a fourth node (2 of T6) (Fig. 1, Par. 66), a second electrode (2 of D1) connected to the first node (2of T4) (Fig. 1, Par. 66), a gate electrode connected to the third node (at P) (Fig. 1, Par. 66), and a lower gate electrode which receives an emission control signal; a second transistor (T2) including a first electrode (1 of T2) which receives a data voltage (Vdata) Fig. 1, Par. 61), a second electrode (2 of T2) connected to the first node (Fig. 1, Pars. 61, 66-67), and a gate electrode which receives a write gate signal (Fig. 1, Par. 83); and a third transistor (T3) including a first electrode (1 of T3) connected to the second node (2 of D2) (Fig. 1, Pars. 62, 67), a second electrode (2 of T3) connected to the third node (at P) (Fig. 1, Pars. 62, 67), and a gate electrode which receives the write gate signal (Fig. 1, Par. 83); and a fifth transistor (T6) including a first electrode(1 of T6) which receives a driving voltage (ELVDD) (Fig. 1, Par. 65), a second electrode (2 of T6) connected to the fourth node(1 of D1) (Fig. 1, Pars. 65-66), a gate electrode which receives the emission control signal( EM) (Fig. 1, Par. 65), and
Zhang does not expressly disclose the second driving transistor including a lower gate electrode which receives an emission control signal; and the fifth transistor including a lower gate electrode physically and directly connected to the lower gate electrode of the second driving transistor.
Zhou discloses the second driving transistor including a lower gate electrode (G2) which receives an emission control signal (Figs. 1-4, Pars. 31-32; Fig. 4 shows that Dim is the same signal as EM).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Zhang with the teaching of Zhou to do light adjustment when required thereby provide an improved display device as suggested by Zhou (Par. 33).
Tsuboi discloses a fifth transistor (204) including a lower gate electrode (back gate) and a back gate of driving transistor (202) physically and directly connected to the light-emitting control signal (Vdd/emission control signal)(Figs. 18-19, Par. 40, see also Pars. 41-42).
Ebisuno discloses a fifth transistor (T5) including a lower gate electrode (G51) directly connected to the light-emitting control signal EM (Fig. 4, Par. 76).
Zhang as modified teaches the lower gate electrode of the second driving transistor will be directly connected the lower gate electrode of the fifth transistor since they all connected to the light-emitting control signal EM (see Zhou’s Figs. 1-4, Pars. 31-32; Fig. 4 shows that Dim is the same signal as EM and Ebisuno’s Fig. 4, Par. 76).
Zhang as modified teaches the lower gate electrode of the second driving transistor will be physically and directly connected the lower gate electrode of the fifth transistor since they all connected to the light-emitting control signal EM (see Zhou’s Figs. 1-4, Pars. 31-32, e.g. Fig. 4 shows that Dim is the same signal as EM and Ebisuno’s Fig. 4, Par. 76 and Tsuboi shows that the back gate of driving transistor 204 and the back gate of transistor 208 are connected to the same emission control signal Vdd, see Figs. 2-7, 18-19, Par. 40, see also Pars. 41-42).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Zhang as modified with the teaching of Ebisuno and Tsuboi to directly connect the lower gate of the fifth with the lower gate electrode of the second driving transistor to try with a reasonable expectation of success to minimizes a current leakage as suggested by Ebisuno (Par. 76) and to minimizes a current leakage as suggested by Tsuboi (Par. 47).
As to claim 2, Zhang as modified discloses in a compensation period (t3) (Fig. 3), the data voltage is applied to the gate electrode of the first driving transistor (D2) along the second transistor (T2), the first driving transistor (D2), and the third transistor (T3) (Figs. 1, 3, Par. 91) in response to the write gate signal or both the write gate signal (S1) and the compensation gate signal (S2) (Figs. 1, 3, Par. 91). See claim 1 motivation above.
As to claim 3, Zhang discloses in the compensation period, a threshold voltage of the first driving transistor is compensated (Figs. 1, Pars. 45, 93).
As to claim 4, Zhang discloses each of the pixels further includes: a fourth transistor (T1) including a first electrode (2 of T1) which receives a first initialization voltage (Vref) (Fig. 1, Pars. 60, 82, see also Pars. 78-79), a second electrode (1 of T1) connected to the third node (at P) (Fig. 1, Par. 60), and a gate electrode which receives an initialization gate signal (S1)(Fig. 1, Pars. 60, 82, see also Pars. 78-79).
As to claim 5, Zhang discloses in an initialization period, the first initialization voltage (Vref) initializes the gate electrode of the first driving transistor (D2) and the gate electrode of the second driving transistor (D1) in response to the initialization gate signal (S1) (Fig. 1, Par. 82).
As to claim 6, Zhang discloses each of the third transistor (T3) and the fourth transistor (T1) is an NMOS transistor (Fig. 1, Pars. 56-57).
As to claim 7, Zhang discloses each of the third transistor (T3) and the fourth transistor (T1) is a PMOS transistor (Fig. 1, Pars. 56-57).
As to claim 8, Zhang discloses each of the pixels further includes: a fifth transistor (T6) including a first electrode (1 of T6) which receives a driving voltage (ELVDD) (Fig. 1, Par. 65), a second electrode (2 of T6) connected to the fourth node (1 of D1) (Fig. 1, Pars. 65-66), and a gate electrode which receives the emission control signal (EM) (Fig. 1, Par. 65).
As to claim 10, Zhang discloses each of the pixels further includes: a sixth transistor (T7) including a first electrode (1 of T7) connected to the second node (2 of D2) (Fig. 1, Par. 68), a second electrode (2 of T7) connected to a fifth node (anode of L1) (Fig. 1, Par. 68), and a gate electrode which receives the emission control signal (EM) (Fig. 1, Pars. 68-69).
As to claim 11, Zhang discloses each of the pixels further includes: a light emitting element (L1) including a first electrode (anode) connected to the fifth node (2 of T7) and a second electrode (cathode) which receives a common voltage (ELVSS) (Fig. 1, Pars. 68-69).
As to claim 12, Zhang discloses in an emission period, the driving voltage (ELVDD) is applied to the first electrode of the light emitting element (L1) along the fifth transistor (T5), the second driving transistor (D1), the first driving transistor (D2), and the sixth transistor (T7) in response to the emission control signal (EM) (Fig. 1, Pars. 89, 92).
As to claim 16, Zhang discloses each of the pixels further includes: a storage capacitor (Cst) including a first electrode (2 of Cst) connected to the third node (at P) (Fig. 1, Pars. 59-60) and a second electrode (1 of Cst) which receives a driving voltage (ELVDD)(Fig. 1, Par. 59).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. US 2019/0189055 A1 to Zhang et al. (Zhang), U.S. Patent Application Publication No. US 2020/0320933 A1 to Zhou et al. (Zhou), U.S. Patent Application Publication No. US 2018/0069069 A1 to Ebisuno et al. (Ebisuno), and US 2020/0143741 A1 to Tsuboi et al. (Tsuboi); in view of U.S. Patent Application Publication No. US 2011/0279419 A1 to Takemura.
As to claim 13, Zhang does not expressly disclose in the emission period, a threshold voltage of the second driving transistor is about 0 voltage (V).
Takemura discloses in the emission period, a threshold voltage of the second driving transistor is about 0 voltage (V) (Par. 53, see also Par. 52).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Zhang with the teaching of Takemura since it is ideal thereby would provide an improved display as suggested by Takemura (Par. 53).
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. US 2019/0189055 A1 to Zhang et al. (Zhang), U.S. Patent Application Publication No. US 2020/0320933 A1 to Zhou et al. (Zhou), U.S. Patent Application Publication No. US 2018/0069069 A1 to Ebisuno et al. (Ebisuno), and U.S. Patent Application Publication No. US 2020/0143741 A1 to Tsuboi et al. (Tsuboi); in view of WO 2020/027445 A1 to Jeon et al. (see US 2021/0319747 A1 as translation).
As to claim 14, Zhang discloses each of the pixels further includes: a seventh transistor (T5) including a first electrode (1 of T5) connected to the fifth node (anode of L1) (Fig. 1, Par. 64).
Zhang does not expressly disclose a second electrode (2) which receives a second initialization voltage, and a gate electrode which receives a bypass gate signal.
Jeon discloses a seventh transistor (T7) including a second electrode which receives a second initialization voltage (Vinit2) (Fig. 2, Par. 75), and a gate electrode which receives a bypass gate signal (Sn+1) (Fig. 2, Par. 75).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Zhang with the teaching of Jeon to improve image quality as suggested by Jeon (Par. 1).
As to claim 15, Zhang discloses each of the first driving transistor (D2), the second driving transistor (D1), the second transistor (T2), the fifth transistor (T6), the sixth transistor (T7), and the seventh transistor (T5) is a PMOS transistor (Fig. 1, Pars. 56-57).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-7 and 10-16 have been considered but are moot in view of the new ground(s) of rejection.
Examiner notes that the new claim elements are now addressed by reference Tsuboi as necessitated by amendments. Please see above for full basis of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2023/0119632 A1 to Kwon et al. teaches a display with dual gate driving transistor.
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/JARURAT SUTEERAWONGSA/Examiner, Art Unit 2621
/LUNYI LAO/ Supervisory Patent Examiner, Art Unit 2621