DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 6/6/25, responding to the Office action mailed on 3/10/25,
has been entered into the record. The present Office action is made with all the suggested
amendments being fully considered. Accordingly, claims 1, 3, 5-22 are pending in this
application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5-7, and 12-21 are rejected under 35 U.S.C. 103 as being unpatentable over Cea (US 20140131660 A1) in view of Hanafi (US 20100133617 A1).
Re Claim 1 (Currently Amended) Cea teaches a semiconductor structure comprising:
a substrate (bottom, 102) ([0029]);
a layer over the substrate (top part of 102, FIG. 1A), the layer comprising insulator material ([0029] “upper insulator layer”);
a source region (110, FIG. 1A.) and a drain region (112) [0024];
a first body (104a) comprising a first semiconductor material ([0029] “nanowires”) extending laterally between the source (110) and drain regions (112) and directly on the layer comprising insulator material (top, 102) along an entire length of the first body (104a) between the source (110) and drain regions (112),
a second body (104B) [0023] comprising a second semiconductor material ([0029] “nanowires”) over the first body (104A) and extending laterally between the source (110) and drain regions(112),
a gate structure (108, [0023] “gate electrode stack”) at least in part wrapped around the first body (bottom 106 in FIG. 1B, [0023] “Each of the nanowires 104 includes a channel region 106…”) and fully wrapped around the second body (middle 106, FIG. 1B), the gate structure including (i) a gate electrode [0023] and (ii) a gate dielectric between the first body and the gate electrode and between the second body and the gate electrode ([0023] states, “The gate electrode stack 108 includes a gate electrode along with a gate dielectric layer disposed between the channel region 106 and the gate electrode (not shown).”).
Cea does not teach the first semiconductor material of the first body under biaxial tensile strain; and
the second body under biaxial tensile strain;
Hanafi teaches the first body (206 on left, Fig. 2D) is under biaxial tensile strain ([0024] says, “…the PMOS FinFET to provide biaxial compressive strain on the silicon germanium (SiGe) Fin 206.); and
the second body (206 on right, Fig. 2D) under biaxial tensile strain[0024].
The ordinary artisan would have been motivated to modify Hanafi in combination with Cea in the above manner for the motivation of using biaxial tensile strain on the device body as it can optimize device performance as transistors reach physical scaling limits.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Hanafi into the structure of Cea.
Re Claim 3 (Currently Amended) Cea in view of Hanafi teaches the semiconductor structure of claim 1, where in a bottom surface of the first body (Cea, 104A) is in direct contact with the layer comprising insulator material (top of 102, FIG. 1C), and the gate structure (108) is on a top surface and two side surfaces of the first body (104/106, FIG. 1B, [0023] states, “Each of the nanowires 104 includes a channel region 106…”).
Re Claim 5 (Currently Amended) Cea in view of Hanafi teaches the semiconductor structure of claim 1, wherein the first body (Cea, 104A) and the second body (104B) comprise silicon structures [0030].
Re Claim 6 (Currently Amended) Cea in view of Hanafi teaches the semiconductor structure of claim 1, wherein the first body (Cea, 104A) and the second body (104B) are included in a vertical stack including two or more nanowires, nanoribbons, or nanosheets ([0026] states, “In accordance with an embodiment of the present invention, the one or more nanowires 104 of the semiconductor device 100 are uniaxially strained nanowires. Thus, a semiconductor device may be fabricated from a single uniaxially strained nanowire (e.g., 104A) or from a plurality of vertically stacked uniaxially strained nanowires (104A-104C), as depicted in FIG. 1A.”).
Re Claim 7 (Currently Amended) Cea in view of Hanafi teaches the semiconductor structure of claim 1, further comprising: one or more additional bodies comprising the semiconductor material (Cea, [0030]) and extending laterally between the source (110) and drain regions (112, FIG. 1A), the semiconductor material of the one or more additional bodies (206, Fig. 2F) under biaxial tensile strain ([0024] says, “…the PMOS FinFET to provide biaxial compressive strain on the silicon germanium (SiGe) Fin 206.
Re Claim 12 (Original) Cea in view of Hanafi teach the semiconductor structure of claim 1, wherein the insulator material (Cea, top part of 102, FIG. 1A) comprises oxygen and silicon ([0029] states, “An upper insulator layer composed of a material which may include, but is not limited to, silicon dioxide…”.
Re Claim 13 (Currently Amended) Cea in view of Hanafi teach the semiconductor structure of claim 1, wherein the semiconductor material of the first body (Cea, 104a) is also under strain induced by the source and drain regions [0026].
Re Claim 14 (Currently Amended) Cea teaches an integrated circuit structure comprising:
a strained semiconductor on insulator (SSOI) structure (FIG. 1A) comprising:
a substrate (bottom part of 102, [0029], FIG. 1C),
an insulator layer (top part of 102, [0029]) over the substrate (FIG. 1C), and
a semiconductor layer (104A) directly on the insulator layer (FIG. 1C),
a first body (104B) and a second body (104C) both over the SSOI structure (FIG. 1C) and comprising a semiconductor material that is under biaxial tensile strain induced by the SSOI structure;
a source region (110) and a drain region (112) [0024], the first body (104B) and the second body (104C) between the source (110) and drain regions (112, FIG. 1A), and the semiconductor layer (104A) being directly on the insulator layer (top of 102) along an entire length (FIG.1A & 1C) of the semiconductor layer between the source (110) and drain regions (112); and
a gate structure (108) that that fully wraps around the first body and the second body (FIG. 1B and 1C: 108 fully wraps around bodies 104B and 104C as shown in modified FIG. 1B), the gate structure including (i) a gate electrode and (ii) gate dielectric separating the gate electrode from the first and second bodies [0023].
Cea does not teach the semiconductor layer, first body, and second body are under biaxial tensile strain induced by the SSOI structure.
Hanafi teaches a first body (206 on left, Fig. 2D), and second body (206 on right, Fig. 2D) are under biaxial tensile strain induced by the SSOI structure; ([0024] says, “…the PMOS FinFET to provide biaxial compressive strain on the silicon germanium (SiGe) Fin 206.)
Hanafi does not explicitly teach the semiconductor layer is under biaxial tensile strain induced by the SSOI structure, but one of ordinary skill can easily add a third body or an additional semiconductor layer to the device under biaxial tensile strain.
The ordinary artisan would have been motivated to modify Hanafi in combination with Cea in the above manner for the motivation of using biaxial tensile strain on the device body as it can optimize device performance as transistors reach physical scaling limits. Adding additional semiconductor layers and or device bodies under biaxial tensile strain can help optimize current in the integrated circuit structure. Further, it has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Hanafi into the structure of Cea.
Re Claim 15 (Currently Amended) Cea in view of Hanafi teach the integrated circuit structure of claim 14, wherein the insulator layer (top of 102) comprises oxygen (Cea, [0029] “An upper insulator layer composed of a material which may include, but is not limited to, silicon dioxide…”).
Re Claim 16 (Currently Amended) Cea in view of Hanafi teach the integrated circuit structure of claim 15, wherein the gate structure (108) only partially wraps around the semiconductor layer (108 does not completely wrap around 104A in x-y plane, FIG. 1A)
Re Claim 17 (Currently Amended) Cea teaches an integrated circuit structure comprising:
an insulator layer (top portion of 102 as shown in fig. 1C) [0025];
a first body (104A) and a second body (104B) [0023] (FIG.1C) above the first body,
a source region (110) and a drain region (112) [0024], the first body (104A) and the second body (104B) between the source and drain regions, wherein an entire length of the first body between the source and drain regions is directly on the insulator layer (FIG. 1A: at least middle portion of 104B and 104C disposed between 110 and 112); and
a gate structure that fully wraps around the second body (FIG. 1B and 1C: 108 fully wraps around bodies 104B and 104C as shown in modified fig 1B below), the gate structure including (i) a gate electrode and (ii) gate dielectric separating the gate electrode from the first and second bodies [0023].
Cea does not teach the first and second bodies comprising a semiconductor material that is under biaxial tensile strain; and
a gate structure that only partially wraps around the first body.
Hanafi teaches the first and second bodies (206 on left is 1st body, 206 on right is 2nd body, Fig. 2D) comprising a semiconductor material that is under biaxial tensile strain ([0024] says, “…the PMOS FinFET to provide biaxial compressive strain on the silicon germanium (SiGe) Fin 206.); and
a gate structure (220/250) [0029] that only partially wraps around the first body (206 on left, Fig. 2J).
The ordinary artisan would have been motivated to modify Hanafi in combination with Cea in the above manner for the motivation of using biaxial tensile strain on the device bodies as it can optimize device performance as transistors reach physical scaling limits. Also only wrapping part of the 1st body with the gate structure can allow one to easily optimize the current in the device bodies.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Hanafi into the structure of Cea.
Re Claim 18 (Currently Amended) Cea in view of Hanafi teaches the integrated circuit structure of claim 17, further comprising:
a substrate (Cea bottom of 102)[0029],
wherein the insulator layer (top of 102) is on the substrate (FIG. 1A).
Re Claim 19 (Currently Amended) Cea in view of Hanafi teaches the integrated circuit structure of claim 18, wherein: the first body, the insulator layer (Cea, upper part of 102) comprising insulator material ([0029] states, “An upper insulator layer composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride or silicon oxy-nitride is disposed on the lower bulk substrate.”), and the substrate (lower part of 102) form a strained semiconductor on insulator (SSOI) structure [0029].
Re Claim 20 (Original) Cea in view of Hanafi teaches the integrated circuit structure of claim 17, further comprising:
a first spacer (Cea, 116 on left side in fig. 1A) between the gate electrode (108) [0032] and the source region (110)[0024], and a second spacer (116 on right side in fig. 1A) between the gate electrode and the drain region (112), wherein the first spacer and the second spacer fully wrap around tip regions of the second body (fig. 1C: 116 fully wraps around middle and/or upper 104B) and only partially wrap around tip regions of the of the first body(fig. 1C).
Re Claim 21 (New) Cea in view of Hanafi the integrated circuit structure of claim 17, further comprising one or more additional bodies (Cea 104A, 104B) comprising the semiconductor material [0030] and extending laterally between the source (110) and drain regions (112), the semiconductor material ( Hanafi, 206 ) of the one or more additional bodies under biaxial tensile strain [0026].
The ordinary artisan would have been motivated to modify Inaba in combination with Cea in view of Hanafi in the above manner for the motivation to teach the substrate and body each contain silicon and to teach the Miller index of the substrate and the Miller index of body. The crystalline orientation is integral for device strength, and paragraph [0037] states, “Compressive stress is preferably applied in the channel width direction. Further, tensile stress is preferably applied in a direction perpendicular to the channel surface. By applying stress to the channel area in this manner, the electron mobility in the transistor may be enhanced”
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Cea in view of Hanafi and further in view of Zhang (US 20210358911 A1).
Re Claim 8 (Currently Amended) Cea in view of Hanafi teach the semiconductor structure of claim 1, but does not teach a first spacer between the gate electrode and the source region, and a second spacer between the gate electrode and the drain region, wherein the first spacer and the second spacer fully wrap around tip regions of the second body and partially wrap around tip regions of the first body.
Zhang teaches a first spacer (128) [0059] between the gate electrode (108) [0057] and the source region (152) [0059](fig. 2, fig. 3), and a second spacer (128) between the gate electrode and the drain region (152), where in the first spacer and the second spacer fully wrap around the tip regions of the second body (130) [0059] (Source/drain, spacer, and body names repeated), and partially wrap around tip regions of the first body (fig. 4: 128 at least partially wraps around bottom-most body 130).
The ordinary artisan would have been motivated to modify Zhang in combination with Cea in view of Hanafi in the above manner for the motivation of adding spacers between the gate electrodes and source and drain regions so the semiconductor operates in a peak capacity.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Zhang into the structure of Cea in view of Hanafi.
Re Claim 10 (Currently Amended) Cea in view of Hanafi and further in view of Zhang the semiconductor structure of claim 1, wherein: each the first body (130, Zhang), and the second body (130) comprises a corresponding middle region between corresponding tips regions (Zhang, fig. 2); and
the gate electrode (Zhang, 108) and the gate dielectric [0034](Paragraph states, “Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.”) at least in part wrap around the middle region of each of the first body and the second body (fig. 2).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cea in view of Hanafi, Zhang, and further in view of Kim (US 20210098626 A1).
Re Claim 9 (Original) Cea in view of Hanafi, Zhang teach the semiconductor structure of claim 8,
wherein the first and second spacers (262, Hanafi) (fig. 2j) compromise nitrogen [0032] (262 comprises nitride, and therefore implicitly includes nitrogen atoms).
Hanafi in view of Zhang does not teach the first and second spacers further comprise silicon.
Kim teaches the first and second spacers (140, Kim) (fig. 2) comprise silicon [0085].
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Kim into the structure of Cea in view of Hanafi, Zhang, to teach using nitride and silicon spacers to ensure the semiconductor works ideally.
The ordinary artisan would have been motivated to modify Kim in combination with Cea in view of Hanafi, Zhang in the above manner for the motivation of the first and second spacers comprising silicon and nitrogen, such as silicon nitride, to minimize the current leakage between the gate and the source/drain regions.
Claims 11 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Cea in view of Hanafi and further in view of Inaba (US 20160268432 A1).
Re claim 11 Cea in view of Hanafi teach the semiconductor structure of claim 1, but does not teach the substrate comprises silicon with crystalline orientation described by a Miller index of (100); and the first body comprises silicon with crystalline orientation described by a Miller index of (110).
Inaba teaches a semiconductor structure (fig. 16) including a substrate (34) and a first body (31a), wherein the substrate has a crystalline orientation described by a Miller index of {100} [0033, Inaba]; and the first body (42a) [0041] has a crystalline orientation described by a Miller index of {110}[0044] (channel area 31a contains the body).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Inaba into the structure of Cea in view of Hanafi to teach the substate comprises silicon with a {110} Miller index and the first body comprises silicon with a {110} Miller index.
The ordinary artisan would have been motivated to modify Inaba in combination with Cea in view of Hanafi in the above manner for the motivation to teach the substrate and body each contain silicon and to teach the Miller index of the substrate and the Miller index of body. The crystalline orientation is integral for device strength, and paragraph [0037] states, “Compressive stress is preferably applied in the channel width direction. Further, tensile stress is preferably applied in a direction perpendicular to the channel surface. By applying stress to the channel area in this manner, the electron mobility in the transistor may be enhanced”.
Re Claim 22 (New) Cea in view of Hanafi teaches the integrated circuit structure of claim 18, but does not teach the substrate comprises silicon with crystalline orientation described by a Miller index of (100); and the first body comprises silicon with crystalline orientation described by a Miller index of (110).
Inaba teaches a semiconductor structure (fig. 16) including a substrate (34) and first body (31a), wherein the substrate has a crystalline orientation described by a Miller index of {100} [0033, Inaba]; and the first body (42a) [0041] has a crystalline orientation described by a Miller index of {110} [0044] (channel area 31a contains the body).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Inaba into the structure of Cea in view of Hanafi to teach the substate comprises silicon with a {110} Miller index and the first body comprises silicon with a {110} Miller index.
The ordinary artisan would have been motivated to modify Inaba in combination with Cea in view of Hanafi in the above manner for the motivation to teach the substrate and body each contain silicon and to teach the Miller index of the substrate and the Miller index of body. The crystalline orientation is integral for device strength, and paragraph [0037] states, “Compressive stress is preferably applied in the channel width direction. Further, tensile stress is preferably applied in a direction perpendicular to the channel surface. By applying stress to the channel area in this manner, the electron mobility in the transistor may be enhanced”
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/4/25