DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9, 30, and 36 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to these claims the clause “the BIST wrapper having a and the interposer” is indefinite. Firstly the interposer does not have antecedent basis and “having a and” seems to be missing something. For both of these reasons combined it cannot be determined what is being claimed by this clause. For the below rejection, it is being interpreted to meaning the BIST wrapper being associated with an interposer.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 12, 26-28, 31, 32-34, and 37 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Teifel, US Patent No. 9,311,444 B1.
In reference to claim 26, Teifel teaches a method comprising:
managing, by processing circuitry, assignments of test interfaces such that the test interfaces are mapped from function interfaces to placeholder interfaces (Column 3, lines 15-20 a test-mode block is a logical functionality for configuring and re-mapping core stimulus signals and core observation signals according to the various functions that are to be performed with input and output via the test-port pins. The test-mode blocks are implemented in physical circuitry in the test-port interface),
wherein the test interfaces are mapped to the placeholder interfaces via mod ports (Table 1, Representative Test Port RTL Output File shows that the test-mode block is a module port, Column 8, line 58).
In reference to claim 27, Teifel teaches wherein a function interface comprises one or
more function control signal lines to access a function of the intellectual property (IP) block core, wherein the one or more function control signal lines to read a memory or write to the memory (Figure 3, Memory test mode, Column 3, lines 15-20 a test-mode block is a logical functionality for configuring and re-mapping core stimulus signals and core observation signals according to the various functions that are to be performed with input and output via the test-port pins. The test-mode blocks are implemented in physical circuitry in the test-port interface, Column 6, lines 37-38 Memory Test Mode enables the internal memory scan chains and allows the internal memories to be tested, Column 6, lines 44-46, In Memory Test Mode they respectively carry the internal (i.e. to or from the chip core) scan-test output, input, and enable signals).
In reference to claim 28, Teifel teaches wherein a test interface comprises one or more test control signal lines to access the function of the IP block core via the function interface (Figure 3, ATPG test mode, Column 3, lines 15-20 a test-mode block is a logical functionality for configuring and re-mapping core stimulus signals and core observation signals according to the various functions that are to be performed with input and output via the test-port pins. The test-mode blocks are implemented in physical circuitry in the test-port interface, Column 6, lines 34-36, “ATPG” stands for “Automatic Test Pattern Generation.” ATPG Test Mode enables the internal logic scan chains and allows the design to be tested with ATPG vectors, Column 6, lines 42-44 In ATPG Test Mode, they respectively carry the oscillator output signal, the scan-chain input signal, and the scan-chain-enable input signal.).
In reference to claim 31, Teifel teaches wherein the processing circuitry is coupled to a memory (Column 6, line 38 internal memories), the processing circuitry comprising one or more of application processing circuitry or graphics processing circuitry (Column 5, line 2, ASIC core).
In reference to claims 1, 2, 5, 12, 32-34, and 37, drawn to an apparatus and computer readable medium containing all of the same functional limitations as found in claims 26-28 and 31 as described above, the same rejections apply.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 6, 9, 29, 30, 35, and 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teifel, US Patent No. 9,311,444 B1.
In reference to claim 29, Teifel teaches claim 26 as describe above. Teifel further teaches wherein the mode ports to map the test interfaces to the placeholder interfaces wherein a mod port comprises one or more mod control signal lines to access the one or more test control signal lines (Table 1, Column 8, line 51 – Column 10, line 67, showing the mapping of the test interfaces to placeholder interfaces for each control mode of 0, 1, or 2). Teifel does not teach wherein the mod ports are associated with an interposer. However interposers are notoriously well known in the art as an electrical interface routing layer, acting as a bridge between a semiconductor chip (die) and a substrate or printed circuit board (PCB) to redistribute connections. OFFICIAL NOTICE IS TAKEN. Accordingly, it would have obvious for one of ordinary skill in the art at the time of invention to associate the mod ports of claims 26 and 29 with interposer because it would allow the mod ports to function as a bridge between the test interface and the placeholder interfaces in cases when they are a semiconductor chip (die) and a substrate or printed circuit board (PCB).
In reference to claim 30, Teifel teaches claim 26 as describe above. Teifel further teaches wherein the IP block core comprises a built-in self-test (BIST) wrapper (Figure 5 wrappers), wherein the BIST wrapper further comprises a segment insertion bit coupled to a BIST access port that is further coupled to a controller and the placeholder interfaces (Table 1, Column 8, line 51 – Column 10, line 67, showing the bistMode assignments). Teifel does not teach wherein the mod ports are associated with an interposer. However interposers are notoriously well known in the art as an electrical interface routing layer, acting as a bridge between a semiconductor chip (die) and a substrate or printed circuit board (PCB) to redistribute connections. OFFICIAL NOTICE IS TAKEN. Accordingly, it would have obvious for one of ordinary skill in the art at the time of invention to associate the mod ports of claims 26 and 29 with interposer because it would allow the mod ports to function as a bridge between the test interface and the placeholder interfaces in cases when they are a semiconductor chip (die) and a substrate or printed circuit board (PCB).
In reference to claims 6, 9, 35, and 36, drawn to an apparatus and computer readable medium containing all of the same functional limitations as found in claims 29 and 30 as described above, the same rejections apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON BOWERS whose telephone number is (571)272-1888. The examiner can normally be reached Flex M-F 7am-6pm.
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/B.B/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851