DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the RCE filed 1/15/2026 with claims filed 12/24/2025 in which claims 1, 5, 9, 13, and 21 were amended.
Claims 1-15 and 21-25 remain pending and are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-12, and 14-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Seo et al (US 2022/0037236 and Seo hereinafter).
As to claims 1-4 and 6-8: Seo discloses [claim 1] a semiconductor device (Figs. 1-2C; [0034]) comprising: source/drain epitaxial regions (SD; [0039]) disposed over a substrate (100; [0035]); source/drain contacts (CA contacts) (portion of CT1; [0044]) disposed in direct contact with the source/drain epitaxial regions (SD), wherein at least one of the CA contacts (Fig. 2A; right CT1) directly connects to a buried power rail (POR; [0037]) through a via-to-BPR (VBPR) contact (comprising CTE and a portion of CT1 from the left vertical surface of CT1 to the part of CT1 that is to the left of the left vertical surface of 134; [0044]); a dielectric cap (130; [0046]) disposed over one or more of the CA contacts (CT1); and a local interconnect (Figs. 2A and 2C; comprising 134 and 132 in contact with CT1) constructed in direct contact with one area (sidewalls and top surface) of the dielectric cap (130) such that a portion of the local interconnect (Fig. 2A; portion of 132 over the right CT1 overlaps with POR and is interpreted to be aligned with as they both lie along a vertical line that can be drawn through both) is vertically aligned with the buried power rail (POR), the local interconnect (Figs. 1 and 2C; portion 132 of local interconnect) having a dimension (along D1) that overlaps two of the CA contacts (132 can overlap with 4 CT1; claim doesn’t restrict to only 2 CA contacts), wherein a first end (looking at Fig. 2C, the bottom end (the first end) of 134 of the local interconnect directly contacts CT1) of the local interconnect (comprising 132 and 134) directly contacts one of the two overlapped contacts (second from left CT1 in Fig. 2C); [claim 2] wherein a via (144; [0047]) is disposed in direct contact with the local interconnect (comprising 132 and 134); [claim 3] wherein a metal line (M1) layer (142; [0047]) is disposed over and in contact with the via (144); [claim 4] wherein the local interconnect (comprising 132 and 134) is wired (through 144; [0047]) to a back end of line (BEOL) (142 is interpreted to be BEOL; [0047]); [claim 6] wherein the VBPR contact (comprising CTE and a portion of CT1 from the left vertical surface of CT1 to the part of CT1 that is to the left of the left vertical surface of 134) has a generally L-shaped configuration (as defined, VBPR of Seo is L-shaped); [claim 7] wherein a gate contact (CB) (Fig. 2B; 134 in direct contact with CT2; [0045]-[0046]) is disposed in direct contact with a sidewall of the dielectric cap (130); [claim 8] wherein a source/drain epitaxial region (left SD in Fig. 2A) of the source/drain epitaxial regions (SD) is wired to a metal line (M1) layer (142; [0047]) at a different cell (left cell of Fig. 2A) over a recessed source/drain epitaxial region (the recessed source/drain region is that in which SD is formed for the right SD regions/right cell) connected to the buried power rail (POR) through the VBPR contact (comprising CTE and a portion of CT1 from the left vertical surface of CT1 to the part of CT1 that is to the left of the left vertical surface of 134).
As to claims 9-12 and 14-15: Seo discloses [claim 9] a semiconductor device (Figs. 1-2C; [0034]) comprising: source/drain epitaxial regions (SD; [0039]) disposed over a substrate (100; [0035]); source/drain contacts (CA contacts) (portion of CT1; [0044]) disposed in direct contact with the source/drain epitaxial regions (SD), wherein at least one of the CA contacts (Fig. 2A; right CT1) directly connects to a buried power rail (POR; [0037]) through a via-to-BPR (VBPR) contact (comprising CTE and a portion of CT1 from the left vertical surface of CT1 to the part of CT1 that is to the left of the left vertical surface of 134; [0044]); a dielectric cap (130; [0046]) disposed over one or more of the CA contacts (CT1); a local interconnect (Figs. 2A and 2C; comprising 134 and 132 in contact with CT1) constructed in direct contact with one area (sidewalls and top surface) of the dielectric cap (130) such that a portion of the local interconnect (Fig. 2A; portion of 132 over the right CT1 overlaps with POR and is interpreted to be aligned with as they both lie along a vertical line that can be drawn through both) is vertically aligned with the buried power rail (POR), the local interconnect (Figs. 1 and 2C; portion 132 of local interconnect) having a dimension (along D1) that overlaps two of the CA contacts (132 can overlap with 4 CT1; claim doesn’t restrict to only 2 CA contacts), wherein a first end (looking at Fig. 2C, the bottom end (the first end) of 134 of the local interconnect directly contacts CT1) of the local interconnect (comprising 132 and 134) directly contacts one of the two overlapped contacts (second from left CT1 in Fig. 2C); and a backside power distribution network (BSPDN) (150; [0049]) disposed adjacent (adjacent is interpreted to mean near and POR and 150 are near each other vertically) the backside power rail (POR); [claim 10] wherein a via (144; [0047]) is disposed in direct contact with the local interconnect (comprising 132 and 134); [claim 11] wherein a metal line (M1) layer (142; [0047]) is disposed over and in contact with the via (144); [claim 12] wherein the local interconnect (comprising 132 and 134) is wired (through 144; [0047]) to a back end of line (BEOL) (142 is interpreted to be BEOL; [0047]); [claim 14] wherein the VBPR contact (comprising CTE and a portion of CT1 from the left vertical surface of CT1 to the part of CT1 that is to the left of the left vertical surface of 134) has a generally L-shaped configuration (as defined, VBPR of Seo is L-shaped); [claim 15] wherein a source/drain epitaxial region (left SD in Fig. 2A) of the source/drain epitaxial regions (SD) is wired to a metal line (M1) layer (142; [0047]) at a different cell (left cell of Fig. 2A) over a recessed source/drain epitaxial region (the recessed source/drain region is that in which SD is formed for the right SD regions/right cell) connected to the buried power rail (POR) and the BSPDN (150) through the VBPR contact (comprising CTE and a portion of CT1 from the left vertical surface of CT1 to the part of CT1 that is to the left of the left vertical surface of 134).
Allowable Subject Matter
Claims 5 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 21-25 are allowed over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art, Seo, discloses a semiconductor device (Figs. 1-2C; [0034]) comprising: source/drain epitaxial regions (SD; [0039]) disposed over a substrate (100; [0035]); source/drain contacts (CA contacts) (portion of CT1; [0044]) disposed in direct contact with the source/drain epitaxial regions (SD), wherein at least one of the CA contacts (Fig. 2A; right CT1) directly connects to a buried power rail (POR; [0037]) through a via-to-BPR (VBPR) contact (comprising CTE and a portion of CT1 from the left vertical surface of CT1 to the part of CT1 that is to the left of the left vertical surface of 134; [0044]); a dielectric cap (130; [0046]) disposed over one or more of the CA contacts (CT1); and a local interconnect (Figs. 2A and 2C; comprising 134 and 132 in contact with CT1) constructed in direct contact with one area (sidewalls and top surface) of the dielectric cap (130) such that a portion of the local interconnect (Fig. 2A; portion of 132 over the right CT1 overlaps with POR and is interpreted to be aligned with as they both lie along a vertical line that can be drawn through both) is vertically aligned with the buried power rail (POR). Seo fails to expressly disclose where a first end of the local interconnect rests on an un-recessed portion of a CA contact associated with a first source/drain epitaxial region and a second end of the local interconnect rests on a recessed portion of a CA contact associated with a second source/drain region.
Response to Arguments
Applicant’s arguments with respect to claims 1-4, 6-12, and 14-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813