DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
It is indefinite what is meant by the groove portion being “shallower” with in increase from the wide with portion. Specifically, it is unclear as to shallower referring back to what?
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mori et al. (US PGPub 20140091444, hereinafter referred to as “Mori”).
Mori discloses the semiconductor device as claimed. See figures 1-3 and corresponding text, where Mori teaches, in claim 1, a semiconductor device, comprising:
an insulating substrate (13);
a semiconductor element (17); and
an oxide film (15B) or a nitride film that is different from the insulating substrate, wherein the insulating substrate (13) includes an insulating layer and a metal circuit pattern (14) provided on an upper surface of the insulating layer, the
semiconductor element (17) is solder joined to an upper surface (15A) of the metal circuit pattern, the oxide film or the nitride film is provided in a region where the semiconductor element (17) is not solder joined in the upper surface of the metal circuit pattern (14), and the oxide film or the nitride film is disposed such that an entirety of the oxide film or an entirety of the nitride film does not overlap not to be overlapped with the semiconductor element (17) in a plan view (figures 1A and 1B; [0011-0016]), and the oxide film or the nitride film is further provided on a side surface of the metal circuit pattern (figure 1B; [0015-0016], the examiner views that Mori only removes part of the oxide to form a recess thus a side surface of the oxide exists).
Mori teaches, in claim 2, wherein the oxide film or the nitride film is provided in 95 % or more of an area of the region where a solder joint is not performed in the upper surface of the metal circuit pattern (figures 1A and 1B; [0011-0016], the examiner views the area surrounding the entire sides and upper portions covered with the oxide film 95% or more).
Mori teaches, in claim 3, wherein the region where the semiconductor element is solder joined in the upper surface of the metal circuit pattern is rougher than the region where the solder joint is not performed in the upper surface of the metal circuit pattern ([0026], the examiner views that the recess has a smaller metal oxide ratio than other parts of the top surface of the metal plate).
Mori teaches, in claim 4, wherein a depression portion is formed on the upper surface of the metal circuit pattern, and the semiconductor element is solder joined on a bottom surface of the depression portion (figures 1A and 1B; [0011-0016]).
Mori teaches, in claim 5, wherein a depth of the depression portion is larger than a thickness of a solder material between the metal circuit pattern and the semiconductor element ([0026], the examiner views that the recess has a smaller metal oxide ratio than other parts of the top surface of the metal plate).
Mori teaches, in claim 6, wherein a groove portion is formed along an outer periphery of the semiconductor element on the upper surface of the metal circuit pattern, and a region where the oxide film or the nitride film is provided includes a wall surface of the groove portion (figures 1A and 1B; [0011-0016]).
Mori teaches, in claim 7, wherein a cross section of the groove portion has a rectangular shape (figures 1A and 1B; [0011-0016]).
Mori teaches, in claim 8, wherein a region where the oxide film or the nitride film is provided includes 95 % or more of an area of the wall surface of the groove portion (figures 1A and 1B; [0011-0016], the examiner views the area surrounding the entire sides and upper portions covered with the oxide film 95% or more).
Mori teaches, in claim 9, wherein a planar shape of the semiconductor element has a corner, the groove portion includes a wide width portion having a larger width than another portion in a portion of the corner of the semiconductor element, and a wall surface of the wide width portion includes a portion where the oxide film or the nitride film is not provided ([0026], the examiner views that the recess has a smaller metal oxide ratio than other parts of the top surface of the metal plate).
Mori teaches, in claim 10, wherein a planar shape of the semiconductor element is a rectangular shape, and the groove portion includes a wide width portion in each of four corner portions of the semiconductor element having the rectangular shape (figures 1A and 1B; [0011-0016]).
Mori teaches, in claim 12, wherein the groove portion and the semiconductor element are not overlapped with each other in a plan view (figures 1A and 1B; [0011-0016]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mori et al. (US PGPub 20140091444, hereinafter referred to as “Mori”).
Mori discloses the semiconductor device substantially as claimed. See the rejection above, however Mori fails to show, in claim 13, wherein a thickness of the oxide film or the nitride film is equal to or larger than 20 nm and equal to or smaller than 2000 nm.
However, Mori teaches, in claim 13, forming an oxide layer using surface oxidation ([0015]). In addition, Mori provides the advantages that by surface oxidation and then removing oxide layer to form a recess at the top surface of the metal plate allows for good wetting for the solder allowing for good bonding ([0032]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the filing date of the invention, to incorporate wherein a thickness of the oxide film or the nitride film is equal to or larger than 20 nm and equal to or smaller than 2000 nm, in the device of the Mori, according to the teachings of Mori, with the motivation of adjusting the recess of the for the purpose of allowing for good wetting for the solder and allowing good bonding between the metal plate. a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007),
Allowable Subject Matter
Claims 14-26 are allowed over the prior art of record.
The following is an examiner’s statement of reasons for allowance: the closest prior art of record and to the examiner’s knowledge does not suggest or render obvious a semiconductor device particularly characterized by where the second metal circuit pattern is not solder joined in the upper surface of the base plate, and the oxide film or the nitride film is disposed not to be overlapped with the second metal circuit pattern in a plan view, as detailed in claim 14. Claims 15-26 depend from claim 14.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 11/05/25 have been fully considered but they are not persuasive. In the remarks applicant raises the clear issue as to whether Mori suggests “the oxide film or nitride film is further provided on a side surface of the metal circuit pattern”.
The Examiner views that Mori does suggest the above limitation and/or statements. Specifically, Mori teaches forming a oxide film to surrounding the entire metal plate just not where the oxide is removed for form a recess at the top surface of the metal plate (14) (figure 1B; [0015]), thus meets the limitation of a side surface containing an oxide film.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 February 22, 2026