DETAILED ACTION
This Office Action is in response to the applicant's amendment filed April 27th, 2026. In virtue of this communication, claims 1, 3, 4, 9, 10, and 21-28 are currently presented in the instant application. Claims 2 and 5-8 are withdrawn from further consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3, 4, 9, and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the first portion" in line 11. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation is understood to be --the top portion--.
Claim 1 recites the limitation "the periphery of the die attach pad" in line 11. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation is understood to be --a periphery of the die attach pad--.
Claims 3, 4, 9, and 10 are also rejected as they depend from claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 9, 10 and 21-27 are rejected under 35 U.S.C. 103 as being unpatentable over How et al. (US 2015/0054145 A1; hereinafter How).
With respect to claim 1, How discloses an integrated circuit (IC) package 110 in at least Figs. 5 and 6, comprising:
a silicon die 32 having a first side 36 and a second side 34 (see Figs. 5 and 6 and paragraphs 12, 15, 16, 19, 21; in paragraph 21 note silicon thickness of controller die and that the controller die is incorrectly numbered 34);
an adhesive layer 38 attached to the first side 36 of the silicon die 32 (see Fig. 5 and paragraphs 14, 16, 20);
a die attach pad 14 having a mounting surface (where 16 contacts 38), the mounting surface having a smaller area than an area of the adhesive layer 38, the silicon die 32 mounted on the die attach pad 14 at the mounting surface (where 16 contacts 38) so that edges of the silicon die 32 and the adhesive layer 38 overhang the die attach pad 14 without touching the die attach pad 14 (see Figs. 5 and 6 and paragraphs 11, 12, 14, 16, 18; note multiple instances where controller die is incorrectly numbered 34 in the description of How), the die attach pad 14 including a top portion (TP; part of 14 that contacts 38 at 16) with a first height H1 and a bottom portion (BP; parts of 14 at recessed portions 62, 64, 66, 72, 76) having a second height H2, the first height H1 and the second height H2 from a bottom surface 18 of the die attach pad 14, second height H2 less than the first height H1, the second height H2 being uniform from an edge of the top portion TP to a periphery of the die attach pad 14 (see Figs. 5 and 6 and paragraphs 18, 19; also see Fig. 5 annotated below. H2 is uniform within BP from TP to arbitrarily defined die attach pad periphery); and
one or more leads 20 that are spaced apart from the edges of the silicon die 32 and the adhesive layer 38 (see Figs. 5 and 6 and paragraphs 12, 13, 15).
How does not explicitly disclose the adhesive layer covering an entire area of the first side.
How discloses in paragraph 17 that “in the integrated circuit package of FIG. 3, a defect is caused by a hole 56 produced in the center of the die attach film layer 38 by an ejector needle (not shown) that pushed through the layer 38 during die ejection from a die bonding machine (not shown)…the result of such a hole in the film layer 38 is often a short circuit and resulting failure of the integrated circuit package 10.” How continues in paragraph 19 that as “further shown by FIG. 5, the intersecting channels 74, 64 create an open space between the center of the controller die 34 where any die attach film void 56 produced by an ejector pin would be located. Thus, there is no electrical path provided between the bottom surface 36 of the controller die 34 and the die attach paddle 14. Thus, this potential failure causing defect is also obviated by the die paddle half etching configuration shown in FIG. 6.”
However, How discloses in paragraph 20 that “in situations where an ejector pin void 56 is rarely encountered, the etching of channels 64 and 74 could be eliminated.” In the instances that the ejector pin void 56 is rarely encountered, the nonconductive die attach film layer 38 would obviously cover an entire area of the first side of 36 of the silicon die 32.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the adhesive layer of How would cover an entire area of the first side (of the silicon die) because How discloses that there are situations where the ejector pin void 56 is rarely encountered and, in those situations, where no ejector pin void is present the adhesive layer would cover the entire are of the first side (see How: paragraph 20 and MPEP 2144 I).
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With respect to claim 3, How discloses the IC package of claim 1, wherein the die attach pad 14 includes an etched area (at recessed portions 62, 64, 66, 72, 74, 76) so that the top portion TP has a smaller length and width than the bottom portion BP (see Figs. 5 and 6 and paragraphs 18, 19; also see Fig. 5 annotated above).
With respect to claim 4, How discloses the IC package of claim 3, wherein the etched area in the top portion of the die attach pad 14 is half-etched (see Figs. 5 and 6 and paragraphs 18, 19, 21, 22).
With respect to claim 9, How discloses the IC package of claim 1, wherein the one or more leads 20 are laterally spaced apart from the edges of the silicon die 32 and the adhesive layer 38 (see Figs. 5 and 6 and paragraphs 12, 15).
With respect to claim 10, How discloses the IC package of claim 1, further comprising: one or more bond wires 31 coupling contacts on the second side 34 of the silicon die 32 to the one or more leads 20 (see Figs. 5 and 6 and paragraph 15); a silicon debris 52 attached to an edge of the adhesive layer 38 (see Figs. 5 and paragraphs 16, 18); and a mold compound 40 encapsulating the silicon die 32, the adhesive layer 38, and the die attach pad 14, the mold compound 40 filling a space where the edges of the silicon die 32 and the adhesive layer 38 overhang the die attach pad 14 (see Figs. 5 and 6 and paragraphs 12, 15, 21; note die attach paddle 14 is part of lead frame 12).
With respect to claim 21, How discloses an integrated circuit (IC) package 110 in at least Figs. 5 and 6, comprising:
a silicon die 32 having a first side 36 and a second side 34 (see Figs. 5 and 6 and paragraphs 12, 15, 16, 19, 21; in paragraph 21 note silicon thickness of controller die and that the controller die is incorrectly numbered 34);
an adhesive material 38 covering an area of the first side 36 (see Fig. 5 and paragraphs 14, 16, 20); and
a die attach pad 14 comprising a first portion (P1; portion of 18 directly below and aligned with perimeter of 38) and a second portion (P2; portion of 14 at 16 in direct contact with 38), a width of the first portion P1 approximately same as a width of the adhesive material 38, and a width of the second portion P2 less than the width of the first portion P1, the second portion P2 contacting the adhesive material 38 (see Figs. 5 and 6 and paragraphs 11, 12, 14, 16, 18; also see Fig. 5 annotated below; note multiple instances where controller die is incorrectly numbered 34 in the description of How); wherein a height HP1 of the first portion P1 is uniform from an edge of the second portion P2 to a periphery of the die attach pad 14 (see Figs. 5 and 6 and paragraphs 18, 19; also see Fig. 5 annotated below. HP1 is uniform within P1 from P2 to arbitrarily defined die attach pad periphery).
How does not explicitly disclose the adhesive material covering an entire area of the first side.
How discloses in paragraph 17 that “in the integrated circuit package of FIG. 3, a defect is caused by a hole 56 produced in the center of the die attach film layer 38 by an ejector needle (not shown) that pushed through the layer 38 during die ejection from a die bonding machine (not shown)…the result of such a hole in the film layer 38 is often a short circuit and resulting failure of the integrated circuit package 10.” How continues in paragraph 19 that as “further shown by FIG. 5, the intersecting channels 74, 64 create an open space between the center of the controller die 34 where any die attach film void 56 produced by an ejector pin would be located. Thus, there is no electrical path provided between the bottom surface 36 of the controller die 34 and the die attach paddle 14. Thus, this potential failure causing defect is also obviated by the die paddle half etching configuration shown in FIG. 6.”
However, How discloses in paragraph 20 that “in situations where an ejector pin void 56 is rarely encountered, the etching of channels 64 and 74 could be eliminated.” In the instances that the ejector pin void 56 is rarely encountered, the nonconductive die attach film layer 38 would obviously cover an entire area of the first side of 36 of the silicon die 32.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the adhesive layer of How would cover an entire area of the first side (of the silicon die) because How discloses that there are situations where the ejector pin void 56 is rarely encountered and, in those situations, where no ejector pin void is present the adhesive layer would cover the entire are of the first side (see How: paragraph 20 and MPEP 2144 I).
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With respect to claim 22, How discloses the IC package of claim 21, further comprising one or more leads 20 that are spaced apart from the edges of the silicon die 32 and the adhesive layer 38 (see Figs. 5 and 6 and paragraphs 12, 15).
With respect to claim 23, How discloses the IC package of claim 22, wherein the silicon die 32 is electrically connected to the one or more leads 20 (see Figs. 5 and 6 and paragraph 15).
With respect to claim 24, How discloses the IC package of claim 22, wherein the silicon die 32 is electrically connected to the one or more leads 20 using bond wires 31 (see Figs. 5 and 6 and paragraph 15).
With respect to claim 25, How discloses the IC package of claim 21, further comprising mold compound 40 covering portions of the silicon die 32, the die attach pad 14, and the adhesive material 38 (see Figs. 5 and 6 and paragraphs 12, 15, 21; note die attach paddle 14 is part of lead frame 12).
With respect to claim 26, How discloses the IC package of claim 21, wherein a side of the first portion (P1; portion of 18 directly below and aligned with perimeter of 38) is exposed from a surface of the IC package 110 (see Fig. 5 and paragraph 15; also see Fig. 5 annotated above).
With respect to claim 27, How discloses the IC package of claim 21 further comprising a silicon debris 52 attached to an edge of the adhesive layer 38 (see Fig. 5 and paragraphs 16, 18).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over How et al. (US 2015/0054145 A1; hereinafter How) in view of Li et al. (US 2017/0033058 A1; hereinafter Li).
With respect to claim 28, How discloses the IC package of claim 21.
How does not disclose wherein the adhesive material is a B-stage film.
Li discloses an IC package in at least Fig. 3 wherein an adhesive material 265 is a B-stage film (see Fig. 3 and paragraphs 23, 27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the adhesive material of How would be a B-stage film because B-stage film is a well-known adhesive material and it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill (see MPEP 2144.07).
Response to Arguments
Applicant's arguments filed April 27th, 2026 have been fully considered but they are not persuasive.
The applicant argues that “Claim 1 as amended recites ‘the die attach pad including a top portion with a first height and a bottom portion having a second height, the first height and the second height from a bottom surface of the die attach pad, second height less than the first height, the second height being uniform from an edge of the first portion to the periphery of the die attach pad’. Applicant submits that none of the cited references show, teach, or suggest at least this limitation. For example, How fails to teach at least this limitation. The die attach pad 14 of How has the same height as the portion 84 instead of the height of the portion between the portions 82, 84. As such, Claim 1 and Claims dependent thereon are allowable.” Additionally, the applicant argues that “Claim 21 as amended recites ‘wherein a height of the first portion is uniform from an edge of the second portion to a periphery of the die attach pad’. As none of the cited references show, teach, or suggest at least this limitation, it is believed Claim 21 and Claims dependent thereon are allowable.” The examiner respectfully disagrees.
With respect to claim 1, How discloses the die attach pad 14 including a top portion (TP; part of 14 that contacts 38 at 16) with a first height H1 and a bottom portion (BP; parts of 14 at recessed portions 62, 64, 66, 72, 76) having a second height H2, the first height H1 and the second height H2 from a bottom surface 18 of the die attach pad 14, second height H2 less than the first height H1, the second height H2 being uniform from an edge of the top portion TP to a periphery of the die attach pad 14 (see Figs. 5 and 6 and paragraphs 18, 19; also see Fig. 5 annotated below. H2 is uniform within BP from TP to arbitrarily defined die attach pad periphery). With respect to claim 21, How discloses wherein a height HP1 of the first portion P1 is uniform from an edge of the second portion P2 to a periphery of the die attach pad 14 (see Figs. 5 and 6 and paragraphs 18, 19; also see Fig. 5 annotated below. HP1 is uniform within P1 from P2 to arbitrarily defined die attach pad periphery). In both instances the height from of the edge of the top portion/second portion to a periphery of the die attach pad is uniform. The periphery is not defined. As rejected the periphery is simply away from the top portion/second portion. This area could be better defined by claiming that an entire area of the die attach pad that is not part of the top portion/second portion is the bottom portion/first portion, and the second height/height of the bottom portion/first portion is uniform from an edge of the top portion to the periphery of the die attach pad.
The claims remain rejected as outlined above.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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