DETAILED ACTION
This action is responsive to communications: 12/11/2025.
In the response filed, applicant amended claims 7, and 18. No other claims are cancelled or added. Claims 7-24 are pending. Claims 7, and 18 are independent.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/11/2025 has been entered.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings. C) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
No Priority
4. No priority claimed, see ADS.
No Information Disclosure Statement
5. No IDS is in the record.
Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
9. Claims 7-14, and 18-23 is/are rejected under 35 U.S.C. 103 as being obvious over Wheeler (US 2016/0188250 A1), in view of Noel (US 2017/0345505 A1).
Regarding independent claim 7, Wheeler teaches an apparatus (Fig. 2A, Fig. 3: 330, Fig. 4A-Fig. 4J, para [0068]), comprising:
a sense amplifier (Fig. 2A: 250 “sensing circuitry”. See also Fig. 3) coupled to a primary bit line (Fig. 2A: digit n-1) and a complementary bit line (Fig. 2A: digit n-1-) of first and second data memory cells (e.g., Fig. 4A: cells in COL0/ rows 404-0, and COL0/ row 404-1. See Fig. 3 cells in relation to Fig. 4: column 0 and different rows) and a first control memory cell (Fig. 4A: cell in COL0, row 404-4, predetermined bit pattern cell used to select “bit vector” for logic operations) in a common column (Fig. 4A: COL0),
wherein first (Fig. 3: 304-0) and second (Fig. 3: 304-1) data word lines are coupled to the first (Fig. 3: cell with col 0/ row 0) and second (Fig. 3: cell with col 0/ row 1) data memory cells, respectively (see also Fig. 4A. para [0073), and
a first control word line (Fig. 3: 304-4, see also Fig. 4A: 404-4) is coupled to the first control memory cell (Fig. 4A: cell in COL0/ row 404-4, bit pattern cell); and
a control circuit (para [0045]: controller or processing resources providing signals e.g., LOAD, AND, OR) coupled to the sense amplifier (Fig. 2A: 250. See also Fig. 3),
the control circuit to perform a logic operation involving bits in the first and second data memory cells (para [0025]: sort operation which includes other operation. para [0079]: “…bit-vectors … serve as operands to the logical operations in association with sorting the elements…”. Thus, data memory cells of COL0/ 474-0 and COL0/474-1 are used in logic operation),
wherein to perform the logic operation, the control circuit is to concurrently activate the first and second data word lines and the first control word line (Fig. 4A, para [0100]: sort function various logical operations require concurrent activation of bit pattern and bit vectors since bit pattern selects the bit vectors upon which logical operation is performed) and
to receive a bit comprising a result (Fig. 4A-Fig. 4J: result bit in SA 450 after e.g., compare operation) of the logic operation from the sense amplifier (Fig. 3: SA, Fig. 4A-Fig. 4J: 450 transfers data to controller or processing resource).
Wheeler is silent with respect to provisions of this claim which pertains to concurrently activating word lines and control lines for logic operation, and receiving logic operation result which corresponds to a majority value from the first, second, and control memory cells.
Noel teaches -
a sense amplifier (para [0047]: “read circuit” and Fig. 2 computing circuitry) coupled to a primary bit line (Fig. 2: RBLT) and a complementary bit line (Fig. 2: RBLF) of first (Fig. 2: 12 with data A) and second (Fig. 2: 12 with data B) data memory cells and a first control memory cell (Fig. 2: 22, 24. These control cells are employed per column and controls logic operation discussed in para [0059]) in a common column (Fig. 2 column associated with bit line and complementary bit line; para [0059]),
wherein first (Fig. 2: top RWLT, RWLF) and second (Fig. 2: bottom RWLT, RWLF) data word lines are coupled to the first (Fig. 2: 12 with data A) and second (Fig. 2: 12 with data B) data memory cells, respectively, and
a first control word line (Fig. 2: PCHT, PCHF) is coupled to the first control memory cell (Fig. 2: 22, 24); and
a control circuit (Fig. 2: 14 CTRL) coupled to the sense amplifier (operably coupled),
the control circuit to perform a logic operation involving (involving is broad and inclusive of other related operation) bits in the first and second data memory cells (para [0012], para [0051], para [0058]),
wherein to perform the logic operation, the control circuit is to concurrently activate (activated at the same time for any period of time during overall operation) the first and second data word lines and the first control word line (Fig. 2 in context of para [0012], para [0051], para [0058], para [0059]: top RWLT, bottom RWLT, PCHT are simultaneously activated for logic operation) and
to receive a bit comprising a result of the logic operation from the sense amplifier (para [0012], para [0051], para [0058]),
wherein the result corresponds to a majority value from the first, second, and control memory cells (para [0051]-para [0053]).
Wheeler and Noel are in the same field of endeavor of compute in memory operation, logic operation using memory circuitry and they are in analogous filed of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Noel’s logic operation circuitry into the apparatus of Wheeler such that claimed limitation can be met in order to reduce power consumption and reduce heat dissipation (Background Noel Background).
Regarding claim 8, Wheeler and Noel teach the apparatus of claim 7. Wheeler teaches wherein: the sense amplifier (Fig. 3: SA) comprises a primary output node (Fig. 3: SSA) coupled to the primary bit line and a complementary output node coupled to the complementary bit line (Fig. 3 array columns, see para [0068]); and
the control circuit is (processing resource and controller) to receive the bit comprising the result of the logic operation from the primary output node of the sense amplifier (para [0069]).
Regarding claim 9, Wheeler and Noel teach the apparatus of claim 7. Wheeler teaches wherein: to perform the logic operation, the control circuit is to write a 1 bit to the first control memory cell (Fig. 4A: writing pattern “1” to cell of COL0/404-4); and
the logic operation comprises an OR of the bits in the first and second data memory cells (para [0079]: OR operation. See also para [0078]-para [0080]: logical operations. Noel para [0028] also teaches the limitation since any binary bit is stored in two cells in column, then OR operation is performed).
Regarding claim 10, Wheeler and Noel teach the apparatus of claim 7. Wheeler teaches wherein: to perform the logic operation, the control circuit is to write a 0 bit to the first control memory cell (Fig. 4D: writing pattern “0” to cell of COL0/ row 404-4); and the logic operation comprises an AND of the bits in the first and second data memory cells (Wheeler para [0079]: AND operation. para [0078]-para [0080]: logical operations associated with sort operation steps. Noel para [0028] also teaches the limitation since any binary bit is stored in two cells in column, then AND operation is performed).
Regarding claim 11, Wheeler and Noel teach the apparatus of claim 7. Wheeler teaches wherein: the sense amplifier is coupled to a third data memory cell and a second control memory cell in the common column; a third data word line is coupled to the third data memory cell; a second control word line is coupled to the second control memory cell; and to perform the logic operation, the control circuit is to concurrently activate the first, second and third data word lines, and the first and second control word lines. (See claim 18 rejection analysis since claimed limitations are substantially identical).
Regarding claim 12, Wheeler and Noel teach the apparatus of claim 11. Noel teaches wherein: to perform the logic operation, the control circuit is to write a 1 bit to the first and second control memory cells; and the logic operation comprises an OR of bits in the first, second and third data memory cells (Noel para [0012], para [0028], para [0050] teaches the limitation since any binary bit is stored in two or more cells in the column, then OR operation is performed).
Regarding claim 13, Wheeler and Noel teach the apparatus of claim 11. Noel teaches wherein: to perform the logic operation, the control circuit is to write a 1 bit and a 0 bit to the first and second control memory cells, respectively; and the logic operation comprises a majority operation for bits in the first, second and third data memory cells (Noel para [0012], para [0028], para [0050] teaches the limitation since any binary bit is stored in two or more cells in the column, then logic operation is performed).
Regarding claim 14, Wheeler and Noel teach the apparatus of claim 11. Noel teaches wherein: to perform the logic operation, the control circuit is to write a 0 bit to the first and second control memory cells; and the logic operation comprises an AND of bits in the first, second and third data memory cells (Noel para [0028] also teaches the limitation since any binary bit is stored in two or more cells in column, then AND operation is performed).
Regarding independent claim 18, Wheeler teaches an apparatus (Fig. 1: 100 computing system), comprising:
a memory device to store instructions (in context of para [0033]: storage in Fig. 1: 110 holds instructions); and
a processor (para [0033]: 140) to execute the instructions to perform a logic operation (para [0033]) involving bits in first (Fig. 3: cell with col 0/ row 0), second (Fig. 3: cell with col 0/ row 1) and third (Fig. 3: cell with col 0/ row 2) data memory cells (See Fig. 2A, Fig. 3, Fig. 4A-Fig. 4J),
wherein: the first, second and third data memory cells (Fig. 4A: cells with col 0 and rows 0-2) are in a common column with first and second control memory cells (Fig. 4A: cell with COL 0/ 404-4, and COL 0/ 404-5, bit pattern cells);
first, second and third data word lines (Fig. 3: 304-0, 304-1, 304-2) are coupled to the first, second and third data memory cells (See Fig. 3: cells in COL 0 with 304-0, 304-1, 304-2. See Fig. 4A: cells with col 0 and rows 0-2), respectively;
first (Fig. 3: 304-4, see also Fig. 4A-Fig. 4J) and second (Fig. 3: 304-4, see also Fig. 4A-Fig. 4J) control word lines are coupled to the first (Fig. 4A-Fig. 4J: cell in COL0, row 404-4, bit pattern cell) and second (Fig. 4A-Fig. 4J: cell in COL0, row 404-5, bit pattern cell) control memory cells, respectively; and
to perform the logic operation, the processor is to write data to the first and second control memory cells based on the logic operation (predetermined data pattern provided by host for compare operation. See Fig. 4A),
concurrently activate the first, second and third data word lines and the first and second control word lines (Fig. 4A-Fig. 4J sort with various logical operations requires concurrent activation of all rows), and
receive a bit comprising a result (Fig. 4A-Fig. 4J: result bit in SA 450 after e.g., compare operation) of the logic operation from the sense amplifier (Fig. 3: SA, Fig. 4A-Fig. 4J: 450 transfers data to controller or processing resource).
Wheeler is silent with respect to provisions of this claim which pertains to concurrently activating word lines and control lines for logic operation, and receiving logic operation result which corresponds to a majority value from the first, second, third, first control, and second control memory cells.
Noel teaches -
Processor (Fig. 2: 14 and host processor combined) concurrently activate the first, second and third data word lines (Fig. 2: 12 in three rows, three cells and associated word lines. See para [0049]: “…two or a number greater than two of elementary cells of a same column of the circuit…”) and the first (Fig. 2: PCHT) and second (Fig. 2: PCHF) control word lines (Fig. 2 in context of para [0012], para [0051], para [0058], para [0059]: top RWLT, bottom RWLT, PCHT are simultaneously activated for logic operation), and
receive a bit comprising a result of the logic operation from the sense amplifier (para [0012], para [0051], para [0058]),
wherein the result corresponds to a majority value from the first, second, third, first control, and second control memory cells (para [0051]-para [0053]).
Wheeler and Noel are in the same field of endeavor of compute in memory operation, logic operation using memory circuitry and they are in analogous filed of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Noel’s logic operation circuitry into the apparatus of Wheeler such that claimed limitation can be met in order to reduce power consumption and reduce heat dissipation (Background Noel Background).
Regarding claim 19, Wheeler and Noel teach the apparatus of claim 18. Noel teaches wherein: the common column comprises a primary bit line and a complementary bit line (Fig. 2: column associated with RBLT, RBLF);
the sense amplifier (para [0047]: “read circuit” and Fig. 2 computing circuitry) comprises a primary output node (Fig. 2: RBLT, RBLF node) coupled to the primary bit line and a complementary output node coupled to the complementary bit line (Fig. 2: RBLT, RBLF),
to perform the logic operation, the processor is to write a 1 bit to the first and second control memory cells; the logic operation comprises A OR B OR C, where A, B and C are bits in the first, second and third data memory cells, respectively (Noel para [0012], para [0028], para [0050] teaches the limitation since any binary bit is stored in two or more cells in the column, then OR operation is performed); and
the bit comprising the result of the logic operation is received from the primary output node of the sense amplifier (Fig. 2: RBLT, RBLF node captures result of logic OR operation).
Regarding claim 20, Wheeler and Noel teach the apparatus of claim 18. Noel teaches wherein: the common column comprises a primary bit line and a complementary bit line Fig. 2: column associated with RBLT, RBLF); the sense amplifier comprises a primary output node coupled to the primary bit line and a complementary output node (Fig. 2: RBLT, RBLF node) coupled to the complementary bit line (Fig. 2: RBLT, RBLF);
to perform the logic operation, the processor is to write a 1 bit to the first control memory cell and a 0 bit to the second control memory cell; the logic operation comprises a majority operation for bits in the first, second and third data memory cells (Noel para [0012], para [0028], para [0050] teaches the limitation since any binary bit is stored in two or more cells in the column, then OR operation is performed); and
the bit comprising the result of the logic operation is received from the primary output node of the sense amplifier (Fig. 2: RBLT, RBLF node captures result of logic OR operation).
Regarding claim 21, Wheeler and Noel teach the apparatus of claim 18. Noel teaches wherein: the common column comprises a primary bit line and a complementary bit line; the sense amplifier comprises a primary output node coupled to the primary bit line and a complementary output node coupled to the complementary bit line; to perform the logic operation, the processor is to write a 0 bit to the first and second control memory cells; the logic operation comprises A AND B AND C, where A, B and C are bits in the first, second and third data memory cells; and the bit comprising the result of the logic operation is received from the primary output node of the sense amplifier (Fig. 2 in context of para [0028], para [0053], para [0058]).
Regarding claim 22, Wheeler and Noel teach the apparatus of claim 18. Noel teaches wherein: the common column comprises a primary bit line and a complementary bit line; the sense amplifier comprises a primary output node coupled to the primary bit line and a complementary output node coupled to the complementary bit line; and the bit comprising the result of the logic operation is received from the primary output node of the sense amplifier (Noel Fig. 2, para [0012], para [0028], para [0050], para [0053], para [0058]: either of the output node can be used for logic operation).
Regarding claim 23, Wheeler and Noel teach the apparatus of claim 18. Noel teaches wherein: the common column comprises a primary bit line and a complementary bit line; the sense amplifier comprises a primary output node coupled to the primary bit line and a complementary output node coupled to the complementary bit line; and the bit comprising the result of the logic operation is received from the complementary output node of the sense amplifier (Noel Fig. 2, para [0012], para [0028], para [0050], para [0053], para [0058]: either of the output node can be used for logic operation).
Allowable Subject Matter
Claims 15-17 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In addition, any associated 112b rejection (see section 7a, 7b above) must be over-come.
Regarding claims 15-17, the prior art of record does not appear to teach, suggest, or provide motivation for combination for “…sense amplifier is coupled to a fourth data memory cell and a third control memory cell in the common column; a fourth data word line is coupled to the fourth data memory cell; a third control word line is coupled to the third control memory cell; and to perform the logic operation, the control circuit is to copy a bit from the third data memory cell to the fourth data memory cell, and concurrently activate the first, second, third and fourth data word lines, and the first, second and third control word lines…”
Regarding claim 24, the prior art of record does not appear to teach, suggest, or provide motivation for combination for “… perform the logic operation, the control circuit is to write a 1 bit to the first and second control memory cells and a 0 bit to the third control memory cell; and the logic operation comprises (A AND B) OR C, where A and B are bits in the first and second data memory cells, respectively, and C is the bit in the third and fourth data memory cells.”
Response to Arguments
Previously set 112b rejection is being withdrawn based on applicant’s persuasive arguments dated 12/11/2025.
Applicant’s arguments with respect to claim(s) 7, and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant has not argued substantively against dependent claim specific limitations and previous rejections are being relied upon.
In general, applicant's arguments are not persuasive since they do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: Shimano (US 20090207642 A1): all figures and disclosure applicable for all claims. Hush (US 10755766 B2): Fig. 1-Fig. 8 disclosure applicable for all claims. SUMBUL (US 2019 / 0042199 A1): Fig. 1-Fig. 14 disclosure applicable for all claims. Cheng (US 2013/0194860 A1): Fig. 3 disclosure applicable for all claims. It is suggested that applicant consider all prior arts made of record.
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825