DETAILED ACTION
Claims 1-20 are currently presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Following Applicants amendments, the 112 rejection of the claims is Withdrawn.
Following Applicants arguments and amendments, the 102 rejection of the claims is Maintained.
Applicant’s Argument: Applicant’s arguments directed the 102 rejection are based on newly amended subject matter.
Examiner’s Response: All arguments are addressed in the 102 rejection of the claims below.
Applicant’s Argument: The cited reference does not teach claim 7.
Examiner’s Response: The Examiner disagrees and points to the cited sections. The tools and simulation environment include Veloce StratoM is an emulator which includes chips used as processing devices to which the compiled DUT is mapped. Therefore the device under test test bench is a processing thread executing processes. Next, a workstation is used to simulate the test environment (abstract, Section 2.6, Section 4.5.1) which is a second processing thread. Therefore, the cited reference teaches the two threads as required through the two different computing domains of Veloce StratoM and Workstation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kokkonen “AXI-STREAM VIP OPTIMIZATION FOR SIMULATION ACCELERATION”, in view of Davis et al. USPPN 2004/0010401.
Regarding claim 1, Kokkonen anticipates receiving simulation input data from a testbench executing on a computer system by a simulator interface executing on the computer system; (Figures 4, 11-16, Sections 1, 2.3, 4.1-4.3, simulation input data from a testbench run on a server executing an API is received)
receiving simulation output data by the simulator interface according to a hardware bus protocol specified by a simulated circuit for communication; (Figures 11-16, Sections 4.1-4.3, an AXI protocol is specified by the simulated circuit and used for sending out data)
simulating by the simulator interface, handshaking with the simulated circuit according to the hardware bus protocol in response to receiving the simulation input data and simulation output data; (Section 4.3, the AXI handshaking protocol is followed based on receiving input and output data)
forwarding the simulation input data to the simulated circuit by the simulator interface according to the hardware bus protocol; and (Figures 11-16, Sections 4.1-4.3, the simulation input data is provided according to the AXI protocol)
forwarding the simulation output data to the testbench by the simulator interface, (Figures 11-16, Sections 4.1-4.3, the output data is sent back to the testbench by the interface)
wherein the simulator interface is configured handle bus protocol specific interactions with the simulated circuit while interfacing with language-standard input/output streams of the testbench. (Section 4.3 The information is sent over a bus; Figures 3, 4 and 13, Sections 2.3-2.4 and 2.6, the driver converts the input signals to the AXI-4 protocol and sends them over the bus from both the device under test and testbench; Sections 4.2-4.3 Figure 16, AXI-4 stream is the protocol used to handle interactions including handshaking and interfaces with the input and output of the device under test)
Regarding claim 2, Kokkonen anticipates the limitations of claim 1. Kokkonen also anticipates wherein receiving the simulation input data includes receiving the simulation input data via a software standard output stream implemented by the testbench. (Figures 4, 5, 7, 13, 15, Section 2.4-2.6.2, 4.1-4.3, The simulation data is received from the output stream (bi-directional) implemented at the test bench)
Regarding claim 3, Kokkonen anticipates the limitations of claim 1. Kokkonen also anticipates wherein forwarding the simulation output data includes forwarding the simulation output data via a software standard input stream implemented by the testbench. (Figures 4, 5, 7, 13, 15, Section 2.4-2.6.2, 4.1-4.3, The simulation data is received from the input stream (bi-directional) implemented at the test bench)
Regarding claim 4, Kokkonen anticipates the limitations of claim 1. Kokkonen also anticipates simulating generation of a clock signal to the simulation of the simulated circuit by the simulator interface in response to a specification of the clock signal by the testbench. (Sections 2.3, 2.6.1, 4.1.1-4.3, Programs 1-3, a clock is created based on a specification of the testbench)
Regarding claim 5, Kokkonen anticipates the limitations of claim 4. Kokkonen also anticipates wherein simulating generation of the clock signal includes driving a clock port of the simulation of the simulated circuit with values that alternate every half period in response to the specification of the clock signal specifying a value of the half period. (Sections 2.6-2.6.1, 4.1.1-4.4, Programs 1-4, the clock can be divided into sub-cycles including a value of the half period)
Regarding claim 6, Kokkonen anticipates the limitations of claim 4. Kokkonen also anticipates wherein simulating generation of the clock signal includes driving a clock port of the simulation of the simulated circuit with values that alternate in response to the specification of the clock signal specifying a first duration of one of the alternating values and a second duration of another of the alternating values. (Sections 2.6-2.6.1, 4.1.1-4.4, Programs 1-4, the clock can be divided into sub-cycles including making the clock wait for different numbers of cycles based on the values received)
Regarding claim 7, Kokkonen anticipates the limitations of claim 1. Kokkonen also anticipates executing the simulation of the simulated circuit by a first thread; (Figures 11-16, Sections 4-4.3, the simulation of the circuit is done in one domain)
executing the testbench by a second thread; (Figures 11-16, Sections 4-4.3, the simulation of the circuit is done in one domain)
wherein forwarding the simulation output data includes forwarding the simulation output data via a software standard input stream implemented by the testbench; and (Figures 11-16, Sections 4-4.3, AXI stream is used to receive the provided simulation output data)
polling the software standard input stream by the second thread. (Figures 11-16, Sections 4-4.3, Programs 1-6, the input stream is polled by the testbench)
Examiner’s Note: For the purposes of examination, the Examiner is interpreting the two different domains as two different threads.
Regarding claim 8, Kokkonen anticipates the limitations of claim 1. Kokkonen also anticipates receiving the simulation input data includes: receiving the simulation input data via a software standard output stream implemented by the testbench, and (Figures 11-16, Sections 4-4.3, AXI stream is used to receive the provided simulation input data)
storing the simulation input data in an input buffer; and (Figures 4, 11-16, Sections 1, 2.3, 4-4.3, the simulation input data is stored in the input buffer of the computer system)
forwarding the simulation input data to the simulated circuit includes: reading the simulation input data from the input buffer, and(Figures 4, 11-16, Sections 1, 2.3, 4-4.3, the data is read from the buffer to provide to the simulated circuit)
forwarding the simulation input data to a data port of the simulated circuit. (Figures 4, 11-16, Sections 1, 2.3, 4-4.3, the data is provided to a data port of the simulated circuit)
Regarding claim 9, Kokkonen anticipates the limitations of claim 1. Kokkonen also anticipates receiving the simulation output data includes transferring the simulation output data from a data port of the simulated circuit to an output buffer; and (Figures 4, 11-16, Sections 1, 2.3, 4-4.3, the simulation output data is stored in the output buffer of the computer system)
forwarding the simulation output data includes: reading the simulation output data from the output buffer, and(Figures 4, 11-16, Sections 1, 2.3, 4-4.3, the data is read from the buffer)
forwarding the simulation output data to the testbench via a software standard input stream implemented by the testbench. (Figures 4, 11-16, Sections 1, 2.3, 4-4.3, the data is provided to the testbench using the AXI standard)
Regarding claim 10, Kokkonen anticipates the limitations of claim 1. Kokkonen also anticipates receiving the simulation input data includes receiving the simulation input data via a software standard output stream implemented by the testbench, and asserting a first VALID handshake signal to the simulated circuit by the simulator interface; (Section 4.3, A TVALID handshake signal is sent; See also Figures 4, 11-16, Sections 4-4.3)
forwarding the simulation input data includes waiting for assertion of the first VALID handshake signal and assertion of a first READY signal from the simulated circuit before providing the simulation input data; (Section 4.3, After the TVALID handshake signal is sent, a TREADY signal is sent; See also Figures 4, 11-16, Sections 4-4.3)
forwarding the simulation output data includes providing the simulation output data via a software standard input stream implemented by the testbench and asserting a second READY signal to the simulated circuit by the simulator interface; and(Section 4.3, After the first TREADY signal is sent, a second TREADY signal is sent; See also Figures 4, 11-16, Sections 4-4.3)
receiving the simulation output data includes waiting for assertion of the second READY signal and assertion of a second VALID signal from the before receiving the simulation output data. (Section 4.3, After the two TREADY signals are sent, and two TVALID signals are sent, data is exchanged; See also Figures 4, 11-16, Sections 4-4.3)
In regards to claim 11, it is the system embodiment of claim 1 with similar limitations to claim 1, and is such rejected using the same reasoning found in claim 1.
In regards to claim 12, it is the system embodiment of claim 3 with similar limitations to claim 3, and is such rejected using the same reasoning found in claim 3.
In regards to claim 13, it is the system embodiment of claim 2 with similar limitations to claim 2, and is such rejected using the same reasoning found in claim 2.
In regards to claim 14, it is the system embodiment of claim 4 with similar limitations to claim 4, and is such rejected using the same reasoning found in claim 4.
In regards to claim 15, it is the system embodiment of claim 5 with similar limitations to claim 5, and is such rejected using the same reasoning found in claim 5.
In regards to claim 16, it is the system embodiment of claim 6 with similar limitations to claim 6, and is such rejected using the same reasoning found in claim 6.
In regards to claim 17, it is the system embodiment of claim 7 with similar limitations to claim 7, and is such rejected using the same reasoning found in claim 7.
In regards to claim 18, it is the system embodiment of claim 8 with similar limitations to claim 8, and is such rejected using the same reasoning found in claim 8.
In regards to claim 19, it is the system embodiment of claim 9 with similar limitations to claim 9, and is such rejected using the same reasoning found in claim 9.
In regards to claim 20, it is the system embodiment of claim 10 with similar limitations to claim 10, and is such rejected using the same reasoning found in claim 10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
PADMAJA DUGGISETTY "DESIGN AND IMPLEMENTATION OF A HIGH PERFORMANCE NETWORK PROCESSOR WITH DYNAMIC WORKLOAD MANAGEMENT”: Also teaches the use of AXI-4 stream with bus protocol handling with a language standard I/O stream.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL COCCHI whose telephone number is (469)295-9079. The examiner can normally be reached 7:15 am - 5:15 pm CT Monday - Thursday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ryan Pitaro can be reached at 571-272-4071. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL EDWARD COCCHI/Primary Examiner, Art Unit 2188
Prosecution Insights