DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed 4/13/2026 with respect to claim(s) 1-3, 8, 11-12, and 15-20 have been considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8, 11, 12, 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ogihara (US PGPub 2007/0069220) in view of Shim et al. (US 6,100,103; hereinafter “Shim”), Chu (US PGPub 2018/0212104), and Suzuki et al. (US PGPub 2010/0051975; hereinafter “Suzuki”).
Re claim 1: Ogihara teaches (e.g. fig. 2 and 6) a light emitting diode (LED) pixel for a display, comprising: a light source (110a, 110b, 110c, 110d, 110e, 110f; hereinafter referred to as “LS”) configured to generate light and including a first type layer (n-type layer 110a) and at least one active layer (emission layer 110b; e.g. paragraph 64); a lower insulation layer (140) surrounding a side surface (side surface of LS) of the light source (LS), the lower insulation layer (140) including holes (holes for wiring connecting to 110a, 110d; hereinafter “VH”); a plurality of conductors (conductors to 108, 105, 107; hereinafter “VC”) electrically connected to the light source (LS); and wherein one of the conductors (108) does not overlap (108 does not overlap 130c) the at least one active layer (130c).
Ogihara is silent as to explicitly teaching the first type layer has a mesa region and an extension region extended from the mesa region, the extension region being thinner than the mesa region; an upper insulation layer surrounding the side surface of the light source and covering an entire upper region of the light source such that the upper insulation layer extends continuously from a first side surface of the light source across the entire upper region and to a second side surface of the light source opposite to the first side surface; wherein an outer boundary of the upper insulation layer is greater than that of the light source, in plan view; and wherein a bottom surface of the light source and a bottom surface of the upper insulation layer are coplanar with each other.
Shim teaches (e.g. fi8g. 5A) the first type layer (11) has a mesa region (region B-B’) and an extension region (region A-A’) extended from the mesa region (B-B’), the extension region (A-A’) being thinner than the mesa region (B-B’).
Chu teaches (e.g. fig. 3) an upper insulation layer (330, 370) surrounding the side surface of the light source (light emitted from active layer 316) and covering an entire upper region (upper part of 316, which is on the bottom side in fig. 3) of the light source (316) such that the upper insulation layer (330, 370) extends continuously (besides the opening for the conductors, 330, 370 is provided continuously, insomuch as PVT1 is provided continuously) from a first side surface (left side of 316) of the light source (316) across the entire upper region (upper part of 316, which is on the bottom side in fig. 3) and to a second side surface (right side of 316) of the light source (316) opposite to the first side surface; wherein an outer boundary of the upper insulation layer (330, 370) is greater than that of the light source (316), in plan view.
Suzuki teaches (e.g. fig. 1) a bottom surface (bottom surface of 11 of 10-1) of the light source (10-1) and a bottom surface (bottom surface of 32-1) of the upper insulation layer (32-1) are coplanar with each other (the two bottom surfaces outlined above are coplanar)
It would have been obvious to one of ordinary skill in the art at the time of effective filling, absent unexpected results, to use the thinned extension region as taught by Shim, to use the upper insulation layer as taught by Chu, and to use the upper insulation layer as taught by Suzuki in the device of Ogihara in order to have the predictable result of improving carrier distribution within the doped layers of the LED since carriers would be injected from the middle of the layers instead of the upper layer, and in order to have the predictable result of using a dielectric to protect the LED from contamination from exposure to the elements, and in order to have the predictable result of properly encapsulating the LED structure and ensuring longevity, respectively.
Re claim 2: Ogihara teaches the LED pixel for a display of claim 1, wherein a surface of the lower insulation layer (140) opposes a surface (bottom surface of 140) of the first type layer (110a).
Re claim 3: Ogihara in view of Shim, Chu, and Suzuki teaches the LED pixel for a display of claim 1, wherein the side surface of the light source (LS) is closer to a center of the light source (LS) than outer surface (outer surfaces of 104) of the upper insulation layer (330 of Chu).
Re claim 8: Ogihara in view of Shim, Chu, and Suzuki teaches the LED pixel for a display of claim 1, wherein an upper surface of the upper insulation layer (330, 370 of Chu) is disposed on a higher elevation than that of the light source (LS).
Re claim 12: Ogihara teaches the LED pixel for a display of claim 1, wherein the light source (LS) comprises a plurality of light emitting parts (110b, 110e, 130c) configured to emit light having different wavelengths from each other (see paragraph 83).
Re claim 15: Ogihara teaches the LED pixel for a display of claim 1, wherein the one of the conductors (VC) are disposed near a corner (108 is near 110b) of the LED pixel.
Re claim 16: Ogihara teaches the LED pixel for a display of claim 1, wherein: the light source (LS) further comprise a plurality of semiconductor layers (110a-110f); and the one of the conductors (VC) is disposed over at least one of the semiconductor layers (107 overlaps 110f), but does not overlay the at least one active layer (108 does not overlap 110f).
Re claim 17: Ogihara in view of Shim, Chu, and Suzuki teaches the LED pixel for a display of claim 1, wherein the upper insulation layer (330, 370 of Chu) comprises at least one of polyimide and epoxy molding compound (polyimide; e.g. paragraph 93 of Ogihara).
Re claim 18: Ogihara teaches the LED pixel for a display of claim 1, further comprising a substrate (101) on which the light source (LS) is disposed, wherein side surfaces of the substrate (101) are flush with side surfaces of the upper insulation layer (104).
Re claim 19: Ogihara teaches the LED pixel for a display of claim 18, wherein the substrate comprises at least one of a sapphire substrate, a SiC substrate (SiC; e.g. paragraph 93), a GaN substrate, a InGaN substrate, an AlGaN substrate, an AlN substrate, a Ga203 substrate, a glass substrate, and a silicon substrate.
Re claim 20: Ogihara teaches a display apparatus, comprising: a plurality of the LED pixels (used in displays; e.g. paragraph 8) of claim 1.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ogihara in view of Shim, Chu, and Suzuki as applied to claim 1 above, and further in view of Sunohara (US PGPub 2006/0040463).
Re claim 11: Ogihara in view of Shim, Chu, and Suzuki teaches substantially the entire structure as recited in claim 1 except explicitly teaching the LED pixel for a display further comprising: a second upper insulation layer disposed on the upper insulation layer; and a plurality of bumps disposed on the second upper insulation layer, wherein the bumps are electrically connected to the conductors.
Sunohara teaches (e.g. fig. 11) a second upper insulation layer (19a) disposed on the upper insulation layer (18a); and a plurality of bumps (27) disposed on the second upper insulation layer (19a), wherein the bumps (27) are electrically connected to the conductors (18b).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the bump formation structure as taught by Sunohara in the device of Ogihara in order to have the predictable result of using a known structure for electrically connecting a packaged device for proper operation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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