DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Drawing Objections
Applicant has amended the drawings at issue and the previous objections have therefore been withdrawn.
Prior Art Rejections
Applicant's arguments filed 11/14/2025 have been fully considered but they are not persuasive.
Applicant asserts Kamboh teaches equal group sizes for carry-skip adders and thus teaches away from differing group sizes for such adders (remarks pg. 8, first paragraph). Examiner respectfully disagrees. Kamboh merely presents an exemplary carry-skip adder design with equal group sizes and does not discuss that a carry-skip adder cannot have differing group sizes. Therefore, Kamboh does not teach away from differing group sizes.
Applicant asserts Lehman does not teach, and teaches away from, unequal or differing sized skip groups in an adder that has RCA stages for MSBs and LSBs (remarks pg. 8, second paragraph). Examiner respectfully disagrees. Kamboh discusses redistributing a group of equal-sized carry skip adders to become nonequal groups in Section VI. In Kamboh’s carry-skip adder, there are three distinct groups: RCA for LSBs, group of equal-sized carry-skip adders, and RCA for MSBs. One of ordinary skill of the art would be motivated to redistribute the group of equal-sized carry-skip based on Lehman without needing to modify the RCA stages for LSBs and MSBs. Furthermore, Lehman Fig. 6(a) is an exemplary 48-bit adder with 4-bit stages wherein the first and last 4-bit stages are not part of carry-skip adder groups, and can thus be interpreted by one of ordinary skill in the art as 4-bit RCAs. Therefore, Lehman suggests the teachings of differing sized skip groups can be applied to an adder that has RCA stages for MSBs and LSBs, and thus does not teach away from RCA stages for MSBs and LSBs.
Applicant asserts that Kamboh and Lehman each separately and in combination teach away from the claimed adder and a person of ordinary skill in the art would not be motivated to modify the references to produce the claimed adder. Examiner respectfully disagrees. As discussed above, neither Kamboh nor Lehman teach away from the modifications to produce the claimed adder, and thus one of ordinary skill in the art would have motivation to attempt the modifications, as Lehman asserts “nonequal carry-skip groups reduces propagation time compared to equal groups”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 21, 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over Kamboh et al. (FPGA implementation of fast adder, hereinafter “Kamboh”) in view of Lehman et al. (Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic Units, hereinafter “Lehman”).
As per claim 1, Kamboh teaches An adder implemented in a field programmable gate array (FPGA) (Kamboh: pg.1324 right col second paragraph), comprising: a first ripple carry adder block, for least significant bits of the adder (Kamboh: pg.1325 right col third paragraph, Fig. 4); and a second ripple carry adder block, for most significant bits of the adder (Kamboh: pg.1325 right col third paragraph, Fig. 4).
However, while Kamboh shows carry-skip adder blocks, Kamboh does not explicitly disclose differing carry skip adder blocks. Thus, Kamboh does not teach a plurality of carry skip adder blocks of differing block sizes, each block size relating to bit-width of input to a block, for a plurality of bits of the adder;
Lehman teaches a plurality of carry skip adder blocks of differing block sizes, each block size relating to bit-width of input to a block, for a plurality of bits of the adder (Lehman: pg. 694 Section VI);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the carry-skip adder blocks of Kamboh with the nonequal group carry-skip adder blocks teachings of Lehman. One would have been motivated to combine these references because both references disclose carry-skip adder designs, and the nonequal carry-skip groups reduces propagation time compared to equal groups (Lehman: pg. 694 right col first paragraph).
As per claim 3, Kamboh/Lehman further teaches The adder implemented in the FPGA of claim 1, wherein: critical path delay for a carry of the adder is lower in comparison to critical path delay for a carry of a ripple carry adder that could be implemented in the FPGA as having a same overall input bit-width as the adder (This is a property of the structure of the combination).
As per claim 4, Kamboh/Lehman further teaches The adder implemented in the FPGA of claim 1, wherein: area of the adder, in the FPGA, is lower in comparison to an area of a further carry skip adder that could be implemented in the FPGA composed of carry skip adder blocks having a fixed block size equal to a largest of the differing block sizes of the plurality of carry skip adder blocks of the adder (This is a property of the structure of the combination).
As per claim 5, Kamboh/Lehman further teaches The adder implemented in the FPGA of claim 1, wherein: the differing block sizes increase from a first carry skip adder block, at a first end of the plurality of carry skip adder blocks, towards at least one carry skip adder block in a middle of the plurality of carry skip adder blocks and decrease from the at least one carry skip adder block in the middle of the plurality of carry skip adder blocks towards a second carry skip adder block, at a second end of the plurality of carry skip adder blocks (Lehman: pg. 694 Section VI, Table I).
As per claim 6, Kamboh/Lehman further teaches The adder implemented in the FPGA of claim 1, wherein: at least one of the plurality of carry skip adder blocks includes a wide AND gate logic for fast block propagate carry generation (Lehman: Fig. 1).
As per claim 21, the claim is directed to an adder that implements the same or similar features as the adder of claim 1, and is therefore rejected for at least the same reasons therein. Furthermore, Kamboh/Lehman teaches a first ripple carry adder block having two or more one bit-width adders, for two or more least significant bits of the adder (Kamboh: pg.1325 right col third paragraph, Fig. 4); a second ripple carry adder block having two or more one bit-width adders, for two or more most significant bits of the adder (Kamboh: pg.1325 right col third paragraph, Fig. 4).
As per claims 23-26, the claims are directed to an adder that implements the same or similar features as the adder of claims 3-6, respectively, and are therefore rejected for at least the same reasons therein.
Claims 2, 7, 22, 27 are rejected under 35 U.S.C. 103 as being unpatentable over Kamboh/Lehman in further view of Wikipedia (Carry-Skip adder, hereinafter “Wikipedia”).
As per claim 2, Kamboh/Lehman further teaches The adder implemented in the FPGA of claim 1.
Kamboh does not explicitly disclose the coupling of propagate and generate signals for the carry skip adder blocks. Thus, Kamboh does not teach wherein: each of the plurality of carry skip adder blocks coupled to receive as inputs routed propagate carry and generate carry signals from full adder logic blocks in a skip adder structure.
Wikipedia teaches wherein: each of the plurality of carry skip adder blocks coupled to receive as inputs routed propagate carry and generate carry signals from full adder logic blocks in a skip adder structure (Wikipedia: Block-carry-skip adders section Figure).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the carry-skip adder blocks of Kamboh with the carry skip adder block of Wikipedia. One would have been motivated to combine these references because both references disclose carry-skip adder designs, and combining prior art elements according to known methods to yield predictable results (routing the propagate and generate signals of carry skip blocks).
As per claim 7, Kamboh/Lehman teaches The adder implemented in the FPGA of claim 1, wherein the adder has two or more features from a feature set consisting of: a second feature comprising variable carry skip block sizes to hide routing delay associated with generating group propagate and generate signals (Lehman: pg. 694 right col first paragraph); and a fourth feature comprising a ripple carry structure to generate a wide AND for the function of fast block propagate generation (Lehman: Fig. 1).
Kamboh does not teach a first feature comprising an adder structure that uses routed propagate and generate signals from adder logic to create carry skip adder structures;
Wikipedia teaches a first feature comprising an adder structure that uses routed propagate and generate signals from adder logic to create carry skip adder structures (Wikipedia: Block-carry-skip adders section Figure);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the carry-skip adder blocks of Kamboh with the carry skip adder block of Wikipedia for at least the same reasons as claim 2.
As per claims 22, 27, the claims are directed to an adder that implements the same or similar features as the adder of claims 2, 7, respectively, and are therefore rejected for at least the same reasons therein.
Claims 28, 30-33 are rejected under 35 U.S.C. 103 as being unpatentable over Kamboh/Lehman in further view of Rose et al. (US 5724276 A, hereinafter “Rose”).
As per claim 28, the claim is directed to an adder that implements the same or similar features as the adder of claim 1, and is therefore rejected for at least the same reasons therein.
However, while Kamboh discloses adder designs on FPGAs (Kamboh: abstract), Kamboh does not explicitly state the FPGA comprises lookup tables to perform the functions of the adder. Thus, Kamboh does not teach wherein lookup tables (LUT) as blocks in the FPGA are decomposed to implement propagate carry, generate carry and sum functions in the adder.
Rose teaches wherein lookup tables (LUT) as blocks in the FPGA are decomposed to implement propagate carry, generate carry and sum functions in the adder (Figs. 1b, 2b; col 1 lines 41-56; wherein the carry logic and sum logic include LUTs).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the FPGA configurable logic blocks of Kamboh with the FPGA logic block teachings of Rose. One would have been motivated to combine these references because both references disclose FPGA logic blocs performing addition, and combining prior art elements according to known methods to yield predictable results (performing addition on FPGAs).
As per claims 30-33, the claims are directed to an adder that implements the same or similar features as the adder of claims 3-6, respectively, and are therefore rejected for at least the same reasons therein.
Claims 29, 34 are rejected under 35 U.S.C. 103 as being unpatentable over Kamboh/Lehman/Rose in further view of Wikipedia.
As per claims 29, 34, the claims are directed to an adder that implements the same or similar features as the adder of claims 2, 7, respectively, and are therefore rejected for at least the same reasons therein.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHAT N LE whose telephone number is (571)272-0546. The examiner can normally be reached Monday-Friday 8:30AM-5PM ET.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182