Prosecution Insights
Prosecution Insights
Technology area: Computing & Software
4 pending office actions • 3 art units • 4 examiners • 0 of 4 (0%) have an AI response strategy ready • 4 patents granted in the last 365 days
Efinix Inc. has 4 pending office actions in the Computing & Software technology area. These actions are assigned to 4 distinct examiners and are distributed across 3 distinct art units. The involvement of 3 distinct art units suggests that the company's computing and software innovations are being evaluated by several different technical groups.
SPANN, COURTNEY P is the busiest examiner for the portfolio, currently handling 1 pending office action. Since there are 4 pending office actions and multiple distinct examiners, each examiner is responsible for a single case. This means that the 1 pending action under SPANN, COURTNEY P represents a portion of the company's active prosecution workload. The spread across 4 distinct examiners indicates a decentralized approach to managing the company's computing patent applications, ensuring varied technical oversight.
Based on the USPTO statutory response window for each pending office action. 1 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 + other | 1 (25%) |
| §103 only | 1 (25%) |
| Multi-statute (no §101) | 2 (50%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| SPANN, COURTNEY P | 1 | 80.0% | +22.1% |
| DOMAN, SHAWN | 1 | 64.9% | +26.6% |
| KIM, HARRISON CHAN YOUNG | 1 | 56.3% | +37.5% |
| STOICA, ADRIAN | 1 | 67.4% | +31.9% |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18612718 | SYSTEM AND METHOD FOR QUEUEING IN PROCESSORS CUSTOM INSTRUCTION EXTENSION | SPANN, COURTNEY P | — |
| 18169007 | NEURAL NETWORK ACCELERATOR ARCHITECTURE BASED ON CUSTOM INSTRUCTION ON FPGA | DOMAN, SHAWN | — |
| 17546858 | DYNAMIC FPGA LOGIC CAPACITY BASED ON ACCURATE EARLY ROUTABILITY ESTIMATION | STOICA, ADRIAN | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 4 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18062055 | METHOD OF USING FPGA FOR AI INFERENCE SOFTWARE STACK ACCELERATION | KIM, HARRISON CHAN YOUNG | 34d |
| 18612718 | SYSTEM AND METHOD FOR QUEUEING IN PROCESSORS CUSTOM INSTRUCTION EXTENSION | SPANN, COURTNEY P | — |
| 18169007 | NEURAL NETWORK ACCELERATOR ARCHITECTURE BASED ON CUSTOM INSTRUCTION ON FPGA | DOMAN, SHAWN | — |
| 17546858 | DYNAMIC FPGA LOGIC CAPACITY BASED ON ACCURATE EARLY ROUTABILITY ESTIMATION | STOICA, ADRIAN | — |
| Art Unit | Apps |
|---|---|
| 2183 | 2 |
| 2145 | 1 |
| 2186 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18612718 | SYSTEM AND METHOD FOR QUEUEING IN PROCESSORS CUSTOM INSTRUCTION EXTENSION | SPANN, COURTNEY P | 2183 | §103§112 | Non-Final OA | — | Pending | Mar 21, 2024 |
| 18169007 | NEURAL NETWORK ACCELERATOR ARCHITECTURE BASED ON CUSTOM INSTRUCTION ON FPGA | DOMAN, SHAWN | 2183 | §103§112 | Final Rejection | — | Pending | Feb 14, 2023 |
| 18062055 | METHOD OF USING FPGA FOR AI INFERENCE SOFTWARE STACK ACCELERATION | KIM, HARRISON CHAN YOUNG | 2145 | §103 | Final Rejection | 34d | Pending | Dec 06, 2022 |
| 17546858 | DYNAMIC FPGA LOGIC CAPACITY BASED ON ACCURATE EARLY ROUTABILITY ESTIMATION | STOICA, ADRIAN | 2186 | §101§103 | Final Rejection | — | Pending | Dec 09, 2021 |
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