Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s reply filed on 1/26/2026 have been received and entered. Claims 1-26 are currently pending.
Response to Arguments
Applicant’s arguments, see pages 7-9, filed 1/29/26, with respect to the rejection of claims 1-5, 7-8, 10-12 and 19-25 under nonstatutory Double Patenting have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration based on the newly submitted IDS filed on 5/7/26, a new ground(s) of rejection is made in view of Lepinay and Zhang.
References Cited in Prior Art Rejections
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Stone et al. USP 10,026,590
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-12 and 15-17 and 19-25 are rejected under 35 U.S.C. 103 as being unpatentable over Lepinay in view of Zhang.
With respect to claim 1, Lepinay teaches a method, comprising:
obtaining an image of a first surface layer of an integrated semiconductor sample using an imaging device, the integrated semiconductor sample comprising integrated circuits (fig. 4);
removing the first surface layer of the integrated semiconductor sample using a focused ion beam to expose a second surface layer of the integrated semiconductor sample, the second surface layer of the integrated semiconductor sample being parallel to the first surface layer of the integrated semiconductor sample (FIM/SEM tomography generating a multiple slices detailed in section titled Principle and Acquisition Process); and
obtaining an image of the second surface layer of the integrated semiconductor sample with the imaging device (FIM/SEM tomography detailed in section titled Principle and Acquisition Process).
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Lepinay, however, does not explicitly teach the step of registering the images of the first and second surface layers of the integrated semiconductor sample based on a feature of the integrated circuits of the integrated semiconductor sample present in both the first and second surface images.
Zhang, the same field of endeavor as aligning of semiconductor cross section images (‘Volumn Reconstruction’ of Lepinay & ‘Image Stitching and Analysis’ of Zhang), discloses a step of obtaining/registering images of the first and second surface layers of the integrated semiconductor sample based on a feature of the integrated circuits of the integrated semiconductor sample present in both the first and second surface images (see section titled ‘Image Stitching and Analysis’). Specifically, Zhang states “we extract features points from the overlap regions and finding corresponding features in the common image regions” which implies that alignment based on features of images can be used in registration of semiconductor cross section images.
It would have been obvious to a person of ordinary skill in the art, before the effective filing date, to modify the system of Lepinay to incorporate the registering the common feature areas present in the first and second images as taught by Zhang.
The suggestion/motivation for doing so would have been to better achieve the reconstruction/image stitching of images.
With respect to claim 2, the combination of Lepinay and Zhang teaches the method of claim 1, wherein the feature comprises at least one member selected from the group consisting of a metal line, a via, a HAR structure, a HAR channel, and a gate structure (page 91 of Lepinay).
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With respect to claim 3, the combination teaches the method of claim 1, comprising performing the image registration based on at least two features of the integrated circuits of the integrated semiconductor sample (abstract, Section III and fig. 3 of Zhang shows the result of extracting a plurality of features per tile in the overlapped region).
With respect to claim 4, the combination of Lepinay and Zhang teaches the method of claim 1, wherein the image registration comprises a statistical evaluation (‘Volume Reconstruction’ of Lepinay and Section III of Zhang).
With respect to claim 5, the combination of Lepinay and Zhang teaches the method of claim 4, wherein the statistical evaluation comprises at least one member selected from the group consisting of a computation of a centroid, a feature detection, and a statistical averaging (“all images in the stack are aligned with respect to a single arbitrarily chosen image with in the stack… based on gray levels and cross-correlation between images” in ‘Volume Reconstruction’ of Lepinay and Section III of Zhang).
With respect to claim 6, the combination of Lepinay and Zhang teaches the method of claim 1, further comprising, before registering the images, measuring and evaluating the position of alignment marks to provide a fiducial based alignment of the first and second surfaces of the integrated semiconductor sample (‘Volume Reconstruction’, ‘alignment strategy’ and fig. 8 of Lepinay).
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With respect to claim 7, the combination of Lepinay and Zhang teaches the method of claim 1, wherein the imaging device comprises a member selected from the group consisting of a charged particle device, an atomic force microscope, and an optical microscope (FIB/SEM tomograph of Lepinay).
With respect to claim 8, the combination of Lepinay and Zhang teaches the method of claim 1,
wherein the imaging device provides an electron beam that is used to image the first and second surfaces of the integrated semiconductor sample, the focused ion beam and the electron beam are at an angle to each other, and a beam axis of the focused ion beam and a beam axis the electron beam intersect each other(FIB/SEM tomograph and fig. 4 of Lepinay shows that FIB and SEM are incident at different angles and intersected).
With respect to claim 9, the combination of Lepinay and Zhang teaches the method of claim 1,
wherein the first and second images are perpendicular to a top surface of the integrated semiconductor sample (“FIB cross sections are performed perpendicular to the deposited process stacks” in the section titled ‘Acquistion Processs’ and fig. 4 of Lipnay).
With respect to claim 10, the combination of Lepinay and Zhang teaches the method of claim 1,
wherein the first and second images are perpendicular to metal lines or gates of a metal layer of the integrated semiconductor sample (“FIB cross sections are performed perpendicular to the deposited process stacks” in the section titled ‘Acquistion Processs’ and fig. 4 of Lipnay).
With respect to claim 11, the combination of Lepinay and Zhang teaches the method of claim 1, wherein the first and second images are inclined at an angle deviating from 90° to the metal lines or gates of the metal layer of the integrated semiconductor sample (oblique angel as shown in fig. 4 of Lepinay) .
With respect to claim 12, the combination of Lepinay and Zhang teaches the method of claim 1, wherein the first and second images are inclined to a top surface of the integrated semiconductor sample to reveal images of at least one HAR channel perpendicular to the top surface of the integrated semiconductor sample (section titled ‘slice step evaluation’ and fig. 4 of Lepinay).
With respect to claim 15, the combination of Lepinay and Zhang teaches the method of claim 1, comprising subtracting an image distortion deviation between the first and second images during image registration (image improvement is performed during the acquisition process to control the noise in the images according to Lepinay in ‘Acquistion process’ and Section III of Zhang).
With respect to claim 16, the combination of Lepinay and Zhang teaches the method of claim 15, comprising approximating the image distortion deviation by a basis distortion during image distortion subtraction (image improvement is performed during the acquisition process to control the noise in the images according to Lepinay in ‘Acquistion process’ and Section III of Zhang).
With respect to claim 17, the combination of Lepinay and Zhang teaches the method of claim 1, further comprising:
determining a curtaining signature of the second cross section; and using the curtaining signature to represent the first and second images as 3D cross section images (various “curtain” or wavy features are used for alignment/reconstruction as shown in figs 5, 6 and 7 of Lepinay).
With respect to claim 19, the combination of Lepinay and Zhang teaches the method of claim 1, further comprising aligning the first and second images based on i) a predetermined footprint shape of features of the integrated circuits of the integrated semiconductor sample present in both the first and second images, and/or ii) a predetermined spatial distribution of the features of the integrated circuits of the integrated semiconductor sample present in both the first and second images (‘Volume Reconstruction’, ‘alignment strategy’ and fig. 8 of Lepinay & Section III, figs. 2 & 3 of Zhang).
With respect to claim 20, the combination of Lepinay and Zhang teaches the method of claim 19, comprising aligning the first and second images in a direction that is i) perpendicular to the first and second surface layers of the integrated semiconductor sample, and/or ii) within the planes of the first and second surface layers of the integrated semiconductor sample (‘Volume Reconstruction’, ‘alignment strategy’ and fig. 8 of Lepinay & Section III, figs. 2 & 3 of Zhang).
With respect to claim 21, the combination of Lepinay and Zhang teaches the method of claim 20, wherein a footprint shape of the features is circular or elliptical (fig. 12 of Lepinay shows shape of the features as circular or elliptical and feature points represented in figs. 5 & 6 of Zhang).
With respect to claim 22, the combination of Lepinay and Zhang teaches the method of claim 1, further comprising, after registering the first and second images, combining the first and section images to a 3D volume image (‘Volume Reconstruction’, ‘alignment strategy’ and fig. 8 of Lepinay & Section III, figs. 2 & 3 of Zhang).
With respect to claim 23, the combination of Lepinay and Zhang teaches one or more machine-readable hardware storage devices comprising instructions that are executable by one or more processing devices to perform operations comprising the method of claim 1 (conclusion section of Zhang disclosing computing system).
With respect to claim 24, the combination of Lepinay and Zhang teaches a system, comprising: one or more processing devices; and one or more machine-readable hardware storage devices comprising instructions that are executable by the one or more processing devices to perform operations comprising the method of claim 1 (conclusion section of Zhang disclosing computing system).
With respect to claim 25, the combination of Lepinay and Zhang teaches the system of claim 24, further comprising: a focused ion beam device configured to provide a focused ion beam; and an electron beam device configured to provide an electron beam, wherein the focused ion beam and the electron beam are at an angle to each other, and a beam axis of the focused ion beam intersects a beam axis of the electron beam (fig. 4 of Lepinay shows that FIB and SEM are incident at different angles and intersected).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lepinay and Zhang as applied to claim 1 above, and further in view of Stone et al. USP 10,026,590 (hereinafter Stone).
With respect to claims 13 and 14, the combination of Lepinay and Zhang teaches the system of claim 1 but it does not explicitly teach the method of determining a distance between the first and the second images.
Stone, the same field of endeavor as the defect analysis using FIB system, teaches the method of calculating different points in the analysis images using fiducials/features that are perpendicular to the top surface of the semiconductor samples (col. 9 line 30 ~ col. 10 line 19).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date, to modify the system of Lepinay to include the distance measuring method as taught by Stone.
The suggestion/motivation for doing so would have been to accurately measure characteristics of the wafer for inspection.
Allowable Subject Matter
Claim 26 is allowed.
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAN S PARK whose telephone number is (571)272-7409. The examiner can normally be reached Monday-Friday 8:30am-5:00pm.
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/CHAN S PARK/Supervisory Patent Examiner, Art Unit 2669
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