DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Applicant’s amendments filed 12/17/2025 have been accepted. Claims 1-20 remain pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9-14, and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20200357898 A1) hereinafter “Lee.”
Regarding Claim 1, Figures 12A-C of Lee teach: A semiconductor structure (1280/1290), comprising: a source/drain region (730/830) having a top surface comprising a plurality of recessed portions (R1, R2, R3 and R4; See annotated Figures 12A-12B below) wherein a first recessed portion (R1; See annotated Figure 12A below) of the plurality of recessed portions comprises a cross-sectional profile (Figure 12A) having substantially a same shape (Figure 12A) as a second recessed portion (R2; See annotated Figure 12A below) of the plurality of recessed portions; and a metal contact (1250; Paragraph 0138) disposed on and surrounding the source/drain region, wherein the metal contact comprising a metal fill portion (Paragraphs 0141-0142) that directly abuts the top surface of the source/drain region including
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the plurality of recessed portions of the source/drain region.
Annotated Figures 12A and 12B of Lee
Regarding Claim 2, Figures 12A-C of Lee teach: each of the at least one plurality of recessed portions (R1, R2, R3 and R4; See annotated Figures 12A-B above) is part of a portion of the top surface (top vertically of item 730) of the source/drain region (730/830) comprising a convex surface and a concave surface (Figure 12A).
Regarding Claim 3, Figures 12A-C of Lee teach: the plurality of recessed portions (R1, R2, R3, and R4; See annotated Figures 12A-B above) comprises one or more additional recessed portions (R3 and R4; See annotated Figures 12A-B above) comprising cross-sectional profiles (Figure 12B) having substantially the same shape as the first (R1; See annotated Figures 12A-B above) and second (R2; See annotated Figures 12A-B above) recessed portion such that the top surface of the source/drain region (730/830) comprises a periodic convex and concave shaped structure (Figures 12A-B).
Regarding Claim 4, Figures 12A-C of Lee teach: a substrate (120) comprising a semiconductor material (Paragraph 0055), wherein the source/drain region (730) is disposed on the substrate.
Regarding Claim 9, Figures 12A-C of Lee teach: a substrate (120) comprising a semiconductor material (Paragraph 0055); a set of fins (135) formed from the semiconductor material and extending vertically with respect to the substrate; gate structures (1055G) disposed on the substrate and on a portion of sidewalls (left/right horizontally) of the set of fins; spacers (125) disposed on the gate structures and on a remaining portion of the sidewalls of the set of fins; and the source/drain region (730) disposed over at least a top portion of each of the set of fins (Figure 12A).
Regarding Claim 10, Figures 12A-C of Lee teach: a portion of the source/drain region (730) disposed over a top portion of each of a set of fins comprises a diamond shaped configuration (Figure 12A).
Regarding Claim 11, Figures 12A-C of Lee teach: An integrated circuit (Paragraph 0148), comprising: a plurality of semiconductor structures (1280/1290), wherein at least one of the plurality of semiconductor structures comprises: a source/drain region (730/830) having a top surface (top vertically) comprising a plurality of recessed portions (R1, R2, R3, and R4; See annotated Figures 12A-12B of Lee below), wherein a first recessed portion (R1; See annotated Figures 12A-12B of Lee below) of the plurality of recessed portions comprises a cross-sectional profile having substantially a same shape as a second recessed portion (R2; See annotated Figures 12A-12B of Lee below) of the plurality of recessed portions; and a metal contact (1250) disposed on and surrounding the source/drain region, wherein the metal contact comprising a metal fill portion (Paragraphs 0141-0142) that directly abuts the top surface of the source/drain region including the plurality of recessed portions of the source/drain region (Figure 12A).
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Annotated Figures 12A-12B of Lee
Regarding Claim 12, Figures 12A-C of Lee teach: each of the plurality of recessed portions (R1, R2, R3, and R4; See annotated Figures 12A-12B above) is part of a portion of the top surface of the source/drain region (730/830) comprising a convex surface and a concave surface (Figures 12A-12B).
Regarding Claim 13, Figures 12A-C of Lee teach: the plurality of recessed portions (R1, R2, R3, and R4; See annotated Figures 12A-12B above) comprises one or more additional recessed portions (R3 and R4; See annotated Figures 12A-12B) comprising cross-sectional profiles having substantially the same shape as the first (R1; See annotated Figures 12A-12B of Lee above) and second recessed portions (R1; See annotated Figures 12A-12B of Lee above) such that the top surface of the source/drain region comprises a periodic convex and concave shaped structure (Figures 12A-12B).
Regarding Claim 14, Figures 12A-C of Lee teach: a substrate (120) comprising a semiconductor material (Paragraph 0055), wherein the source/drain region (730/830) is disposed on the substrate.
Regarding Claim 17, Figures 12A-C of Lee teach: a substrate (120) comprising a semiconductor material (Paragraph 0055); a set of fins (135 and 145) formed from the semiconductor material and extending vertically with respect to the substrate; gate structures (1055G and 1056G) disposed on the substrate and on a portion of sidewalls of the set of fins (Figures 12A-12B); spacers (125) disposed on the gate structures and on a remaining portion of the sidewalls of the set of fins; and the source/drain region (730/830) disposed over a top portion of each of the set of fins.
Regarding Claim 18, Figures 12A-C of Lee teach: a portion of the source/drain region (730/830) disposed over a top portion of each of a set of fins (135/145) comprises a diamond shaped configuration (Figures 12A-12B).
Regarding Claim 19, Figures 12A-C of Lee teach: A method for fabricating a semiconductor substrate (1280/1290), comprising: forming a source/drain region (730/830) having a top surface comprising a plurality of recessed portions (R1, R2, R3 and R4; See annotated Figures 12A-12B below), wherein a first recessed portion (R1; See annotated Figure 12A below) of the plurality of recessed portions comprises a cross-sectional profile (Figure 12A) having substantially a same shape as a second recessed portion (R2; See annotated Figure 12A below) of the plurality of recessed portions; and forming a metal contact (1250; Paragraph 0138) on and surrounding the source/drain region, wherein the metal contact comprising a metal fill portion (Paragraphs 0141-1042) that directly abuts the top surface of the source/drain region including the plurality of recessed portions of the source/drain region.
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Annotated Figures 12A and 12B of Lee
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-8 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20200357898 A1) hereinafter “Lee” in view of Zhang et al. (US 20200373300 A1) hereinafter “Zhang.”
Regarding Claim 5, Lee teaches all of the limitations of the claimed invention as stated above.
Figures 12A-C of Lee teach: a first channel region (135) disposed on the substrate (120), and a second channel region (145) disposed on the substrate
Lee does not teach: the first channel region comprising a first set of nanosheet layers; and the second channel region comprising a second set of nanosheet layers.
Figure 13A of Zhang teaches: a semiconductor structure (100) comprising a channel region (110) comprising a set of nanosheet layers (Paragraph 0040).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first channel region comprising a first set of nanosheet layers and the second channel region comprising a second set of nanosheet layers because Zhang teaches gate-all-around devices that utilize nanosheet channels provide area efficiency (Zhang Paragraph 0004).
Regarding Claim 6, the combination of Lee and Zhang teaches all of the limitations of the claimed invention as stated above.
Lee does not teach: the first set of nanosheet layers and the second set of nanosheet layers each comprises silicon.
Figure 13A of Zhang teaches: a semiconductor structure (100) comprising a channel region (110) that comprises a set of nanosheet layers (Paragraph 0040); wherein the nanosheet layers comprise silicon (Paragraph 0040).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first set of nanosheet layers and the second set of nanosheet layers each comprises silicon because Zhang teaches nanosheets that comprise silicon are known in the art to act as channel layers (Paragraph 0040) in gate-all-around devices that provide area efficiency (Zhang Paragraph 0004).
Regarding Claim 7, Figures 12A-C of Lee teach: the first channel region (135) is one of a p-type field-effect transistor region (1280) and the second channel region (145) is one of an n-type field-effect transistor region (1290).
Regarding Claim 8, Figures 12A-C of Lee teach: each of the first channel region (135) and the second channel region (145) further comprises a gate structure (1055G/1056G)
Regarding Claim 15, Lee teaches all of the limitations of the claimed invention as stated above.
Figures 12A-C of Lee teach: a first channel region (135) disposed on the substrate (120), and a second channel region (145) disposed on the substrate
the first channel region comprising a first set of nanosheet layers; and the second channel region comprising a second set of nanosheet layers.
Figure 13A of Zhang teaches: a semiconductor structure (100) comprising a channel region (110) comprising a set of nanosheet layers (Paragraph 0040).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first channel region comprising a first set of nanosheet layers and the second channel region comprising a second set of nanosheet layers because Zhang teaches gate-all-around devices that utilize nanosheet channels provide area efficiency (Zhang Paragraph 0004).
Regarding Claim 16, Figures 12A-C of Lee teach: the first channel region (135) is one of a p-type field-effect transistor region (1280) and the second channel region (145) is one of an n-type field-effect transistor region (1290).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20200357898 A1) hereinafter “Lee” in view of Liu et al. (US 20190371925 A1) hereinafter “Liu.”
Regarding Claim 20, Lee teaches all of the limitations of the claimed invention as stated above.
Lee does not teach: forming the source/drain region having the top surface comprising the plurality of recessed portions comprises a directed self-assembly patterning process.
Figures 1-7 of Liu teach: performing a directed self-assembly patterning process over a source and drain region (Paragraph 0036)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the forming of the source/drain region having the top surface comprising the at least one recessed portion comprises a directed self-assembly patterning process because Liu teaches using a directed self-assembly to increase source and drain contact edge width (Liu Paragraph 0001).
Response to Arguments
Applicant’s arguments, see Applicant’s Remarks, filed 12/17/2025, with respect to the rejections of Claims 1, 11, and 19 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lee.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Halee Cramer whose telephone number is (571)270-1641. The examiner can normally be reached Monday - Friday 7:30am - 4:30pm.
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/HALEE CRAMER/Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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