DETAILED ACTION
Claims 1-29 are pending. Applicant has amended claims 1, 3-4, 8-11, 17, 20, 23, and 29.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 9. 11, 14, 16, 17, 21-23 and 26-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LUO et al. (CN 111078412 A).
As to claim 1, LUO teaches a non-transitory machine-readable medium having stored thereon instructions, which if performed, at least in part, by one or more processors, cause the one the or more processors to at least, in response to an application programming interface (API) call (Preferably, the API interception refers to the executable file … intercepting library Detours as API interception technology by open source API; page 5, 1st paragraph, and “In the CUDA application … invoke a group cudaMalloc * function to indicate the CUDA runtime library for memory allocation … controlling the flow into the cudaHookMalloc - * function; page 7, 3rd paragraph): set a limit on a maximum amount of memory (“capacity for memory allocation requested by the user”; page 7, 4th paragraph and “according to the preset distribution rule and memory allocation limit … and memory allocation quota still has remaining … the success information returned by the function”; page 7, 8th paragraph – page 2, 2nd paragraph) usable by one or more processor of a graphics processing unit (GPU) to perform one or more threads (As shown in Fig. 1, the current GPU hardware architecture mainly includes a global memory and stream processor, shared memory, registers, ALU and other structures; page 6, last 2 paragraphs and thread; page 9, 2nd paragraph), wherein the limit is indicated as a parameter of the API call (the cudaMalloc * function according to preset distribution rule and memory allocation limit, the memory allocation request of the client code for judging whether accords with memory allocation rule; page 8, 2nd paragraph).
As to claim 2, LUO teaches wherein the parameter is a data value comprising a numerical limit on memory (“capacity for memory allocation requested by the user”; page 7, 4th paragraph, and the “cudaMalloc * function”; page 8, 2nd paragraph and page 3, 7th paragraph).
As to claim 3, LUO teaches wherein one or more processes are to indicate the parameter to the API call to cause one or more thread groups to be executed by the one or more processors (page 9, 1st – 4th paragraphs and claim 4).
As to claim 5, LUO teaches wherein the maximum amount of memory is to be limited for one or more thread groups to be executed by the one or more processors (“capacity for memory allocation requested by the user”; page 7, 4th paragraph).
As to claim 6, LUO teaches wherein the maximum amount of memory is a quantity of memory usable by one or more thread groups to be executed by the one or more processors (“capacity for memory allocation requested by the user”; page 7, 4th paragraph).
As to claim 7, LUO teaches wherein each of one or more thread groups to be executed by the one or more processors are to access the maximum amount of memory based, at least in part, on the parameter (page 8, 2nd paragraph and “capacity for memory allocation requested by the user”; page 7, 4th paragraph).
As to claim 9, it is the same as the medium claim 1 except this is a method claim, and therefore is rejected under the same ground of rejection.
As to claim 11, see rejection of claim 2 above.
As to claim 14, LUO teaches performing, by the one or more processors, one or more thread groups, where the one or more thread groups comprise a first subset to access the maximum amount of memory (page 8, 2nd paragraph and “capacity for memory allocation requested by the user”; page 7, 4th paragraph).
As to claim 16, LUO teaches wherein the one or more processors are graphics processing units (GPUs) (GPU; abstract).
As to claim 17, it is the same as the medium claim 1 except this is a one or more processors claim, and therefore is rejected under the same ground of rejection.
As to claim 21, see rejection of claim 2 above.
As to claim 22, see rejection of claim 5 above.
As to claim 23, it is the same as the medium claim 1 above except this is a system claim and therefore is rejected under the same ground of rejection.
As to claim 26, LUO teaches wherein the parameter is to indicate a numerical limit on memory usable by one or more thread groups to be executed by the one or more processors (“capacity for memory allocation requested by the user”; page 7, 4th paragraph).
As to claim 27, see rejection of claim 7 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 10, 12, 13, 19, 20, 24, 25 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over LUO et al. (CN 111078412 A) in view of Munshi et al. (US 2017/0075730 A1).
As to claim 4, LUO does not clearly teach wherein the parameter is to be indicated to the API call by one or more commands of a parallel processing library.
However, Munshi teaches the parameter is to be indicated to the API call by one or more commands of a parallel processing library (see abstract, “an application may select and specify capability requirements for performing a processing task”; paragraph [0030], and “Performing a processing task may include executing multiple threads … concurrently; paragraph [0031], and thread group; paragraph [0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of Munshi to the system of LUO because both are directed to the same field of endeavor, and Munshi teaches a method for a parallel computing program calling APIs in a host processor to perform a data processing task in parallel among compute units, thus enable to the system of LUO able to perform tasks parallel, would improve the performance of the system.
As to claim 10, see rejection of claim 4 above.
As to claim 12, LUO as modified by Munshi teaches indicating the parameter to a parallel processing library, the parallel processing library causing memory of the one or more processors to be limited (see Munshi: paragraphs [0042]-[0043]).
As to claim 13, LUO as modified by Munshi teaches indicating the one or more memory range parameters to a parallel processing library by causing one or more commands provided by the parallel processing library to be executed and specifying to the one or more commands the one or more memory range parameters (see Munshi: paragraphs [0042]-[0043] and [0045]).
As to claim 19, LUO as modified by Munshi teaches a parallel processing library to provide one or more commands that, when performed by the processor, cause the parallel processing library to limit the range of memory based, at least in part, on the one or more memory range parameters, where the one or more memory range parameters are to be indicated to the parallel processing library using the one or more commands (see Munshi: paragraphs [0042]-[0043] and [0045]).
As to claim 20, see rejection of claim 4 above.
As to claim 24, see rejection of claim 4 above.
As to claim 25, LUO as modified by Munshi teaches wherein the parameter is to indicate a numerical value, where the numerical value is usable to by a parallel processing library to limit the range of memory (see LUO: “capacity for memory allocation requested by the user”; page 7, 4th paragraph) and (see Munshi: paragraph [0057], [0078]-[0079]).
As to claim 29, LUO as modified by Munshi teaches wherein the one or more processors are one or more streaming multiprocessors (SMs) of one or more graphics processing units (GPUs) (see Munshi: GPU and “Performing a processing task may include executing multiple threads … concurrently; paragraph [0031]).
Claims 8, 15, 18 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over LUO et al. (CN 111078412 A) in view of NARENDRA TRIVEDI et al. (US 2018/0336342 A1).
As to claim 8, LUO does not teach wherein one or more thread groups are to be executed by the one or more processors, where a first subset of the one or more thread groups is able to access the limited maximum amount of memory and a second subset of the one or more thread groups is able to access a full range of memory, the first subset indicated to the API by one or more identifier.
However, NARENDRA TRIVEDI teaches wherein one or more thread groups are to be executed by the one or more processors, where a first subset of the one or more thread groups is able to access the limited range of memory (TEE-RANGE; paragraph [0057] and [0051]) and a second subset of the one or more thread groups is able to access a full range of memory, the first subset indicated to the API by one or more identifier (trusted and untrusted applications; paragraph [0034]-[0035] and threads execute on processor cores; paragraph [0028]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of NARENDRA TRIVEDI to the system of LUO because NARENDRA TRIVEDI teaches a method that enable the system of LUO to allocate different amount of memory to the threads/process as required.
As to claim 15, LUO as modified by NARENDRA TRIVEDI teaches indicating one or more identifiers to a parallel processing library, where the one or more identifiers are usable to identify one or more thread groups to be limited according to the parameter (see NARENDRA TRIVEDI: a trusted execution environment identifier; paragraph [0078]).
As to claim 18, LUO as modified by NARENDRA TRIVEDI teaches wherein the one or more circuits are to cause a parallel processing library to limit the range of memory by causing one or more requests to the parallel processing library to access memory outside the range of memory to fail, the one or more requests performed by one or more thread groups executed by the one or more processors (see NARENDRA TRIVEDI: “The interface plugin may enforce access control policies to limit read and write access of a TEE to a particular memory range within an on-chip NVRAM”; paragraph [0079]. Thus, any requests that request access out of the particular memory range would fail).
As to claim 28, see rejection of claim 8 above.
Response to Arguments
Applicant's arguments filed 1/23/2026 have been fully considered but they are not persuasive.
In response to Applicant’s arguments regarding LUO does not teach the claimed limitation, especially the “a maximum amount of memory” because “memory allocation quota” is not “a maximum amount of memory usable by one or more processors of a GPU”, the term “a maximum amount of memory” has been clarified to show LUO still teaches the limitations of claim 1 and other independent claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DIEM K CAO/Primary Examiner, Art Unit 2196
DC
May 4, 2026
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