DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/20/2026 has been entered.
Response to Arguments
Applicant’s response has been fully considered.
Applicant’s amendments to claims 31-33 overcome the previously raised objections.
Applicant’s amendments and the accompanying arguments with respect to the prior art rejections of claims 1 and 14, and their dependent claims, regarding the third slit extending linearly in the third direction from the one end of the first slit to the one end of the second slit, where the one end of the first slit and the one end of the second slit are located on a same side of the respective positions where the first, second and third pillars extend through the first conductive layers in the second direction have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kikutani (US 2017/0263625).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, 8, 11-15, 21, 22, and 25-34 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US 2010/0109071) in view of Lee et al. (US 2019/0244969), Kikutani (US 2017/0263625), and Sonehara (US 2017/0018566).
In reference to claim 1, Tanaka et al. (US 2010/0109071), hereafter “Tanaka,” discloses a semiconductor memory device comprising:
a plurality of first conductive layers WL stacked above a substrate and spaced apart from each other in a first direction Z intersecting a surface of the substrate 11, each of the first conductive layers extending longitudinally in a second direction X intersecting the first direction, as viewed in the first direction, paragraph 38;
a second conductive layer USG extending in the second direction X above the first conductive layers;
a third conductive layer USG extending in the second direction X above the first conductive layers, the third conductive layer being arranged adjacently to the second conductive layer in a third direction Y intersecting both the first direction and the second direction, Figure 8B and paragraphs 39 and 41;
a plurality of first pillars SP extending through the first conductive layers and the second conductive layer in the first direction, intersections of the first pillars with at least one of the first conductive layers functioning as first memory cells and intersections of the first pillars with the second conductive layer functioning as first select transistors;
a plurality of second pillars SP extending through the first conductive layers and the third conductive layer in the first direction, intersections of the second pillars with at least one of the first conductive layers functioning as second memory cells and intersections of the second pillars with the third conductive layer functioning as second select transistors, paragraphs 52 and 57;
a first insulator 31 provided in a first slit 30, see Figure 1, extending in the first and second (X) directions along one side of the first conductive layers in the third direction, the first insulator continuously covering bottom and both side surfaces extending in the second direction of the first slit, Figures 1 and 10 and paragraphs 26, 27, and 73;
a second insulator 31 provided in a second slit extending 30 in the first and second (X) directions along the other side of the first conductive layers in the third direction, the second insulator continuously covering bottom and both side surfaces extending in the second direction of the second slit, Figures 1 and 10 and paragraphs 26, 27, and 73;
an insulating member, region between layers 15 and 16 unlabeled in Figure 5, provided between the second conductive layer USG and the third conductive layer USG,
the first slit is in direct contact with the first conductive layers, Figures 10A and 10B.
Tanaka does not disclose a plurality of third pillars extending through the first conductive layers and extending between the second conductive layer and the third conductive layer in the first direction;
a third insulator provided in a third slit extending in the first and third directions along one side of the first conductive layers in the second direction, one end of the third slit in the third direction being directly coupled to one end of the first slit in the second direction and the other end of the third slit in the third direction being directly coupled to one end of the second slit in the second direction, and the third insulator being in direct contact with ends, of the first conductive layers in the second direction; and
an insulating member provided between the second conductive layer and the third conductive layer,
a plurality of contact portions of the first conductive layers with the third insulator are aligned in the first direction,
the first conductive layers extend in the second direction continuously from respective positions where the first, second, and third pillars extend through the first conductive layers to the third slit, and the ends of the first conductive layer are in direct contact with the third insulator in the second direction,
the first conductive layers have substantially a same planar shape from the respective positions where the first, second, and third pillars extend through the first conductive layers to the third slit, as viewed in the first direction,
the third slit extends linearly in the third direction from the one end of the first slit to the one end of the second slit, or
the one end of the first slit and the one end of the second slit are located on a same side of the respective positions where the first, second, and third pillars extend through the first conductive layers in the second direction.
Lee et al. (US 2019/0244969) discloses a semiconductor memory device including teaching an insulating member 118 provided between the second conductive layer and the third conductive layer, paragraph 40,
a plurality of third pillars, DCS1 in Figures 3 and 6, extending through the first conductive layers 131 and extending between the second conductive layer and the third conductive layer in the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a plurality of third pillars to extend through the first conductive layers and extend between the second conductive layer and the third conductive layer in the first direction.
One would have been motivated to do so in order to provide structural support to the stacked structure, paragraph 46.
Kikutani (US 2017/0263625), hereafter “Kikutani,” discloses an analogous semiconductor memory device including teaching
a third insulator provided in a third slit, 15t2 in Figures 5A and 5B, extending in the first and third (Z) directions along one side of the first conductive layers in the second (X) direction, a first portion of the third slit in the third direction being directly coupled to one end of the first slit in the second (X) direction and a second portion of the third slit in the third direction being directly coupled to one end of the second slit in the second direction,
the first conductive layers extend in the second direction continuously from respective positions where the first, second, and third pillars extend through the first conductive layers to the third slit, and
the third slit extends linearly in the third direction from the one end of the first slit to the one end of the second slit,
the first conductive layers have substantially a same planar shape from the respective positions where the first, second, and third pillars extend through the first conductive layers to the third slit, as viewed in the first direction, Figure 5B and paragraphs 58 and 59 (“the electrode layers 40 are not formed into stairs in the end portion 15t2),
the one end of the first slit and the one end of the second slit are located on a same side of the respective positions where the first, second, and third pillars extend through the first conductive layers in the second direction, see annotated Figures 5A and 5B below.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a third insulator to be provided in a third slit extending in the first and third directions along one side of the first conductive layers in the second direction, a first portion of the third slit in the third direction being directly coupled to one end of the first slit in the second direction and a second portion of the third slit in the third direction being directly coupled to one end of the second slit in the second direction, and
the first conductive layers to extend in the second direction continuously from respective positions where the first, second, and third pillars extend through the first conductive layers to the third slit,
the third slit to extend linearly in the third direction from the one end of the first slit to the one end of the second slit,
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[AltContent: textbox (1st slit)][AltContent: arrow][AltContent: textbox (2nd slit)][AltContent: arrow][AltContent: textbox (3rd slit)][AltContent: arrow][AltContent: arrow]the first conductive layers to have substantially a same planar shape from the respective positions where the first, second, and third pillars extend through the first conductive layers to the third slit, as viewed in the first direction,
the one end of the first slit and the one end of the second slit are located on a same side of the respective positions where the first, second, and third pillars extend through the first conductive layers in the second direction.
One would have been motivated to do so in order to provide multiple, laterally separated memory cell arrays within the device, paragraphs 56 and 60.
Kikutani does not disclose the third insulator being in direct contact with ends of the first conductive layers in the second direction; or
a plurality of contact portions of the first conductive layers with the third insulator are aligned in the first direction, or
the ends of the first conductive layer are in direct contact with the third insulator in the second direction.
Sonehara (US 2017/0018566), hereafter “Sonehara,” discloses a semiconductor memory device including teaching the third insulator, 55 in ST1, being in direct contact with ends of the first conductive layers 42, 62 in the second direction, a plurality of contact portions of the first conductive layers 42, 62 with the third insulator, 55 in ST1, are aligned in the first direction (Z direction), and the ends of the first conductive layers 42, 62, are in direct contact with the third insulator 55 in ST1 in the second direction, Figures 1, 2, and 5.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the third insulator to be in direct contact with ends of the first conductive layers in the second direction, a plurality of contact portions of the first conductive layers with the third insulator to be aligned in the first direction, and the ends of the first conductive layers to be in direct contact with the third insulator in the second direction. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting the slit with a vertical sidewall as in Sonehara for the slit with an inclined sidewall of Tanaka .
In reference to claim 7, Tanaka does not disclose fourth through sixth conductive layers, pillars, or insulators.
Lee teaches a semiconductor memory device including teaching first and second memory cell array regions CAR in Figure 1, see also paragraphs 26 and 31. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the memory device of Tanaka to include a second memory cell array. One would have been motivated to do so in order to form a semiconductor memory device incorporating more storage for high capacity data processing, paragraph 3. The natural result of the combination results in a second structure such as that taught by Tanaka in view of Kikutani and Sonehara in reference to claim 1 where:
Tanaka discloses a plurality of fourth conductive layers WL stacked above a substrate and spaced apart from each other in a first direction Z, each of the fourth conductive layers extending in a second direction X, paragraph 38;
a fifth conductive layer USG extending in the second direction X above the fourth conductive layers;
a sixth conductive layer USG extending in the second direction X above the fourth conductive layers, the sixth conductive layer being arranged adjacently to the fifth conductive layer in a third direction Y intersecting both the first direction and the second direction, Figure 8B and paragraphs 39 and 41;
a plurality of fourth pillars SP extending through the fourth conductive layers and the fifth conductive layer in the first direction, intersections of the fourth pillars with at least one of the fourth conductive layers functioning as third memory cells and intersections of the fourth pillars with the fifth conductive layer functioning as third select transistors;
a plurality of fifth pillars SP extending through the fourth conductive layers and the sixth conductive layer in the first direction, intersections of the fifth pillars with at least one of the fourth conductive layers functioning as fourth memory cells and intersections of the fifth pillars with the sixth conductive layer functioning as fourth select transistors, paragraphs 52 and 57;
a fourth insulator 31 provided in a fourth slit 30, see Figure 1, extending in the first and second (X) directions along one side of the fourth conductive layers in the third direction, the fourth insulator continuously covering bottom and both side surfaces extending in the second direction of the fourth slit, Figures 1 and 10 and paragraphs 26, 27, and 73; and
a fifth insulator 31 provided in a fifth slit extending 30 in the first and second (X) directions along the other side of the fourth conductive layers in the third direction, the fifth insulator continuously covering bottom and both side surfaces extending in the second direction of the fifth slit, Figures 1 and 10 and paragraphs 26, 27, and 73.
Lee discloses a semiconductor memory device including teaching
a plurality of sixth pillars, DCS1 in Figures 3 and 6, extending through the fourth conductive layers 131 and extending between the fifth conductive layer and the sixth conductive layer in the first direction; Figures 11A and 11C.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a plurality of sixth pillars to extend through the fourth conductive layers and extend between the fifth conductive layer and the sixth conductive layer in the first direction;
One would have been motivated to do so in order to provide structural support to the stacked structure, paragraph 46.
Kikutani discloses a sixth insulator provided in a sixth slit, 15t2 in Figures 5A and 5B, extending in the first and third (Y) directions, a first portion of the sixth slit in the third direction being coupled to one end of the fourth slit in the second direction and a second portion of the sixth slit in the third direction being coupled to one end of the fifth slit in the second direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a sixth insulator provided in a sixth slit to be extending in the first and third directions, a first portion of the sixth slit in the third direction being coupled to one end of the fourth slit in the second direction and a second portion of the sixth slit in the third direction being coupled to one end of the fifth slit in the second direction. One would have been motivated to do so in order to provide multiple, laterally separated memory cell arrays within the device, paragraphs 56 and 60.
Sonehara discloses the sixth insulator, 55 in ST1, being in direct contact with ends of the fourth conductive layers 42, 62 in the second direction, Figures 1, 2, and 5. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the sixth insulator to be in direct contact with ends of the fourth conductive layers in the second direction. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting the slit with a vertical sidewall as in Sonehara for the slit with an inclined sidewall of Tanaka .
In reference to claim 8, the ends of the fourth conducive layers face the ends of the first conductive layers in the second direction with the third and sixth insulators interposed therebetween, naturally results from the combination of Tanaka in view of Kikutani and Lee wherein the ends of the blocks of the first and second memory cell array regions CAR in Figure 1 of Lee face each other in the second direction and the insulator slit 30 in Tanaka surround and separate the blocks, cell arrays, and peripheral circuitry.
In reference to claim 11, Lee discloses the first and second memory cells and the first and second select transistors belong to a first memory plane, CAR on left in Figure 1, and the third and fourth memory cells and the third and fourth select transistors belong to a second memory plane, CAR on right in Figure 1, different from the first memory plane.
In reference to claim 12, Tanaka does not disclose a seventh conductive layer extending in the second direction above the second conductive layer, the first pillars extending through the seventh conductive layer in the first direction, and an eighth conductive layer extending in the second direction above the third conductive layer and being arranged adjacently to the seventh conductive layer in the third direction, the second pillars extending through the eighth conductive layer in the first direction, wherein the third pillars extend between the seventh conductive layer and the eighth conductive layer in the first direction.
Lee teaches a seventh conductive layer 131, SSL2, extending in the second direction D1 above the second conductive layer 131 SSL1, the first pillars extending through the seventh conductive layer in the first direction, and an eighth conductive layer, 131 SSL2, extending in the second direction D1 above the third conductive layer 131, SSL1 and being arranged adjacently to the seventh conductive layer in the third direction D2, the second pillars extending through the eighth conductive layer in the first direction, paragraphs 35 and 84 and Figures 2 and 11A, wherein the third pillars DCS1 extend between the seventh conductive layer and the eighth conductive layer in the first direction, Figure 3.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a seventh conductive layer to be extending in the second direction above the second conductive layer, the first pillars extending through the seventh conductive layer in the first direction, and an eighth conductive layer to be extending in the second direction above the third conductive layer and being arranged adjacently to the seventh conductive layer in the third direction, the second pillars extending through the eighth conductive layer in the first direction, wherein the third pillars extend between the seventh conductive layer and the eighth conductive layer in the first direction.
To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007). In this case substituting a single layer string selection configuration for a double layer string selection configuration, paragraph 35 of Lee.
In reference to claim 13, Lee discloses the insulating member 118 is provided between the seventh conductive layer and the eighth conductive layer, Figures 3 and 11A (118 penetrating the top two layers 121).
In reference to claim 14, Tanaka discloses a semiconductor memory device comprising:
a substrate including a first block area of a first memory cell array,
a stacked structure of conductive layers provided above the substrate, and a separation member 31 provided in a slit 30 extending inside the stacked structure, the first block area being partitioned by the slit above the substrate, paragraph 26, wherein the stacked structure includes
a plurality of first conductive layers WL stacked separately in a first direction Z intersecting a surface of the substrate 11, and disposed correspondingly to the first block area, each of the first conductive layers extending longitudinally in a second direction X intersecting the first direction, as viewed in the first direction, paragraph 38;
a second conductive layer USG extending in the second direction X above the first conductive layers;
a third conductive layer USG extending in the second direction X above the first conductive layers, the third conductive layer being arranged adjacently to the second conductive layer in a third direction Y intersecting both the first direction and the second direction, Figure 8B and paragraphs 39 and 41;
a plurality of first pillars SP extending through the first conductive layers and the second conductive layer in the first direction, intersections of the first pillars with at least one of the first conductive layers functioning as first memory cells and intersections of the first pillars with the second conductive layer functioning as first select transistors;
a plurality of second pillars SP extending through the first conductive layers and the third conductive layer in the first direction, intersections of the second pillars with at least one of the first conductive layers functioning as second memory cells and intersections of the second pillars with the third conductive layer functioning as second select transistors, paragraphs 52 and 57;
an insulating member, region between layers 15 and 16 unlabeled in Figure 5, provided between the second conductive layer USG and the third conductive layer USG,
the slit 30 includes first and second parts both extending in the first and second (X) directions, the first block area above the substrate being sandwiched by the first and second parts of the slit in the third direction, Figures 1 and 10 and paragraphs 26, 27, and 73,
the first part of the slit is positioned along one side of the first conductive layers in the third direction, the second part of the slit is positioned along the other side of the first conductive layers in the third direction, Figure 1,
and includes an insulator covering an inner surface of the slit continuously in the first to second parts of the slit, paragraph 73 and Figures 10A and 10B.
Tanaka does not disclose a plurality of memory cell arrays including a first memory cell array and a second memory cell array, the first memory cell array being separated from the second memory cell array by a boundary region therebetween,
a plurality of third pillars extending through the first conductive layers and extending between the second conductive layer and the third conductive layer in the first direction;
an insulating member provided between the second conductive layer and the third conductive layer,
a plurality of contact portions of the first conductive layers with the separation member are aligned in the first direction, or
the first conductive layers have substantially a same planar shape from the respective positions where the first, second, and third pillars extend through the first conductive layers to the third slit, as viewed in the first direction.
Lee discloses a semiconductor memory device including teaching
a plurality of memory cell arrays including a first memory cell array, CAR on left in Figure 1, and a second memory cell array, CAR on right in Figure 1, the first memory cell array being separated from the second memory cell array by a boundary region therebetween, CNR, ROW DCR, paragraphs 26 and 31,
an insulating member 118 provided between the second conductive layer and the third conductive layer, paragraph 40,
a plurality of third pillars, DCS1 in Figures 3 and 6, extending through the first conductive layers 131 and extending between the second conductive layer and the third conductive layer in the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the semiconductor memory device of Lee to include a plurality of memory cell arrays including a first memory cell array and a second memory cell array the first memory cell array being separated from the second memory cell array by a boundary region therebetween.
One would have been motivated to do so in order to form a semiconductor memory device incorporating more storage for high capacity data processing, paragraph 3.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a plurality of third pillars to extend through the first conductive layers and extend between the second conductive layer and the third conductive layer in the first direction.
One would have been motivated to do so in order to provide structural support to the stacked structure, paragraph 46.
Kikutani discloses an analogous semiconductor memory device including teaching
a slit includes first and second parts both extending in the first and second (X) directions and a third part, 15t2 in Figure 5A and 5B, extending in the first and third (Y) directions between respective ends of the first and second parts of the slit,
the third part of the slit is positioned along one side of the first conductive layers in the second direction, and the third part of the slit is directly coupled to one end of the first part of the slit and to one end of the second part of the slit and extends linearly in the third direction from one end of the first part of the slit to one end of the second part of the slit as viewed in the first direction,
the separation member includes an insulator 70 covering an inner surface of the slit continuously in the first to third parts of the slit, paragraphs 53 and 54,
the first conductive layers extend in the second direction continuously from respective positions where the first, second, and third pillars extend through the first conductive layers to the separation member, Figure 5B and paragraphs 58 and 59 (“the electrode layers 40 are not formed into stairs in the end portion 15t2)
the one end of the first part of the slit and the one end of the second part of the slit are located on a same side of the respective positions where the first, second, and third pillars extend through the first conductive layers in the second direction, see annotated Figures 5A and 5B below.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the slit to include a third part extending in the first and third directions between respective ends of the first and second parts of the slit,
the third part of the slit to be positioned along one side of the first conductive layers in the second direction, and the third part of the slit to be directly coupled to one end of the first part of the slit and to one end of the second part of the slit and extend linearly in the third direction from one end of the first part of the slit to one end of the second part of the slit as viewed in the first direction,
the separation member to include an insulator covering an inner surface of the slit continuously in the first to third parts of the slit,
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[AltContent: textbox (1st slit)][AltContent: arrow][AltContent: textbox (2nd slit)][AltContent: arrow][AltContent: textbox (3rd slit)][AltContent: arrow][AltContent: arrow]the first conductive layers to extend in the second direction continuously from respective positions where the first, second, and third pillars extend through the first conductive layers to the separation member, and
the one end of the first part of the slit and the one end of the second part of the slit are located on a same side of the respective positions where the first, second, and third pillars extend through the first conductive layers in the second direction.
One would have been motivated to do so in order to provide multiple, laterally separated memory cell arrays within the device, paragraphs 56 and 60.
Kikutani does not disclose the separation member being in direct contact with ends of the first conductive layers in the second direction; or
a plurality of contact portions of the first conductive layers with the separation member are aligned in the first direction, or
the ends of the first conductive layer are in direct contact with the separation member in the second direction.
Sonehara discloses a semiconductor memory device including teaching separation member, 55 in ST1, being in direct contact with ends of the first conductive layers 42, 62 in the second direction, a plurality of contact portions of the first conductive layers 42, 62 with the separation member, 55 in ST1, are aligned in the first direction (Z direction), and the ends of the first conductive layers 42, 62, are in direct contact with the separation member, 55 in ST1, in the second direction, Figures 1, 2, and 5.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the separation member to be in direct contact with ends of the first conductive layers in the second direction, a plurality of contact portions of the first conductive layers with the separation member to be aligned in the first direction, and the ends of the first conductive layers to be in direct contact with the separation member in the second direction. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting the slit with a vertical sidewall as in Sonehara for the slit with an inclined sidewall of Tanaka .
In reference to claim 15, Tanaka discloses the substrate further includes a second block area of the first memory cell array adjacent to the first block area in the third direction Y, the second block area being partitioned by the slit 30 above the substrate (portions of the cell array partitioned by slit 30 in Figure 1),
the slit further includes a fourth part extending in the first and second (X) directions, the second block area above the substrate being sandwiched by the second and fourth parts of the slit in the third direction, paragraph 27, and
Tanaka does not disclose the third part of the slit further extending between respective ends of the second and fourth parts of the slit, and a portion of the conductive layers other than the first conductive layers in the stacked structure contacts with the separation member in a part of the slit at its end in the second direction, the portion of the conductive layers extending in the second direction within the second block area.
Kikutani discloses a third part of the slit further extending between respective ends of second and fourth parts of the slit, Figure 6A, and a portion of the conductive layers other than the first conductive layers in the stacked structure contacts with the separation member in a part of the slit at its end in the second direction, the portion of the conductive layers extending in the second direction within the second block area, Figure 6B and paragraph 62 (“the electrodes 40 are not formed into stairs in the end portion 15t2.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the third part of the slit to further extend between respective ends of the second and fourth parts of the slit, and a portion of the conductive layers other than the first conductive layers in the stacked structure contacts with the separation member in a part of the slit at its end in the second direction, the portion of the conductive layers extending in the second direction within the second block area.
One would have been motivated to do so in order to provide multiple, laterally separated memory cell arrays within the device, paragraph 56.
In reference to claims 21 and 22, Lee discloses the insulating member 118 does not extend through the first conductive layers, Figure 11A (118 only penetrating the top two layers 121).
In reference to claim 25, Sonehara discloses a plurality of contact portions of the first conductive layers 42, 62 with the sixth insulator, 55 in ST1, are aligned in the first direction (Z direction), Figures 1, 2, and 5.
In reference to claim 26, Kikutani discloses the fourth conductive layers 40 extend in the second direction continuously from respective positions where the fourth, fifth, and sixth pillars extend through the fourth conductive layers to the sixth slit, Figure 5B and paragraphs 58 and 59 (“the electrode layers 40 are not formed into stairs in the end portion 15t2) and
Sonehara discloses the ends of the fourth conductive layers 42, 62 are in contact with the sixth insulator, 55 in ST1, in the second direction, Figures 1, 2, and 5.
In reference to claims 27 and 29, Kikutani discloses the first conductive layers 40 have a plate-like shape expanding along the second and third directions within a region from the respective positions where the first, second, and third pillars extend through the first conductive layers to the ends of the first conductive layers, Figure 5B and paragraphs 58 and 59 (“the electrode layers 40 are not formed into stairs in the end portion 15t2).
In reference to claims 28 and 30, Kikutani discloses the first conductive layers 40 have a planar shape extending in the third direction between a side surface of the first slit and a side surface of the second slit and extending continuously in the second direction from the respective positions where the first, second and third pillars extend through the first conductive layers to the ends of the first conductive layers, the side surface of the first slit being along the one side of the first conductive layers in the third direction and the side surface of the second slit being along the other side of the first conductive layers in the third direction, Figure 5B and paragraphs 58 and 59 (“the electrode layers 40 are not formed into stairs in the end portion 15t2).
In reference to claims 31 and 33, Tanaka discloses the one end of the first slit and the one end of the second slit are located on a same side of the respective positions where the first, second, and third pillars extend through the first conductive layers in the second direction, Figure 1.
In reference to claims 32 and 34, Tanaka does not disclose an upper end of the insulating member in the first direction and upper ends of the third pillars in the first direction are aligned with each other.
Lee discloses a semiconductor memory device including teaching an insulating member 118 provided between the second conductive layer and the third conductive layer, paragraph 40,
a plurality of third pillars, DCS1 in Figures 3 and 6, extending through the first conductive layers 131 and extending between the second conductive layer and the third conductive layer in the first direction;
wherein an upper end of the insulating member 118 in the first direction and upper ends of the third pillars DCS1 in the first direction are aligned with each other, Figures 11A and 11C.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for an upper end of the insulating member in the first direction and upper ends of the third pillars in the first direction to be aligned with each other.
One would have been motivated to do so in order to provide structural support to the stacked structure, paragraph 46.
Claims 2 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US 2010/0109071) in view of Lee et al. (US 2019/0244969), Kikutani (US 2017/0263625), and Sonehara (US 2017/0018566) as applied to claims 1 and 14 above and further in view of Ariyoshi (US 10,115,681).
In reference to claim 2, Tanaka discloses a source layer, CS in Figure 4, provided between the substrate 11 and the first conductive layers WL, lower ends of the first and second pillars SP reaching the source layer, paragraph 44.
Tanaka is silent regarding a first portion of the source layer is exposed to the bottom surface of the first slit and a second portion of the source layer is exposed to the bottom surface of the second slit, and the first insulator covers the exposed first portion of the source layer wholly and the second insulator covers the exposed second portion of the source layer wholly.
Ariyoshi (US 10,115,681) discloses a semiconductor memory device including teaching a source layer, 14 in Figure 29, provided between the substrate 9 and the first conductive layers 246, lower ends of the first and second pillars 58 reaching the source layer, col. 36 line 63 to col. 37 line 13, wherein a first portion of the source layer is exposed to the bottom surface of the first slit 79 and a second portion of the source layer is exposed to the bottom surface of the second slit 79, col. 36 lines 23-32, and the first insulator 176 covers the exposed first portion of the source layer wholly and the second insulator covers the exposed second portion of the source layer wholly, col. 38 lines 13-15.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a source layer to be provided between the substrate and the first conductive layers, lower ends of the first and second pillars reaching the source layer, wherein a first portion of the source layer is exposed to the bottom surface of the first slit and a second portion of the source layer is exposed to the bottom surface of the second slit, and the first insulator covers the exposed first portion of the source layer wholly and the second insulator covers the exposed second portion of the source layer wholly. One would have been motivated to do so in order to form a buried source to interconnect the memory cells, col. 34 lines 12-16 and col. 37 lines 9-13.
In reference to claim 16, Tanaka discloses a source layer, CS in Figure 4, provided between the substrate 11 and the first conductive layers WL, lower ends of the first and second pillars SP reaching the source layer, paragraph 44.
Tanaka is silent regarding a first portion of the source layer is exposed to the bottom surface of the first slit and a second portion of the source layer is exposed to the bottom surface of the second slit, and the insulator included in the separation member covers the exposed first and second portions of the source layer wholly.
Ariyoshi (US 10,115,681) discloses a semiconductor memory device including teaching a source layer, 14 in Figure 29, provided between the substrate 9 and the first conductive layers 246, lower ends of the first and second pillars 58 reaching the source layer, col. 36 line 63 to col. 37 line 13, wherein a first portion of the source layer is exposed to the bottom surface of the first slit 79 and a second portion of the source layer is exposed to the bottom surface of the second slit 79, col. 36 lines 23-32, and the insulator 176 included in the separation member covers the exposed first and second portions of the source layer wholly., col. 38 lines 13-15.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a source layer to be provided between the substrate and the first conductive layers, lower ends of the first and second pillars reaching the source layer, wherein a first portion of the source layer is exposed to the bottom surface of the first slit and a second portion of the source layer is exposed to the bottom surface of the second slit, and the insulator included in the separation member covers the exposed first and second portions of the source layer wholly. One would have been motivated to do so in order to form a buried source to interconnect the memory cells, col. 34 lines 12-16 and col. 37 lines 9-13.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US 2010/0109071) in view of Lee et al. (US 2019/0244969), Kikutani (US 2017/0263625), and Sonehara (US 2017/0018566) as applied to claim 8 above and further in view of Lee et al. (US 2016/0343434).
In reference to claims 9 and 10, Tanaka in view of Lee does not disclose inter-area conductive layers disposed between the third insulator and the sixth insulator above the substrate and spaced apart from each other in the first direction, or
a plurality of seventh pillars extending through the inter-area conductive layers in the first direction.
Lee et al. (US 2016/0343434) discloses a semiconductor memory device including teaching inter-area conductive layers, 160 in region DC in Figure 2B, disposed between the third insulator 141 and the sixth insulator 141 above the substrate and spaced apart from each other in the first direction D3, paragraph 69, and a plurality of seventh pillars 150d extending through the inter-area conductive layers in the first direction, paragraph 70. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for inter-area conductive layers to be disposed between the third insulator and the sixth insulator above the substrate and spaced apart from each other in the first direction. One would have been motivated to do so in order to control capacitance within the device, paragraph 69.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yamashita (US 2019/0279996), Oike (US 2019/0371812), Oike (US 2019/0371813), and Oike et al. (US 2019/0214403) discloses a related slit structure and Izumi et al. (US 2016/0093626) discloses conductive layers the all extend through a contact area.
Yamashita (US 2019/0279996), Oike (US 2019/0371812), Oike (US 2019/0371813), and Oike et al. (US 2019/0214403) references potentially have a common owner with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). These references might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
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/BRYAN R JUNGE/Primary Examiner, Art Unit 2897
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