Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment filed on 3/23/2026 has been entered. Claims 15 – 20 are withdrawn. Claims 1, 2, 8, 9 are amended. Claims 7, 14 are canceled. Claims 1 – 6, 8 – 13 are pending in the present application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 6, 8 – 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by More ( Pub. No. US 20230114789 A1 ), hereinafter More.
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Regarding Independent Claim 1 (Currently Amended), More teaches a GAA (gate-all-around) semiconductor device comprising:
a first source/drain region ( More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236; More, FIG. 24, 234; [0023], inner spacer features 234; More, FIG. 24, 202; [0013], substrate 202; More, FIG. 24, 254; [0039], source/drain contacts 254 ) comprising an epitaxially grown first buffer layer ( More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236 ) disposed in contact with first device channels ( More, FIG. 24, 2080; [0035], channel members 2080 ), first device channel inner spacers ( More, FIG. 24, 234; [0023], inner spacer features 234 ) and a device substrate ( More, FIG. 24, 202; [0013], substrate 202 ), and an epitaxially grown first source/drain ( More, FIG. 24, 238S, 240, 238B, 236 ) disposed adjacent to the first buffer layer ( More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236 ) wherein the first buffer layer ( More, FIG. 24. 238S, 240, 238B, 236; [0029]; [0026] ) is undoped ( More, [0011], According to embodiments of the present disclosure, each of the source/drain features is disposed on an undoped semiconductor feature in a source/drain recess ) and is disposed between the first source/drain (More, FIG. 24, 238S, 240, 238B, 236, 254), each of the first device channels ( More, FIG. 24, 2080; [0035], channel members 2080 ), and the first device channel inner spacers ( More, FIG. 24, 234; [0023] ); and
a second source/drain region ( Opposite to the first source/drain region, i.e. on the other side of 250, as shown in More, FIG. 24 ) comprising an epitaxially grown second buffer layer ( Opposite to the first buffer layer, as shown in More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236 ) disposed in contact with second device channels ( More, FIG. 24, 2080; [0035], channel members 2080 ) and second device channel inner spacers ( Opposite to the first device channel inner spacers, as shown in More, FIG. 24, 234; [0023], inner spacer features 234 ) and the device substrate ( More, FIG. 24, 202; [0013], substrate 202 ), and an epitaxially grown second source/drain ( Opposite to the epitaxially grown first source/drain, i.e. on the other side of 250, as shown in More, FIG. 24, 238S, 240, 238B, 236 ) disposed adjacent to the second buffer layer ( Opposite to the first buffer layer, as shown in More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236 ), wherein the second buffer layer ( Opposite to the first buffer layer, as shown in More, FIG. 24. 238S, 240, 238B, 236; [0029]; [0026] ) is disposed between the second source/drain ( Opposite to the epitaxially grown first source/drain, i.e. on the other side of 250, as shown in More, FIG. 24, 238S, 240, 238B, 236, 254 ), each of the second device channels ( More, FIG. 24, 2080; [0035], channel members 2080 ), and the second device channel inner spacers ( Opposite to the first device channel inner spacers, as shown in More, FIG. 24, 234; [0023] );
wherein the first source/drain region ( More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236; More, FIG. 24, 234; [0023], inner spacer features 234; More, FIG. 24, 202; [0013], substrate 202; More, FIG. 24, 254; [0039], source/drain contacts 254 ) and the second source/drain region ( Opposite to the first source/drain region, i.e. on the other side of 250, as shown in More, FIG. 24 ) are disposed on opposing sides of a device gate structure ( More, FIG. 24, 250; [0035], gate structure 250 ); and wherein the device gate structure ( More, FIG. 24, 250; [0035], gate structure 250 ) comprising semiconductor nanosheet channels ( More, FIG. 24, 2080; [0035], channel members 2080 ) disposed between the first source/drain region ( More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236; More, FIG. 24, 234; [0023], inner spacer features 234; More, FIG. 24, 202; [0013], substrate 202; More, FIG. 24, 254; [0039], source/drain contacts 254 ) and the second source/drain region ( Opposite to the first source/drain region, i.e. on the other side of 250, as shown in More, FIG. 24 ).
Regarding Claim 2 (Currently Amended), More teaches the GAA semiconductor device as claimed in claim 1, further comprising wherein the first source / drain comprises a defect-free crystalline structure ( More, [0032], … Voids in the second epitaxial layer 240 may reduce volume of the highly doped second epitaxial layer 240, leading to increased resistance. The voids may also induce other defects in the second epitaxial layer 240, which may also lead to increased resistance … the second epitaxial layer 240 is more likely to merge directly over the inner spacer features 234 to bridge the gaps, leading to smaller or no voids adjacent the sidewalls of the inner spacer features ).
Regarding Claim 3 (Original), More teaches the GAA semiconductor device as claimed in claim 1, further comprising wherein a nanosheet channel comprises a first cross-section having a first area adjacent to the first buffer layer ( More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236 ) and a second cross-section having a second area disposed between adjacent high-k metal gate portions of the gate structure, wherein the first area is larger than the second area ( More, [0015], In some embodiments, all sacrificial layers 206 may have a substantially uniform first thickness and all of the channel layers 208 may have a substantially uniform second thickness. The first thickness and the second thickness may be identical or different. As described in more detail below, the channel layers 208 or parts thereof may serve as channel member(s) for a subsequently-formed multi-gate device and the thickness of each of the channel layers 208 is chosen based on device performance considerations. The sacrificial layers 206 in channel regions(s) may eventually be removed and serve to define a vertical distance between adjacent channel members, which are formed from the channel layers 208, for a subsequently-formed multi-gate device and the thickness of each of the sacrificial layers 206 is chosen based on device performance considerations ).
Regarding Claim 4 (Original), More teaches the GAA semiconductor device as claimed in claim 1, further comprising wherein a nanosheet channel comprises a compressive strained crystalline semiconductor material ( More, [0013], an epitaxial layer (epi-layer), may be strained for performance enhancement; [0029], first epitaxial layer 238 includes … sidewall portions 238S that are disposed directly on sidewalls of the channel layers 208 ).
Regarding Claim 5 (Original), More teaches the GAA semiconductor device as claimed in claim 1, further comprising wherein a nanosheet channel comprises a tensile strained crystalline semiconductor material ( More, [0013], an epitaxial layer (epi-layer), may be strained for performance enhancement; [0029], first epitaxial layer 238 includes … sidewall portions 238S that are disposed directly on sidewalls of the channel layers 208 ).
Regarding Claim 6 (Original), More teaches the GAA semiconductor device as claimed in claim 1, further comprising wherein the first buffer layer ( More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236 ) comprises a first material having a first Ge concentration ( More, [0036], buffer semiconductor layer 236 may include undoped silicon (Si), undoped germanium (Ge), undoped silicon germanium (SiGe), or undoped germanium tin (GeSn) ), the first source/drain ( More, FIG. 24, 254; [0039], source/drain contacts 254 ) comprises a carbon doped Si ( More, [0013], substrate 202 may also include other semiconductors such as germanium (Ge), silicon carbide (SiC); [0024], inner spacer material may include metal oxides, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride )
Regarding Independent Claim 8 (Currently Amended), More teaches a GAA (gate-all-around) semiconductor device comprising:
a first source/drain region ( More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236; More, FIG. 24, 234; [0023], inner spacer features 234; More, FIG. 24, 202; [0013], substrate 202; More, FIG. 24, 254; [0039], source/drain contacts 254 ) comprising an epitaxially grown first buffer layer ( More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236 ) disposed in contact with first device channels ( More, FIG. 24, 2080; [0035], channel members 2080 ), first device channel inner spacers ( More, FIG. 24. 234; [0023], inner spacer features 234 ) and a device substrate ( More, FIG. 24, 202; [0013], substrate 202 ), and an epitaxially grown first doped semiconductor source/drain ( More, FIG. 24, 238S, 240, 238B, 236 ) disposed adjacent to the first buffer layer ( More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236 ), wherein the first buffer layer ( More, FIG. 24. 238S, 240, 238B, 236; [0029]; [0026] ) is undoped ( More, [0011], According to embodiments of the present disclosure, each of the source/drain features is disposed on an undoped semiconductor feature in a source/drain recess ) and is disposed between the first doped semiconductor source/drain ( More, FIG. 24, 238S, 240, 238B, 236, 254 ), each of the first device channels ( More, FIG. 24, 2080; [0035], channel members 2080 ), and the first device inner channel spacers ( More, FIG. 24, 234; [0023] ); and
a second source/drain region ( Opposite to the first source/drain region, i.e. on the other side of 250, as shown in More, FIG. 24 ) comprising an epitaxially grown second buffer layer ( Opposite to the first buffer layer, as shown in More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236 ) disposed in contact with second device channels ( More, FIG. 24, 2080; [0035], channel members 2080 ), second device channel inner spacers ( Opposite to the first device channel inner spacers, as shown in More, FIG. 24, 234; [0023], inner spacer features 234 ) and the device substrate ( More, FIG. 24, 202; [0013], substrate 202 ), and an epitaxially grown second doped semiconductor source/drain ( Opposite to the epitaxially grown first doped semiconductor source/drain, i.e. on the other side of 250, as shown in More, FIG. 24, 238S, 240, 238B, 236 ) disposed adjacent to the second buffer layer ( Opposite to the first buffer layer, as shown in More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236 ), wherein the second buffer layer ( Opposite to the first buffer layer, as shown in More, FIG. 24. 238S, 240, 238B, 236; [0029]; [0026] ) is disposed between the second doped semiconductor source/drain ( Opposite to the epitaxially grown first source/drain, i.e. on the other side of 250, as shown in More, FIG. 24, 238S, 240, 238B, 236 ), each of the second device channels ( More, FIG. 24, 2080; [0035], channel members 2080 ), and the second device channel inner spacers ( Opposite to the first device channel inner spacers, as shown in More, FIG. 24, 234; [0023] );
wherein the first source/drain region ( More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236; More, FIG. 24, 234; [0023], inner spacer features 234; More, FIG. 24, 202; [0013], substrate 202; More, FIG. 24, 254; [0039], source/drain contacts 254 ) and the second source/drain region ( Opposite to the first source/drain region, i.e. on the other side of 250, as shown in More, FIG. 24 ) are disposed on opposing sides of a device gate structure ( More, FIG. 24, 250; [0035], gate structure 250 ), and wherein the device gate structure ( More, FIG. 24, 250; [0035], gate structure 250 ) comprising semiconductor nanosheet channels ( More, FIG. 24, 2080; [0035], channel members 2080 ) disposed between the first source/drain region ( More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236; More, FIG. 24, 234; [0023], inner spacer features 234; More, FIG. 24, 202; [0013], substrate 202; More, FIG. 24, 254; [0039], source/drain contacts 254 ) and the second source/drain region ( Opposite to the first source/drain region, i.e. on the other side of 250, as shown in More, FIG. 24 ).
Regarding Claim 9 (Currently Amended), More teaches the GAA semiconductor device as claimed in claim 8, further comprising wherein the first source / drain comprises a defect-free crystalline structure ( More, [0032], … Voids in the second epitaxial layer 240 may reduce volume of the highly doped second epitaxial layer 240, leading to increased resistance. The voids may also induce other defects in the second epitaxial layer 240, which may also lead to increased resistance … the second epitaxial layer 240 is more likely to merge directly over the inner spacer features 234 to bridge the gaps, leading to smaller or no voids adjacent the sidewalls of the inner spacer features ).
Regarding Claim 10 (Original), More teaches the GAA semiconductor device as claimed in claim 8, further comprising wherein a nanosheet channel comprises a first cross-section having a first area adjacent to the first buffer layer ( More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236 ) and a second cross-section having a second area disposed between adjacent high-k metal gate portions of the gate structure, wherein the first area is larger than the second area ( More, [0015], In some embodiments, all sacrificial layers 206 may have a substantially uniform first thickness and all of the channel layers 208 may have a substantially uniform second thickness. The first thickness and the second thickness may be identical or different. As described in more detail below, the channel layers 208 or parts thereof may serve as channel member(s) for a subsequently-formed multi-gate device and the thickness of each of the channel layers 208 is chosen based on device performance considerations. The sacrificial layers 206 in channel regions(s) may eventually be removed and serve to define a vertical distance between adjacent channel members, which are formed from the channel layers 208, for a subsequently-formed multi-gate device and the thickness of each of the sacrificial layers 206 is chosen based on device performance considerations ).
Regarding Claim 11 (Original), More teaches the GAA semiconductor device as claimed in claim 8, further comprising wherein a nanosheet channel comprises a compressive strained crystalline semiconductor material ( More, [0013], an epitaxial layer (epi-layer), may be strained for performance enhancement; [0029], first epitaxial layer 238 includes … sidewall portions 238S that are disposed directly on sidewalls of the channel layers 208 ).
Regarding Claim 12 (Original), More teaches the GAA semiconductor device as claimed in claim 8, further comprising wherein a nanosheet channel comprises a tensile strained crystalline semiconductor material ( More, [0013], an epitaxial layer (epi-layer), may be strained for performance enhancement; [0029], first epitaxial layer 238 includes … sidewall portions 238S that are disposed directly on sidewalls of the channel layers 208 ).
Regarding Claim 13 (Original), More teaches the GAA semiconductor device as claimed in claim 8, further comprising wherein the first buffer layer ( More, FIG. 24. 238S, 240, 238B, 236; [0029], sidewall portions 238S, bottom portion 238B; second epitaxial layer 240; [0026], buffer semiconductor layer 236 ) comprises a first material having a first Ge concentration ( More, [0036], buffer semiconductor layer 236 may include undoped silicon (Si), undoped germanium (Ge), undoped silicon germanium (SiGe), or undoped germanium tin (GeSn) ), the first source/drain ( More, FIG. 24, 254; [0039], source/drain contacts 254 ), the first source/drain ( More, FIG. 24, 254; [0039], source/drain contacts 254 ) comprises a carbon doped Si ( More, [0013], substrate 202 may also include other semiconductors such as germanium (Ge), silicon carbide (SiC); [0024], inner spacer material may include metal oxides, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride ).
Response to Arguments
Applicant’s argument for claim 1 ( currently amended ): page 9, line 7 from bottom, cited “ The Office Action, page 2, provides that elements 238S, 238B, 240, and 236, comprise the claimed epitaxially grown first buffer layer. Applicant respectfully disagrees. As provided in More, paragraphs [0026] - [0031] the device comprises buffer semiconductor layer 236 comprised of an undoped material to reduce its conductivity, while first epitaxial layer 238 (comprising elements 238S and 238B) comprises a doped material such as arsenic doped silicon and second epitaxial layer 240 is heavily doped (paragraph [0030]) disqualifying elements 238S and 238B as possible undoped buffer layer elements. Applicant submits that choosing to characterize the combination of elements 236, 2385, 238B, and 240, as a common element "buffer layer" the combination cannot be characterized as "undoped" as most portion fo ( ps. this should be “ of ” ) the combination are doped. Further, as provided in paragraph [0034] of the reference, "Referring to FIG. 13, the first epitaxial layer 238, the second epitaxial layer 240 and the third epitaxial layer 242 over one source/drain region 212SD may be collectively referred to as a source/drain feature 248. The source/drain feature 248 interfaces sidewalls of the channel layers 208 and a top surface of the buffer semiconductor feature 236 by way of the first epitaxial layer 238." Applicant submits that doped elements characterized as portions of the source/drain feature can not also comprise portions of the buffer layer with element 236. ”.
Examiner’s response: based on the original specification, FIG. 6 and FIG. 13, 601 is buffer layer, which is on the side walls and the bottom surface of the source/drain region 710, so the buffer layer includes two parts: the side walls and the bottom surface of the source/drain region 710; besides, [0059], cited “ Buffer layer 610 may comprise doped or undoped semiconductor material ”, which means the buffer layer may be doped; besides, based on the amended claim 1, the second buffer layer does not have the limitation of “ undoped ”, which means the buffer layer may be doped; besides, as asked by examiners in the interview 3/11/2026, “ If buffer layer 610 in FIG. 13 is undoped, then how transistor work ? because undoped source/drain is not conductive or extreme low conductivity. ”. Therefore, the first buffer layer is mapped by More ( FIG. 24, 238S, 238B, 240, 238B, 236 ) to map two parts of the buffer layer, and the “ undoped ” limitation is mapped by “ ( More, [0011], According to embodiments of the present disclosure, each of the source/drain features is disposed on an undoped semiconductor feature in a source/drain recess ) ”.
Applicant’s argument for claim 1 ( currently amended ): page 10, line 11, cited “ The Office Action characterizes element 254, source drain contacts, as the claimed first source/drain. Paragraph [0039] of More provides: "The source/drain contact 254 may include cobalt (Co), nickel (Ni), titanium (Ti), or tungsten (W) and may be deposited using PVD or a suitable deposition method". Applicant submits that such metallic materials are not suitable or effective as materials for a source/drain feature and that as provided in paragraph [0034] the source/drain feature of the reference includes doped, epitaxially grown layers 238, 240, and 242. ”.
Examiner’s response: “ More, FIG. 24, source/drain contact 254 ” is used to map the contact part of source/drain region, “ More, FIG. 24, sidewall portions 238S, bottom portion 238B, second epitaxial layer 240 ” are used to map the epitaxially grown part of source/drain region, as shown in this office action.
Applicant’s argument for claim 1 ( currently amended ): page 10, line 7 from bottom, cited “ Similar arguments may be made with regard to the second buffer layer of the second source/drain region where the Office Action seeks to characterize portions of the epitaxially grown doped source drain feature, 238S, 238B and 240, as buffer layer components to achieve an element having the claimed buffer layer characteristics. ”.
Examiner’s response: based on the amended claim 1, the second buffer layer does not have the limitation of “ undoped ”, which means the buffer layer may be doped, and More ( FIG. 24, 238S, 238B, 240, 238B, 236 ) is enough to map two parts ( i.e. the side walls and the bottom surface of the source/drain region ) of the buffer layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights