Prosecution Insights
Last updated: May 29, 2026
Application No. 17/544,136

SUBTRACTIVE LINE WITH DAMASCENE TOP VIA

Non-Final OA §103§112
Filed
Dec 07, 2021
Examiner
LUKE, DANIEL M
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
4 (Non-Final)
71%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
487 granted / 688 resolved
+2.8% vs TC avg
Strong +20% interview lift
Without
With
+19.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
19 currently pending
Career history
719
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
81.1%
+41.1% vs TC avg
§102
10.5%
-29.5% vs TC avg
§112
7.3%
-32.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 688 resolved cases

Office Action

§103 §112
DETAILED ACTION This office action is in response to the amendment filed 8/20/2025. Currently, claims 8-10 and 13-14 are pending. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 8-10 and 13-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 8 has been amended to recite “wherein the second bottom metal layer wire comprises a second wire height that is less than the wire height [of the bottom metal layer wire]”. In the remarks filed 8/20/2025, Applicant cites Figures 9A-10B and paragraph [0036] of the disclosure as filed as providing support for such a feature. paragraph [0036] is reproduced below: [0036] The top via 134 may include a via liner 136 that is deposited within the via hole 132 before forming the top via 134. The via liner 136 may include a material such as TaN or TiN to improve adhesion the top via 134 to the low-K layer 130. The forming of the top via 134 may include metallizing the via hole 132 with a metal that is different from a metal of the bottom metal layer 104. Furthermore, forming the bottom metal layer 104 from one metal and forming the top via 134 from another metal is generally not possible when top via is formed by subtractive manner of tall metal line. The top via 134 may include a via width that is equal to the bottom metal layer wire 112b width. In the context of this application, having a width that is equal to another width means that the widths are substantially the same, on the scale of the specific fabricated component. In the specific instance of the top via 134 and the bottom metal layer wire 112b width, having an "equal" width means that any difference between the width of the top via 134 and the bottom metal layer wire 112b is approximately the thickness of the via liner 136, and not greater. The cited passage does not contain any accounting for the heights of the bottom metal layer wires, let alone the detail that the height of the second bottom metal layer wire is less than the height of the bottom metal layer wire. With respect to FIG. 9A-10B, the figures depict the semiconductor structure at different fabrication stages within the method of manufacture. FIG. 9 depicts the deposition of the via liner 136 and the top via 134, while FIG. 10 depicts the formation of top metal layer wire 138. Neither of these figures relate to the bottom metal layer wires 112a-c. In the case that the support is alleged to come from the presence of substrate liner 114 under wire 112c, the Examiner notes that, with respect to the presence of the substrate liner, the specification states it paragraph [0026]: Some of the bottom metal layer wires 112a, b, c may be formed with a substrate liner 114 between the substrate 102 and the bottom metal layer wire. In embodiments with a substrate liner 114, typically all bottom metal layer wires 112a, b, c would have the substrate liner 114 below, but for illustrative purposes the semiconductor structure 100 only includes the substrate liner 114 under the third bottom metal layer wire 112c. Indeed, all three wires are formed in a same patterning of a same structure (FIG. 1-2). Therefore, the limitation ““wherein the second bottom metal layer wire comprises a second wire height that is less than the wire height” is considered to be new matter. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 8-10 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 6,080,674) in view of Liu (US 11,302,570), Nogami et al. (US 6,235,632) and Siew (US 9,997,402). Pertaining to claim 8, Wu shows, with reference to FIG. 2f, a semiconductor structure, comprising: a bottom metal layer wire (213, below “V1”) comprising a wire width and a wire height (inherent); a top via hole (V1) above the bottom metal layer wire, wherein the top via hole comprises a via width that is equal to the wire width; and a dielectric layer (41) formed of a single material surrounding the bottom metal layer wire and the top via hole, wherein the low-k layer covers a second bottom metal layer wire adjacent to the bottom metal layer wire. Wu fails to show that the dielectric layer is a low-k dielectric; and a via in the via hole, with a via liner between the bottom metal layer wire and the top via and on lateral sides between the top via and the a low-k layer. Furthermore, Wu fails to show the second bottom metal layer wire comprises a second wire height that is less than the wire height. However, Liu teaches in col. 9, lines 26-42 that, for a similar structure, the material of the dielectric layer may be a low-k material. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to substitute the material of the dielectric layer of Wu for the low-k material taught by Liu, as the court has held that the simple substitution of one known element for another to obtain predictable results is prima facie obvious. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Furthermore, it is well established that a lower k-value of an interlayer dielectric corresponds with improved electrical isolation, reducing issues such as crosstalk. Meanwhile, Nogami teaches in FIG. 1b-e that, for a similar interconnection structure, a metal via 24 is formed in the via hole 18 with a via liner 20 between the bottom metal layer wire 10 and the via and on lateral sides between the via and the dielectric layer 16. The via in the via hole, as taught by Nogami, is required for structure of Wu to function as in interconnect, and thus would be obvious to one of ordinary skill in the art. The via liner acts as a diffusion barrier (Nogami, col. 1, lines 14-17), preventing unwanted diffusion between materials, and thus one of ordinary skill in the art would find the teaching of the via liner to be applicable to Wu. Additionally, Siew teaches in FIG. 1 that conductive lines such as those of Wu are formed to include liner/barrier layer structures. The result of the inclusion of these layers is a metal layer wire 234 that has a height less than that of metal layer wire 232. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to apply the teaching of the liner structures of Siew to Wu with the motivation that the resulting conductive structure is taught to have a low resistance (Siew, col. 4, lines 22-23). Pertaining to claim 9, Nogami teaches the bottom metal layer wire comprises a first material (col. 3, lines 7-8) and the top via comprises a second material that is different from the first material (col. 3, lines 51-52). Pertaining to claim 10, Wu shows the via hole V1, which defines the dimensions of the top via, comprises lateral sides that are perpendicular to a top surface of the dielectric layer (FIG. 2f). Thus, when applying the teaching of Nogami to Wu, the via in the via hole will also have lateral sides that are perpendicular to a top surface of the dielectric layer. Pertaining to claim 13, Nogami teaches the metal layer wire material is e.g. copper (col. 3, lines 7-8). Pertaining to claim 14, Liu teaches in e.g. FIG. 1O-2 that a substrate 102 is below the metal layer wire 136, wherein the substrate comprises transistor devices (gate 106, S/D 105 and channel therebetween). Response to Arguments Applicant's arguments filed 8/20/2025 have been fully considered but they are not persuasive. Applicant argues that none of Wu, Liu and Nogami teaches a second bottom metal layer wire that has a wire height that is less than that of the first. In response, none of Wu, Liu and Nogami are relied upon for such a teaching. Rather, this is taught by Siew as discussed in the rejections above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL LUKE/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Show 11 earlier events
Aug 13, 2025
Interview Requested
Aug 20, 2025
Response Filed
Oct 02, 2025
Final Rejection mailed — §103, §112
Oct 28, 2025
Interview Requested
Nov 17, 2025
Examiner Interview Summary
Nov 17, 2025
Applicant Interview (Telephonic)
Dec 02, 2025
Response after Non-Final Action
May 01, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
71%
Grant Probability
90%
With Interview (+19.7%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 688 resolved cases by this examiner. Grant probability derived from career allowance rate.

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