DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/29/2025 has been entered.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2007/0025226 A1) in view of Jeong et al. (US 2010/0240189 A1).
Regarding claim 1, Park discloses a semiconductor structure (Fig. 9) comprising:
a bottom electrode (“heating electrode 310”, ¶ 0043) including a recess (see Fig. 9); and
a memory cell (“phase change layer 112”, ¶ 0043), where a portion (portion within 310) of phase change material forming the memory cell is located within the recess formed inside a plug of the bottom electrode (see Fig. 9; as 310 plugs the opening in 104, it is considered to be a plug).
Park differs from the claimed invention by the substitution of a metal for the plug with “any material that emits Joule heat by receiving a current” (¶ 0027). However, metal and the corresponding function was known in the art (¶ 0093 of Jeong). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the known material of metal as taught by Jeong for material of Park and the results of the substitution would have been predictable. (see MPEP § 2143(I)(B)).
Regarding claim 2, Park in view of Jeong further discloses wherein the memory cell is a phase change memory cell (¶ 0041).
Regarding claim 3, Park in view of Jeong further discloses wherein the portion of the memory cell is a first portion of the memory cell, and the semiconductor structure further comprises:
a first layer (combination of 310 and the first portion of the memory cell) including the bottom electrode and the first portion of the memory cell;
a second layer (portion of 112 above 310) on top of the first layer, the second layer including a second portion (portion of 112 above 310) of the memory cell; and
a third layer (114) on top of the second layer, the third layer including a top electrode (“upper electrode 114”, ¶ 0043) connected to the memory cell.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park and Jeong as applied to claim 3 and further in view of Lai et al. (US 9,537,093 B1).
Regarding claim 4, Park does not disclose the inclusion of a metal liner deposited on sidewalls of the second portion of the memory cell.
Lai, in the same field of endeavor, discloses forming a metal liner (“conductive spacers 216A, 216B” in Fig. 4B, Col. 4, Lines 16-17) on sidewalls of a memory cell (202).
There was a benefit to forming metal liners on the sidewalls of a memory cell in that is aids in providing stable resistance and stable operating efficiency (Col. 2, Lines 35-36 of Lai).
It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to deposit the metal liner as taught by Lai on the sidewalls of the second portion of the memory cell of Park for this benefit.
Regarding claim 5, Park does not disclose that the second layer further comprises a first insulator and a second insulator, and the second portion of the memory cell is between the first insulator and the second insulator.
Lai, in the same field of endeavor, discloses forming a first insulator and a second insulator (insulating layers 240 in Figs. 6A and 6B) such that the memory cell is between the first insulator and the second insulator (see Fig. 6B).
There was a benefit to forming first and second insulators on either side of a memory cell in that it adds structural protection to the memory cell, reducing the risk of damage.
It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a first insulator and a second insulator as taught by Lai in the second layer of Park such that the second portion of the memory cell is between the first insulator and the second insulator for this benefit.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park and Jeong as applied to claim 1 and further in view of Lai et al. (US 9,537,093 B1).
Regarding claim 6, Park does not disclose the inclusion of a metal liner deposited on sidewalls of the memory cell.
Lai, in the same field of endeavor, discloses forming a metal liner (“conductive spacers 216A, 216B” in Fig. 4B, Col. 4, Lines 16-17) on sidewalls of a memory cell (202).
There was a benefit to forming metal liners on the sidewalls of a memory cell in that is aids in providing stable resistance and stable operating efficiency (Col. 2, Lines 35-36 of Lai).
It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to deposit the metal liner as taught by Lai on the sidewalls of the memory cell of Park for this benefit.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5.
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/CHRISTOPHER A CULBERT/Examiner, Art Unit 2815