DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claim 1 in the Applicant’s response dated 2 December 2025. The claim amendments and the Applicant’s accompanying comments have been addressed below.
The Examiner acknowledges the amendments to claim 3-7 in the Applicant’s response dated 2 December.
The Examiner acknowledges the cancellation of claims 2, 12 and 19-20 in the Applicant’s response dated 2 December.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-6, 13 and 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Minhyun Lee et al. (US 2019/0148493 A1; hereinafter “Lee”).
Regarding Claim 1, Lee teaches an integrated circuit (IC) device comprising:
a transistor comprising a gate (109 and 108, Fig. 9, para [0044] describes a gate electrode 109 and gate insulating film 108), a channel (101, Fig. 9, para [0045] describes a semiconductor layer 101 wherein a portion below the gate structure and between a source region 102 and drain region 103 comprises a channel region), and a source/drain (S/D) region (102, Fig. 9, para [0046] describes source region 102); and
a S/D contact coupled to the S/D region (104, 106 and 111a, Fig. 9, describes structures contacting source region 102), the S/D contact comprising:
an inner conductive structure (106, Fig. 9, para [0065] describes a conductive metal layer forming a source electrode 106); and
a barrier region coupled between the S/D region and the inner conductive structure (104 and 111a, Fig. 9, para [0065] describes a mixture layer 111a and a graphene layer 104 between the S/D region 102 and the inner conductive structure 106), the barrier region comprising:
a metal layer comprising a metal (111a, Fig. 9, para [0065] describes a mixture layer 111a comprising a metal); and
a carbon layer comprising carbon in a graphitic or diamond crystal structure (104, Fig. 9, para [0050] describes a 2D material layer that may be formed in a crystal of a carbon element, such as graphene).
Regarding Claim 3, Lee teaches the IC device of claim 1, wherein the metal comprises niobium (111a, Fig. 9, para [0065] describes wherein the mixture layer 111a may comprise a same metal as the inner conductive structure 106 wherein said metal may be niobium as described in para [0054]).
Regarding Claim 4, Lee teaches the IC device of claim 1, wherein the metal comprises tantalum (111a, Fig. 9, para [0065] describes wherein the mixture layer 111a may comprise a same metal as the inner conductive structure 106 wherein said metal may be tantalum as described in para [0054]).
Regarding Claim 5, Lee teaches the IC device of claim 1, wherein the metal comprises aluminum (111a, Fig. 9, para [0065] describes wherein the mixture layer 111a may comprise a same metal as the inner conductive structure 106 wherein said metal may be aluminum as described in para [0054]).
Regarding Claim 6, Lee teaches the IC device of claim 1, wherein the carbon layer has a thickness between 0.1 and 2 nanometers (104, Fig. 9, para [0061] describes wherein the thickness of the 2D material layer 104 may be within a range of 0.3 to 5 nm wherein a thickness of 0.5 nm would fall within the range of 0.1 to 2 nanometers).
Regarding Claim 13, Lee teaches the IC device of claim 1, further comprising:
a second S/D region (103, Fig. 9, para [0046] describes a drain region 103); and
a second S/D contact coupled to the second S/D region (105, 107 and 111b, Fig. 9, describes structures contacting drain region 103), the second S/D contact comprising an inner conductive structure (107, Fig. 9, para [0065] describes a conductive metal layer forming a drain electrode 107) and a barrier region (105 and 111b, Fig. 9, para [0065] describes a mixture layer 111b and a graphene layer 105 between the S/D region 103 and the inner conductive structure 107).
Regarding Claim 21, Lee teaches the IC device of claim 1, wherein the S/D region comprises silicon (102, Fig. 9, para [0047] describes wherein source region 102 may comprise silicon).
Regarding Claim 22, Lee teaches the IC device of claim 1, wherein the inner conductive structure comprises titanium (106, Fig. 9, para [0054] describes wherein inner conductive structure 106 may comprise titanium).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Minhyun Lee et al. (US 2019/0148493 A1; hereinafter “Lee”) in further view of Chih-Yen Chen et al. (US 2020/0127116 A1; hereinafter “Chen”).
Regarding Claim 7, Lee discloses all the limitations of claim 1.
Lee fails to explicitly disclose the IC device of claim 1, wherein the metal layer has a thickness between 0.1 and 2 nanometers.
However, Chen teaches a similar IC device, wherein the metal layer has a thickness between 0.1 and 2 nanometers (118, Fig. 1F, para [0036] describes a lining layer 118 formed under a source electrode 120 wherein the lining layer comprises a graphene layer and a metal such as aluminum and has a thickness in a range from about 0.5 nm to 4 nm, such as 2 nm wherein a resulting thickness of the metal material in said lining layer would fall within a range of 0.1 nm to 2 nm).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Lee with Chen to further disclose an integrated circuit device wherein a metal layer has a thickness between 0.1 and 2 nm in order to provide the advantage of enabling the barrier region and metal layer comprised within to be of a thickness which may lower the contact resistance between a source/drain electrode and the layers from which the barrier layer intervenes further increasing device performance (Chen, para [0043]).
Regarding Claim 24, Lee discloses all the limitations of claim 21.
Lee fails to explicitly disclose the IC device of claim 21, wherein the barrier region has a thickness between 0.25 and 2.5 nanometers.
However, Chen teaches a similar IC device, wherein the barrier region has a thickness between 0.25 and 2.5 nanometers (118, Fig. 1F, para [0036] describes a lining layer 118 formed under a source electrode 120 wherein the lining layer comprises a graphene layer and a metal such as the barrier layer of Lee and further has a thickness in a range from about 0.5 nm to 4 nm, such as 2 nm wherein a resulting 2 nm thickness of the lining layer would fall within a range of 0.25 nm to 2.5 nm).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Lee with Chen to further disclose an integrated circuit device wherein a barrier layer has thickness between 0.25 and 2.5 nanometers in order to provide the advantage of enabling the barrier region to be of a thickness which may lower the contact resistance between a source/drain electrode and the layers from which the barrier layer intervenes further increasing device performance (Chen, para [0043]).
Claims 23 are rejected under 35 U.S.C. 103 as being unpatentable over Minhyun Lee et al. (US 2019/0148493 A1; hereinafter “Lee”) in further view of Emre Alptekin et al. (US 2015/0270179 A1; hereinafter “Alptekin”).
Regarding Claim 23, Lee discloses all the limitations of claim 22.
Lee fails to explicitly disclose the IC device of claim 22, wherein the titanium is in a liner of the inner conductive structure, and the inner conductive structure further comprises a core comprising a second metal.
However, Alptekin teaches a similar IC device, wherein the titanium is in a liner of the inner conductive structure (655, Fig. 6, para [0054] describes a liner titanium layer 655 surrounding fill metal 660 of the source/drain contact), and the inner conductive structure further comprises a core comprising a second metal (660, Fig. 6, para [0054] describes a conductive fill metal 660 comprising a second metal such as tungsten wherein the fill metal 660 is surrounded by titanium liner 655).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Lee with Alptekin to further disclose an integrated circuit device wherein a source/drain contact comprises a titanium liner and a core of a second metal in order to provide the advantage of promoting adhesion from a surrounding dielectric layer to a source/drain contact and preventing diffusion of a metal layer into a surrounding dielectric material (Alptekin, para [0054]).
Response to Arguments
Applicant’s arguments with respect to independent claim 1 and claims 3-7, 13 and 21-24 dependent therefrom, have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Thursday 7:00 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights