Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is final.
This action is in response to the amendments and arguments filed on 07/22/2025.
Claims 1-20 are pending and have been considered.
Independent claims 1, 8, and 15 have been amended.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The amendments have not made the claims eligible.
The rejection of Claims 1-3, 5-10, 12-17, 19, and 20 under 35 U.S.C. 103 as being unpatentable over Tom et al. “Un/DoPack: Re-Clustering of Large System-on-Chip Designs with Interconnect Variation for Low-Cost FPGAs” (“Tom”) in view of Rostoker et al. (US Pat 5,557,531) (“Rostoker”) is withdrawn In view of the amendments.
The rejection of Claims 4, 11, and 18 under 35 U.S.C. 103 as being unpatentable over Tom in view of Rostoker, and in further view of Feng et al. (US PGPub 20150020038) (hereinafter "Feng") is withdrawn In view of the amendments.
Claims 1-6, 8, 10, 11, 13, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (US PGPub 20150020038) (hereinafter “Feng”) in view of Tom et al. “Un/DoPack: Re-Clustering of Large System-on-Chip Designs with Interconnect Variation for Low-Cost FPGAs” ( “Tom”)
Claims 7, 9, 12, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (US PGPub 20150020038) (hereinafter “Feng”) in view of Tom et al. “Un/DoPack: Re-Clustering of Large System-on-Chip Designs with Interconnect Variation for Low-Cost FPGAs” ( “Tom”) in further of in view of Rostoker et al. (US Pat 5,557,531) (“Rostoker”)
Response to Amendments/Arguments
The Examiner thanks the Applicant for the Amendments and Arguments filed on 07/22/2025. Independent claims 1, 8, and 15 have been amended. Applicant argues that the amendments overcome the rejections.
Regarding the rejections under 35 USC 101 rejection have been considered but have not been found persuasive.
The amendment has not changed the nature of the claim, and the specific limitation is of a mental process nature as generating the estimations for routability and logic usage based on Rent’s rule can be simply performed in the mind or with pen and paper, being a simple formula. As for the argument that the specification describes an improvement, the Examiner acknowledges the specification presents it this way, however in view of the Alice/Mayo analysis, both the improvement needs to be reflected in the claim and the improvement needs to come from additional elements, and not from the abstract idea. As drafted, the independent claims recite abstract ideas in the generation of estimation (as discussed above, reciting a mental process) and determining the estimates allow implementation (a comparison of values that can be performed in the mind), and additional elements of receiving the high-level coding, and performing synthesis, both being well-known and understood, which bring no improvement and nothing significantly more. The claims remain directed to an abstract idea, without significantly more and are not found eligible under 35 USC 101.
Regarding the Claim rejections under 35 U.S.C. 103. Applicant’s arguments have been considered. However, the arguments is moot in view of the Feng reference, used in the previous Office Action in the rejection of claims 4, 11, and 18. In view of the amendment a new search was performed and Feng found again in the search. In presenting arguments in the rejection of claims 4, 11, and 18, Applicant argued that Feng does not cure the deficiencies of Tom and Rostoker to show all of the limitations of the independent claims.
Feng however teaches most limitations of independent claim and combined with Tom, teaches all the limitation of the independent claim. Claims are interpreted under broadest reasonable interpretation. A person skilled in the art would have recognized both the benefits of using Rent;s rule, as those in the field have known and used for estimation extensively since 1960s (as early predictor, even if imperfect accuracy compared to checking after place and route) and motivated to combine with Tom that teaches the check comparison of estimates to overall resources. The rejection over Tom in view of Rostoker are withdrawn, and instead a new rejection is made over Feng in view of Tom. The dependent claims are also rejected according to the changes of the rejections of the independent claims. The action is properly made final as the amendment necessitated new search.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1: Claims 1-7 are directed to a method and falls within the statutory category of processes; Claims 8-14 are directed to a non-transitory computer readable media and fall within the statutory category of articles of manufacture; and Claims 15-20 are directed to a system and fall within the statutory category of machines. Therefore, claims 1-20 are directed to patent eligible categories of invention.
Step 2A Prong 1: The limitations of claims 1, 8, and 15 of “generating a routability estimation and a logic usage estimation for the synthesized design, based on Rent's rule using parameters tuned to types of circuits in a specific FPGA;”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper. For example, a person can, with the use of pen and paper, perform synthesis on a design to mentally generate a routability estimation and a logic usage estimation, which could include counting the routing elements and the logic objects of the synthesized design. Rent’s rule /formula is If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claims recite an abstract idea under Prong 1 step 2A.
Additionally, the limitations of claims 1 and 15 of “determining whether the synthesized design is implementable on a specific FPGA, based on the routability estimation, the logic usage estimation, and available resources of the specific FPGA”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper. For example, a person can mentally determine whether a synthesized design is implementable on a specific FPGA by comparing the routability and logic usage estimations to the available resources of the FPGA. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claims recite an abstract idea under Prong 1 step 2A.
Further, the limitations of claim 8 of “determining and indicating to a user whether the synthesized design is implementable on a specific FPGA, based on the routability estimation, the logic usage estimation, and available resources of the specific FPGA”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper. For example, a person can mentally determine and, with the use of pen and paper, indicate to a user whether a synthesized design is implementable on a specific FPGA by comparing the routability and logic usage estimations to the available resources of the FPGA. A person, with the use of pen and paper, can also indicate to a user whether the synthesized design is implementable If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong 1 step 2A.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. In particular, claims 1, 8, and 15 respectively recite additional elements of “A method, performed by a computer aided design (CAD) system, comprising”, “A tangible, non-transitory, computer-readable media having instructions thereupon which, when executed by a processor, cause the processor to perform a method comprising”, and “A computer aided design (CAD) system, comprising: a memory, to … and a processor, to” which are merely recitations of generic computing components and functions being used as a tool to implement the judicial exception (see MPEP § 2106.05(f)) which does not integrate a judicial exception into a practical application.
Further, claims 1, 8, and 15 also recite additional elements such as “receiving a high level coding of a design for a circuit to be implemented in a field programmable gate array (FPGA)” and performing synthesis on the design, to produce a synthesized design” which are merely recitations of insignificant extra-solution data gathering activity (See MPEP § 2106.05(g)) and to doing synthesis, a well known activity, which does not integrate a judicial exception into a practical application. Therefore, this additional element does not integrate the abstract idea into a practical application and it does not impose any meaningful limits on practicing the abstract idea. The claims are directed to an abstract idea under Steps 2A Prong 1 and 2. The insignificant extra-solution activities are further addressed below under step 2B as also being Well-Understood, Routine, and Conventional (WURC). The insignificant extra-solution activities are further addressed below under step 2B as also being Well-Understood, Routine, and Conventional (WURC).
Step 2B: The claims 1, 8, and 15 do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components and field of use/technological environment which do not amount to significantly more than the abstract idea. Further, the insignificant extra-solution data gathering activities are also Well-Understood, Routine and Conventional (see MPEP § 2106.05(d)(ll) "The courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network"). Similarly, performing logic synthesis is WURC, and basis of all (digital) semiconductor industry -see https://en.wikipedia.org/wiki/Logic_synthesis, and for example Burgun, Luc; Greiner, Alain; Prado Lopes Eudes (October 1994). "A Consistent Approach in Logic Synthesis for FPGA Architectures". Proceedings of the International Conference on ASIC. Pekin: 104–107. Jiang, Jie-Hong "Roland"; Devadas, Srinivas (2009). "Chapter 6: Logic synthesis in a nutshell". In Wang, Laung-Terng; Chang, Yao-Wen; Cheng, Kwang-Ting (eds.). Electronic design automation: synthesis, verification, and test. Morgan Kaufmann. ISBN 978-0-12-374364-0. Hachtel, Gary D.; Somenzi, Fabio (2006) [1996]. Logic Synthesis and Verification Algorithms. Springer Science & Business Media. ISBN 0-7923-9746-0. Hassoun, Soha; Sasao, Tsutomu, eds. (2002). Logic synthesis and verification. Kluwer. ISBN 978-0-7923-7606-4.
Therefore, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception. Having concluded analysis within the provided framework, claims 1, 8, and 15 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claims 2 and 16, they recite additional limitations of “the determining comprises comparing the logic usage estimation and the logic capacity, and comparing the routability estimation and the routing capacity”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper. For example, a person can mentally compare the logic usage estimation to the logic capacity and compare the routability estimation to the routing capacity. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claims recite an abstract idea under Prong 1 step 2A.
Further, regarding claims 2 and 16, they also recite additional element recitations of “wherein: the available resources of the specific FPGA comprise logic capacity and routing capacity” which is merely a recitation of a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into a practical application. Further, these claims do not recite any further additional elements and for the same reasons as above with regard to integration into a practical application and whether additional elements amount to significantly more, these claims also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as they have not been integrated into a practical application, and fail Step 2B as not amounting to significantly more. Therefore, claims 2 and 16 do not recite patent eligible subject matter under 35 U.S.C. §101.
Regarding claims 3, 10, and 17, they recite additional limitations of “the determining comprises determining whether the logic usage estimation and the routability estimation fit within the combined first, second and third logic elements including a trade-off in usage of the logic and the routing of the third logic elements”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper. For example, a person can mentally determine whether the logic usage estimation and the routability estimation fit within the combined first, second, and third logic elements and mentally trade-off the usage of logic and routing in the third logic elements. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claims recite an abstract idea under Prong 1 step 2A.
Further, regarding claims 3, 10, and 17, they also recite additional element recitations of “wherein: the available resources of the specific FPGA comprise first logic elements (LEs) that are logic-only, second logic elements that are routing-only, and third logic elements that are usable for either of logic and routing” which is merely a recitation of a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into a practical application. Further, these claims do not recite any further additional elements and for the same reasons as above with regard to integration into a practical application and whether additional elements amount to significantly more, these claims also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as they have not been integrated into a practical application, and fail Step 2B as not amounting to significantly more. Therefore, claims 3, 10, and 17 do not recite patent eligible subject matter under 35 U.S.C. §101.
Regarding claims 4, 11, and 18, they recite additional limitations of “wherein: the generating the routability estimation and the logic usage estimation are in accordance with Rent's rule regarding a relationship between a number of external signal connections to a logic block and a number of logic gates in the logic block; and the generating includes recursive bipartitioning of the synthesized design”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper. For example, a person can mentally generate the routability and logic usage estimations in accordance with Rent’s rule by considering the number of external signal connections to a logic block and the number of logic gates in the logic block in the estimations. A person can also, with the use of pen and paper, use recursive bipartitioning by repeatedly splitting portions of the synthesized design into two parts when mentally generating the estimations. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claims recite an abstract idea under Prong 1 step 2A. (One should also note that using recursive bipartitioning of the synthesized design is a well-known, WURC process.)
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Further, regarding claims 4, 11, and 18, the additional element recitations of “the generating the routability estimation and the logic usage estimation are in accordance with Rent's rule regarding a relationship between a number of external signal connections to a logic block and a number of logic gates in the logic block”, as drafted, is a process that, under its broadest reasonable interpretation, also covers mathematical operations but for the recitation of generic computer components. . For example, an equation can be developed using Rent’s rule to generate the routability and logic usage estimation, such as:
(see at least [0035]-[0037] of the instant specification). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mathematical Operations” grouping of abstract ideas. Accordingly, the claims recite an abstract idea under Prong 1 step 2A. Further, the claims do not recite any further additional elements and for the same reasons as above with regard to integration into a practical application and whether additional elements amount to significantly more, the claims also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as they have not been integrated into a practical application, and fail Step 2B as not amounting to significantly more. Therefore, claims 4, 11, and 18 do not recite patent eligible subject matter under 35 U.S.C. §101.
Regarding claim 5, it recites additional limitations of “trading off speed and area on a per block, per group of blocks, hierarchical, or global basis; and repeating the determining after at least one such trade-off”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper. For example, a person can mentally trade-off speed and area on a per block, per group of blocks, hierarchical, or global basis and mentally repeat the determining after the trade-off. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong 1 step 2A. Further, the claim does not recite any further additional elements and for the same reasons as above with regard to integration into a practical application and whether additional elements amount to significantly more, the claim also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as they have not been integrated into a practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 5 does not recite patent eligible subject matter under 35 U.S.C. §101.
Regarding claim 6, it recites additional limitations of “targeting congestion in the synthesized design; and repeating the determining, after a change to a targeted congestion”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper. For example, a person can mentally target congestion in the synthesized design and mentally repeat the determining after a change to a targeted congestion. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong 1 step 2A. Further, the claim does not recite any further additional elements and for the same reasons as above with regard to integration into a practical application and whether additional elements amount to significantly more, the claim also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as they have not been integrated into a practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 6 does not recite patent eligible subject matter under 35 U.S.C. §101.
Regarding claims 7 and 20, they recite additional limitations of “annotating a design database with synthesis directives to reduce logic used, reduce connectivity, trade-off speed and area, or reduce congestion, responsive to determining the synthesized design is not implementable on the specific FPGA”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper. For example, a person, with the use of pen and paper, can annotate a design database with synthesis directives to reduce logic used, reduce connectivity, trade-off speed and area, or reduce congestion, in response to mentally determining the synthesized design is not implementable on the specific FPGA. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claims recite an abstract idea under Prong 1 step 2A. Further, the claims do not recite any further additional elements and for the same reasons as above with regard to integration into a practical application and whether additional elements amount to significantly more, the claims also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as they have not been integrated into a practical application, and fail Step 2B as not amounting to significantly more. Therefore, claims 7 and 20 do not recite patent eligible subject matter under 35 U.S.C. §101.
Regarding claim 9, it recites additional limitations of “the determining comprises comparing the logic usage estimation and the logic capacity, and comparing the routability estimation and the routing capacity”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper. For example, a person can mentally compare the logic usage estimation to the logic capacity and compare the routability estimation to the routing capacity. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong 1 step 2A.
Further, regarding claim 9, it also recites additional element recitations of “wherein: the available resources of the specific FPGA comprise logic capacity and routing capacity; and the indicating to the user comprises a user interface” which is merely a recitation of a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Further, the claim does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, the claim also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 9 does not recite patent eligible subject matter under 35 U.S.C. §101.
Regarding claim 12, it recites additional limitations of “indicating to a user regarding trading off speed and area on a per block, per group of blocks, hierarchical, or global basis; and repeating the determining after at least one such trade-off”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper. For example, a person can mentally trade-off speed and area on a per block, per group of blocks, hierarchical, or global basis and, with the use of pen and paper, indicate to a user regarding such a trade-off. A person can also mentally repeat the determining after the trade-off. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong 1 step 2A. Further, the claim does not recite any further additional elements and for the same reasons as above with regard to integration into a practical application and whether additional elements amount to significantly more, the claim also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as they have not been integrated into a practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 12 does not recite patent eligible subject matter under 35 U.S.C. §101.
Regarding claim 13, it recites additional limitations of “indicating to a user regarding targeting congestion in the synthesized design; and repeating the determining, after a change to a targeted congestion”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper. For example, a person can mentally target congestion in the synthesized design and, with the use of pen and paper, indicate to the user regarding the targeted congestion. A person can also mentally repeat the determining after a change to a targeted congestion. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong 1 step 2A. Further, the claim does not recite any further additional elements and for the same reasons as above with regard to integration into a practical application and whether additional elements amount to significantly more, the claim also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as they have not been integrated into a practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 13 does not recite patent eligible subject matter under 35 U.S.C. §101.
Regarding claim 14, it recites additional limitations of “indicating to a user regarding annotating a design database with synthesis directives to reduce logic used, reduce connectivity, trade-off speed and area, or reduce congestion, responsive to determining the synthesized design is not implementable on the specific FPGA”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper. For example, a person, with the use of pen and paper, can indicate to a user regarding annotating a design database with synthesis directives to reduce logic used, reduce connectivity, trade-off speed and area, or reduce congestion, in response to mentally determining the synthesized design is not implementable on the specific FPGA. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong 1 step 2A. Further, the claim does not recite any further additional elements and for the same reasons as above with regard to integration into a practical application and whether additional elements amount to significantly more, the claim also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as they have not been integrated into a practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 14 does not recite patent eligible subject matter under 35 U.S.C. §101.
Regarding claim 19, it recites additional limitations of “target congestion in the synthesized design; trade off speed and area on a per block, per group of blocks, hierarchical, or global basis; and repeat such determining, after a change to a targeted congestion”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper. For example, a person can mentally target congestion in the synthesized design and mentally trade-off speed and area on a per block, per group of blocks, hierarchical, or global basis. A person can also mentally repeat the determining after a change to a targeted congestion. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with the use of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong 1 step 2A. Further, the claim does not recite any further additional elements and for the same reasons as above with regard to integration into a practical application and whether additional elements amount to significantly more, the claim also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as they have not been integrated into a practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 19 does not recite patent eligible subject matter under 35 U.S.C. §101.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8, 10, 11, 13, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (US PGPub 20150020038) (hereinafter “Feng”) in view of Tom et al. “Un/DoPack: Re-Clustering of Large System-on-Chip Designs with Interconnect Variation for Low-Cost FPGAs” ( “Tom”)
Independent claims share substantially similar limitations The analysis is performed for claim 1, with further analysis for additional elements for 8 and 15.
Regarding claim 1 representative for claims 8 and 15, Feng teaches
a method, performed by a computer aided design (CAD) system, comprising:
receiving a [[high level coding of a]] design for a circuit to be implemented in a field programmable gate array (FPGA) (([0007] A user design is typically implemented in a register-transfer level (RTL) language like Verilog or VHDL. A synthesis tool will synthesize the design into a netlist of basic logic elements appropriate for implementation in the FPGA.;
performing synthesis on the design, to produce a synthesized design ([0007] A user design is typically implemented in a register-transfer level (RTL) language like Verilog or VHDL. A synthesis tool will synthesize the design into a netlist of basic logic elements appropriate for implementation in the FPGA.);
generating a routability estimation and a logic usage estimation for the synthesized design, based on Rent's rule using parameters tuned to types of circuits in a specific FPGA; ([0018] The Rent characteristic of a netlist is the relation between the number of external terminals of a given subcircuit with the number of modules in the subcircuit. [0003] A cluster-based FPGA is made of an array of repeating clusters. A BLE (basic logic element) is composed of a LUT (look up table) and a FF (flip-flop) as shown in FIG. 1A. A cluster (or CLB, configuration logic block) is composed of multiple BLEs. An FPGA array is composed of multiple such CLBs. [0005] In reality, the logic element can contain types other than just simple LUTs and flip flops (for example, multiplexers, carry logic and so on; [0040] One difference between the present invention and some of the prior-art approaches discussed herein is that a recursive bipartitioner is used to obtain k-way partitions, where the k-way partitions are used to reconstruct the desired logic clusters to implement in the FPGA device. The k-way partitioning approach of the present invention based on recursive bipartitioning is shown below. By generating the partitions in this way, the Rent characteristic of the cluster-level netlist can be generally improved, thus improving routability and resulting in lower routing requirements.)
In Broadest Reasonable Interpretation Rent Rule interpreted as Rent characteristic; Rent characteristic is used for estimation and logic usage while the recursive bipartitioning is used to improve these values, which are reflected in an interpretation of the improved characteristic
Feng does not teach, however Tom teaches
determining whether the synthesized design is implementable on a specific FPGA, based on the routability estimation, the logic usage estimation, and available resources of the specific FPGA (Pages 680-681, Section 1 Introduction, Figure 1, and Section 3 UN/DO PACK CAD FLOW, The hard channel width constraint is targeted based on the routing capacity of the device and the array size constraint is the logic capacity, and decision blocks of the FPGA CAD flow in Figure 1 are used to determine whether the channel width and array size of the synthesized circuit fit within the respective constraints);
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the estimation of needed resources as taught by Feng with comparison of resources as taught by Tom to have the advantage of actually using the estimates in determining if design is implementable and not resulting in infeasible design. Accordingly the claim is unpatentable over Feng/Tom.
Claims 8 and 15 further recite a non-transitory computer-readable memory (CRM) that stores the instructions for the method and a respectively a computer system with a memory and a processor that executes the instructions of the method. Feng teaches a CAD flow “[0004] In the CAD (computer aided design) flow; [0023] typical computer aided design (CAD) process flow”. A POSITA would have understood the CAD functionality to be implemented by software stored on a conventional non-transitory CRM would have been understood by one of ordinary skill in the art to execute software stored in a CRM and a processes to execute these instructions. Therefore, Feng inherently teaches the memory and processor executing the CAD flow.
Regarding claim 2, Feng/Tom teach the limitations of the parent claim. Tom further teaches
wherein: the available resources of the specific FPGA comprise logic capacity and routing capacity ((Page 680, Abstract and Section 1 Introduction) Low-cost FPGA architectures have limited routing capacity which causes a hard channel width constraint that makes it difficult for CAD tools to successfully route a circuit into the low-cost devices, thus the FPGA CAD must meet the device routing capacity by targeting a hard channel width constraint; (Page 681, Figure 1 and Section 3 UN/DO PACK CAD FLOW) Thus as the hard channel width constraint (interconnect capacity) is meant to meet the device routing capacity and the array size constraint is the logic capacity of the FPGA, those are the available resources that the FPGA CAD flow is designed to meet);
and the determining comprises comparing the logic usage estimation and the logic capacity, and comparing the routability estimation and the routing capacity (Pages 680-681, Section 1 Introduction, Figure 1, and Section 3 UN/DO PACK CAD FLOW, The hard channel width constraint is targeted based on the device routing capacity and the array size constraint is the logic capacity, and decision blocks of Figure 1 are used to determine whether the channel width and array size of the circuit fit within the respective constraints).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the Feng/Tom’s teaching of estimation and validation of estimated resources with further teachings of Tom to have the advantage of verifying different components of the fit. Accordingly the claim is unpatentable over Feng/Tom.
Regarding claim 3, Feng/Tom teach the limitations of the parent claim. Tom further teaches
the method performed by the CAD system as recited in claim 1, wherein: the available resources of the specific FPGA comprise first logic elements (LEs) that are logic-only, second logic elements that are routing-only, and third logic elements that are usable for either of logic and routing (Pages 680-681, Section 1 Introduction and Section 2 Background and Related Work, The resources of the FPGA include configurable logic blocks (CLBs) which includes logic elements (LEs) such as flip-flops that could be considered logic only, however, empty LEs, or whitespace may be used to increase the number of routing channels and routing capacity of a region. The empty LEs may be considered routing-only, as they are added for routing purposes, and thus the CLBs can be considered logic elements that are usable for logic and routing);
and the determining comprises determining whether the logic usage estimation and the routability estimation fit within the combined first, second and third logic elements including a trade-off in usage of the logic and the routing of the third logic elements (Pages 681-683, Section 3 UN/DO PACK CAD FLOW, Section 3.1 UnPack: Congestion Calculator, and Section 3.2 DoPack: Incremental Re-Cluster, The presented FPGA CAD flow determines whether the channel width and array size meet their respective constraints, where the array size is based on the number of CLBs. Further, if the channel width exceeds the hard channel width constraint, then there may be a trade-off that causes more CLBs to be added which increases the array size, making it closer to the constraint, however, the increase in CLBs allows for empty LEs to depopulate a congested region and increase the routing channels).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the Feng/Tom’s teaching of estimation and validation of estimated resources with further teachings of Tom to have the advantage of verifying different components of the fit. Accordingly the claim is unpatentable over Feng/Tom.
Regarding claim 4, Feng/Tom teach the limitations of the parent claim. Feng further teaches wherein: the generating the routability estimation and the logic usage estimation are in accordance with Rent's rule regarding a relationship between a number of external signal connections to a logic block and a number of logic gates in the logic block ([0018], "The Rent characteristic of a netlist is the relation between the number of external terminals of a given subcircuit with the number of modules in the subcircuit" and ([0008]) the modules can include logic such as lookup tables and flip flops; ([0040]) K-way partitions are used to reconstruct logic clusters to implement in a FPGA device to improve the Rent characteristic, where an improvement in the Rent characteristic indicates improved routability and lower routing requirements; ([0033]) and Figure 3) Examples of Rent characteristic estimations are shown by R(1), R(2), and R(3) in Figure 3);
and the generating includes recursive bipartitioning of the synthesized design ([0040], A recursive bipartitioner is used to obtain the k-way partitions that are used to reconstruct logic clusters for improving the Rent characteristic, ([0029]-[0030], Figure 2 and Figure 4) where the partitioning happens after synthesis).
Regarding claim 5, Feng/Tom teach the limitations of the parent claim. Tom further teaches
further comprising: trading off speed and area on a per block, per group of blocks, hierarchical, or global basis (Page 682-683, Section 3.2 DoPack: Incremental Re-Cluster, In the re-clustering process, logic elements are packed into new CLB clusters, where good delay performance is desired; (Page 685, Section 5.1 Single Region Experimental Results) However, since the aim is a decrease in channel width, there may be a decrease in timing performance due to an increase in critical path delay, where there may also be an increase in the area of the circuit, so that the channel width constraint can be met);
and repeating the determining after at least one such trade-off (Page 681, Figure 1 and Section 3 UN/DO PACK CAD FLOW, After re-clustering, the FPGA CAD flow determines whether the channel width is withing the channel width constraint, while after the UnPack step, the CAD flow also determines whether the array size is within its constraint).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the Feng/Tom’s teaching of estimation and validation of estimated resources with further teachings of Tom to have the advantage of addressing/solving the fitting in case of estimates indicating a non-fit. Accordingly the claim is unpatentable over Feng/Tom.
Regarding claim 6, Feng/Tom teach the limitations of the parent claim. Tom further teaches
targeting congestion in the synthesized design (Page 681, Figure 1 and Section 3 UN/DO PACK CAD FLOW, The UnPack step determines which portion of the circuit is congested and fully unpacks the CLBs in this region, where the UnPack step occurs after synthetization);
and repeating the determining, after a change to a targeted congestion (Pages 681-682, Figure 1, Section 3 UN/DO PACK CAD FLOW and Section 3.1 UnPack: Congestion Calculator, Regions of congestion are identified and CLBs are added to create some depopulation in the region. After this is done, as shown in Figure 1, the array size and channel width are determined whether they are within their respective constraints. Further, as per the feedback arrow at the UnPack step in Figure 1, the process may be repeated if the channel width is found to not meet the hard channel width constraint).
Regarding claim 10, it is the article claim, having similar limitations of claim 3. Thus, claim 10 is also rejected under the similar rationale as cited in the rejection of claim 3.
Regarding claim 11, it is the article claim, having similar limitations of claim 4. Thus, claim 11 is also rejected under the similar rationale as cited in the rejection of claim 4.
Regarding claim 13 , Feng/Tom teach the limitations of the parent claim. Tom further teaches
wherein the method further comprises: indicating to a user regarding targeting congestion in the synthesized design (Page 681, Figure 1 and Section 3 UN/DO PACK CAD FLOW, The UnPack step determines which portion of the circuit is congested and fully unpacks the CLBs in this region, where the UnPack step occurs after synthetization; (Pages 681-682, Section 3.1 UnPack: Congestion Calculator and Figure 2) Further, a congestion map is generated as shown in Figure 2, which indicates areas of high and low congestion regions);
and repeating the determining, after a change to a targeted congestion (Pages 681-682, Figure 1, Section 3 UN/DO PACK CAD FLOW and Section 3.1 UnPack: Congestion Calculator, Regions of congestion are identified and CLBs are added to create some depopulation in the region. After this is done, as shown in Figure 1, the array size and channel width are determined whether they are within their respective constraints. Further, as per the feedback arrow at the UnPack step in Figure 1, the process may be repeated if the channel width is found to not meet the hard channel width constraint).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the Feng/Tom’s teaching of estimation and validation of estimated resources with further teachings of Tom to have the advantage of addressing the fitting in case of estimates indicating a non-fit. Accordingly the claim is unpatentable over Feng/Tom.
Regarding claim 16, it is the system claim, having similar limitations of claim 2. Thus, claim 16 is also rejected under the similar rationale as cited in the rejection of claim 2.
Regarding claim 17, it is the system claim, having similar limitations of claim 3. Thus, claim 17 is also rejected under the similar rationale as cited in the rejection of claim 3.
Regarding claim 18, it is the system claim, having similar limitations of claim 4. Thus, claim 18 is also rejected under the similar rationale as cited in the rejection of claim 4.
Regarding claim 19, Tom teaches the CAD system as recited in claim 15, further comprising the processor to: target congestion in the synthesized design (Page 681, Figure 1 and Section 3 UN/DO PACK CAD FLOW, The UnPack step determines which portion of the circuit is congested and fully unpacks the CLBs in this region, where the UnPack step occurs after synthetization);
trade off speed and area on a per block, per group of blocks, hierarchical, or global basis (Page 682-683, Section 3.2 DoPack: Incremental Re-Cluster, In the re-clustering process, logic elements are packed into new CLB clusters, where good delay performance is desired; (Page 685, Section 5.1 Single Region Experimental Results) However, since the aim is a decrease in channel width, there may be a decrease in timing performance due to an increase in critical path delay, where there may also be an increase in the area of the circuit, so that the channel width constraint can be met);
and repeat such determining, after a change to a targeted congestion (Pages 681-682, Figure 1, Section 3 UN/DO PACK CAD FLOW and Section 3.1 UnPack: Congestion Calculator, Regions of congestion are identified and CLBs are added to create some depopulation in the region. After this is done, as shown in Figure 1, the array size and channel width are determined whether they are within their respective constraints. Further, as per the feedback arrow at the UnPack step in Figure 1, the process may be repeated if the channel width is found to not meet the hard channel width constraint).
Regarding claim 20, it is the system claim, having similar limitations of claim 7. Thus, claim 20 is also rejected under the similar rationale as cited in the rejection of claim 7.
Claims 7, 9, 12, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (US PGPub 20150020038) (hereinafter “Feng”) in view of Tom et al. “Un/DoPack: Re-Clustering of Large System-on-Chip Designs with Interconnect Variation for Low-Cost FPGAs” ( “Tom”) in further of in view of Rostoker et al. (US Pat 5,557,531) (“Rostoker”)
Regarding claim 7 , Feng/Tom teach the limitations of the parent claim. Tom further teaches
further comprising: annotating [[a design database with synthesis]] directives to reduce logic used, reduce connectivity, trade-off speed and area, or reduce congestion, responsive to determining the synthesized design is not implementable on the specific FPGA (Page 682-683, Section 3.2 DoPack: Incremental Re-Cluster, The UnPack output provides a list of logic elements in each of the congested regions and the new cluster size for each region, as well as a list of already-packed CLBs, such that in the DoPack step, congestion-driven clustering can occur. (Pages 681, Figure 1 and Section 3 UN/DO PACK CAD FLOW) The UnPack step occurs in response to a routing solution that fails to meet the channel width constraint).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the Feng/Tom’s teaching of estimation and validation of estimated resources with further teachings of Tom to have the advantage of addressing the fitting in case of estimates indicating a non-fit through changes in allocation and resynthesis. Accordingly the claim is unpatentable over Feng/Tom.
Feng/Tom does not specifically teach, however Rostoker teaches
: annotating a design database with synthesis directives to reduce logic used, reduce connectivity, trade-off speed and area, or reduce congestion, responsive to determining the synthesized design is not implementable [[on the specific FPGA]] (Col. 11 lines 60-67, Wire delays of the synthesized design are back annotated into a design database, where if the timing characteristics do not meet the timing constraints, additional optimization is performed; (Col. 13 lines 35-42) Further, the annotation of wire delays are provided from the Modular Design Environment to the Design Compiler for necessary timing/area trade-off evaluations based on the delays and (Col. 13 lines 12-14) the Design Complier is used for synthesis and optimalization of the synthesized design; (Col. 48 lines 53-60) The design can be for an integrated circuit including a programmable logic device (PLD)).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the Feng/Tom’s teaching of estimation and validation of estimated resources with further teachings of Tom to have the advantage of addressing the fitting in case of estimates indicating a non-fit through changes in allocation and resynthesis. Accordingly the claim is unpatentable over Feng/Tom/Rostoker.
Regarding claim 9, Feng/Tom teach the limitations of the parent claim. Tom further teaches
wherein: the available resources of the specific FPGA comprise logic capacity and routing capacity (Page 680, Abstract and Section 1 Introduction) Low-cost FPGA architectures have limited routing capacity which causes a hard channel width constraint (interconnect capacity) that makes it difficult for CAD tools to successfully route a circuit into the low-cost devices, thus the FPGA CAD must meet the device routing capacity by targeting a hard channel width constraint; (Page 681, Figure 1 and Section 3 UN/DO PACK CAD FLOW) Thus as the hard channel width constraint is meant to meet the device routing capacity and the array size constraint is the logic capacity of the FPGA, those are the available resources that the FPGA CAD flow is designed to meet);
the determining comprises comparing the logic usage estimation and the logic capacity, and comparing the routability estimation and the routing capacity (Pages 680-681, Section 1 Introduction, Figure 1, and Section 3 UN/DO PACK CAD FLOW, The hard channel width constraint is targeted based on the device routing capacity and the array size constraint is the logic capacity, and decision blocks of Figure 1 are used to determine whether the channel width and array size of the circuit fit within the respective constraints).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the Feng/Tom’s teaching of estimation and validation of estimated resources with further teachings of Tom to have the advantage of verifying different components of the fit. Accordingly the claim is unpatentable over Feng/Tom.
Feng/Tom does not specifically teach, however Rostoker teaches the indicating to the user comprises a user interface (Col. 30 lines 63-69 Col. 31 lines 1-10, Figures 13-15 and Figures 17-18, The user interface 1802 in Figure 18 is connected to many function blocks including the partitioner and the estimator, where estimates, including of the area, are provided to the developer).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the Feng/Tom’s teaching of estimation and validation of fesibility of estimated resources with teachings of Rostoker of having an user interface to present this information to the user. Accordingly the claim is unpatentable over Feng/TomRostoker.
Regarding claim 12 Feng/Tom teach the limitations of the parent claim. Tom further teaches
wherein the method further comprises: [[indicating to a user regarding]] trading off speed and area on a per block, per group of blocks, hierarchical, or global basis (Page 682-683, Section 3.2 DoPack: Incremental Re-Cluster, In the re-clustering process, logic elements are packed into new CLB clusters, where good delay performance is desired; (Page 685, Section 5.1 Single Region Experimental Results) However, since the aim is a decrease in channel width, there may be a decrease in timing performance due to an increase in critical path delay, where there may also be an increase in the area of the circuit, so that the channel width constraint can be met);
and repeating the determining after at least one such trade-off (Page 681, Figure 1 and Section 3 UN/DO PACK CAD FLOW, After re-clustering, the FPGA CAD flow determines whether the channel width is withing the channel width constraint, while after the UnPack step, the CAD flow also determines whether the array size is within its constraint).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the Feng/Tom’s teaching of estimation and validation of estimated resources with further teachings of Tom to have the advantage of addressing the fitting in case of estimates indicating a non-fit. Accordingly the claim is unpatentable over Feng/Tom.
Feng/Tom does not specifically teach, however Rostoker teaches indicating to a user regarding trading off speed and area [[on a per block, per group of blocks, hierarchical, or global basis]] (Col. 13 lines 35-42, The Design Compiler provides constraint-driven optimization, including making necessary timing/area trade-off evaluations based on wire delays from the Modular Design Environment (MDE); (Col. 14 lines 30-65 and Figure 8) Further, the Co-Design Environment allows for the user to interact with the design process, and includes a graphical user interface, the MDE, and Design Complier Interface, which controls the data flow and interactions between the MDE and Design Complier and enables the user to follow the design process between environments and assists the user in the composition of the constraints file for optimization).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the Feng/Tom’s teaching of estimation and validation of estimated resources with further teachings of Tom to have the advantage of addressing the fitting in case of estimates indicating a non-fit. Accordingly the claim is unpatentable over Feng/Tom/Rostoker.
Regarding claim 14 , Feng/Tom teach the limitations of the parent claim. Tom further teaches
wherein the method further comprises: [[indicating to a user regarding]] annotating [[a design database with synthesis]] directives to reduce logic used, reduce connectivity, trade-off speed and area, or reduce congestion, responsive to determining the synthesized design is not implementable on the specific FPGA (Page 682-683, Section 3.2 DoPack: Incremental Re-Cluster, The UnPack output provides a list of logic elements (LEs) in each of the congested regions and the new cluster size for each region, as well as a list of already-packed CLBs, such that in the DoPack step, congestion-driven clustering can occur. (Pages 681, Figure 1 and Section 3 UN/DO PACK CAD FLOW) The UnPack step occurs in response to a routing solution that fails to meet the channel width constraint).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the Feng/Tom’s teaching of estimation and validation of estimated resources with further teachings of Tom to have the advantage of addressing the fitting in case of estimates indicating a non-fit by reducing the values that lead to higher estimates . Accordingly the claim is unpatentable over Feng/Tom.
Feng/Tom does not specifically teach, however Rostoker teaches wherein the method further comprises: indicating to a user regarding annotating a design database with synthesis directives to reduce logic used, reduce connectivity, trade-off speed and area, or reduce congestion, responsive to determining the synthesized design is not implementable [[on the specific FPGA]] (Col. 11 lines 60-67, Wire delays of the synthesized design are back annotated into a design database, where if the timing characteristics do not meet the timing constraints, further optimization is performed; (Col. 13 lines 35-42) Further, the annotation of wire delays is provided from the Modular Design Environment (MDE) to the Design Compiler for necessary timing/area trade-off evaluations based on the delays and (Col. 13 lines 12-14) the Design Complier is used for synthesis and optimalization of the synthesized design; (Col. 14 lines 30-65, Col. 15 lines 27-36, and Figure 8) The Co-Design Environment allows for the user to interact with the design process, and includes a graphical user interface, the Delay Back Annotator, the MDE, and Design Complier Interface, which controls the data flow and interactions between the MDE and Design Complier and enables the user to follow the design process between environments; (Col. 48 lines 53-60) where the design can be for an integrated circuit including a programmable logic device (PLD)).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the Feng/Tom’s teaching of estimation and validation of estimated resources with teachings of Rostoker to have the advantage of addressing the fitting in case of estimates indicating a non-fit by reducing the values that lead to higher estimates through indicating changes in synthesis instructions. Accordingly the claim is unpatentable over Feng/Tom/Rostoker.
Prior art made of record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hsu et al. (US PGPub 20160203254) teaches a method for reducing congestion in a synthesized integrated circuit design b that includes estimating the cell and routing resources of the design and the use of a user interface. The method identifies a congested region and may move a cell out of the congested region to reduce congestion in the design.
McElvain et al. (US PGPub 20040243964) teaches a method that includes identifying congestion in an area of an integrated circuit design and re-routing a net to avoid the congested area. The method also includes considering timing parameters when increasing the area of the circuit.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.S./Examiner, Art Unit 2188
/RYAN F PITARO/Supervisory Patent Examiner, Art Unit 2188
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