DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/11/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-9, 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Glass et al (US Publication No. 2020/0258982) in view of Wang et al (US Publication no. 2020/0058744) and Smith et al (US Publication No. 2021/098306).
Regarding claim 1, Glass discloses an integrated circuit structure, comprising: a plurality of horizontally stacked nanowires Fig 2N’, 275; a gate dielectric material layer Fig 2N’, 282 ¶0053 surrounding the plurality of horizontally stacked nanowires; a gate electrode structure Fig 2N’, 284 ¶0053 over the gate dielectric material layer Fig 2N’, 282 ¶0053; an epitaxial source or drain structure Fig 2N’, 262 at an end of the plurality of horizontally stacked nanowires ¶0041; and a conductive trench contact structure Fig 2N’, 290 vertically over the epitaxial source or drain structure. Glass discloses all the limitations but silent on the arrangement of the contact structure. Whereas Wang discloses a conductive trench contact structure Fig 22A-22B having a portion vertically over the epitaxial source or drain structure Fig 22A, 214/216 and a portion laterally spaced apart from the epitaxial source or drain structure Fig 22A, 214/216, the conductive trench contact structure electrically isolated from the epitaxial source or drain structure Fig 22B. Also, Smith discloses a conductive trench contact structure Fig 25, 269a having a first portion vertically over the epitaxial source or drain structure Fig 25 and a second portion laterally spaced apart from the epitaxial source or drain structure Fig 25, the second portion having a bottom surface below a top surface of the epitaxial source or drain structure Fig 25, the conductive trench contact structure electrically isolated from the epitaxial source or drain structure Fig 25. Glass, Wang and Smith are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify the contact structure because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact structure of Glass and incorporate the teachings of Wang or Smith to improve device performance and avoid contact resistance Wang-¶0013 and 0051.
Regarding claim 2, Wang discloses wherein the conductive trench contact structure is electrically isolated from the epitaxial source or drain structure by a dielectric structure Fig 22, 276.
Regarding claim 3, Wang in view of Glass discloses a second plurality of horizontally stacked nanowires; and a second epitaxial source or drain structure at an end of the second plurality of horizontally stacked nanowires, wherein the conductive trench contact structure is vertically over and electrically coupled to the second epitaxial source or drain structure Fig 22.
Regarding claim 4, Wang discloses a second conductive trench contact structure laterally spaced apart from the conductive trench contact structure by a dielectric plug Fig 22.
Regarding claim 6, Glass discloses an integrated circuit structure, comprising: a fin Fig 2N; a gate dielectric material layer Fig 2N, 282 ¶0053 surrounding the fin; a gate electrode structure Fig 2N, 284 ¶0053 over the gate dielectric material layer; an epitaxial source or drain structure Fig 2N, 262 at an end of the fin; and a conductive trench contact structure vertically over the epitaxial source or drain structure Fig 2N, 290. Glass discloses all the limitations but silent on the arrangement of the contact structure. Whereas Wang discloses a conductive trench contact structure Fig 22A-22B having a portion vertically over the epitaxial source or drain structure Fig 22A, 214/216 and a portion laterally spaced apart from the epitaxial source or drain structure Fig 22A, 214/216, the conductive trench contact structure electrically isolated from the epitaxial source or drain structure Fig 22B. Also, Smith discloses a conductive trench contact structure Fig 25, 269a having a first portion vertically over the epitaxial source or drain structure Fig 25 and a second portion laterally spaced apart from the epitaxial source or drain structure Fig 25, the second portion having a bottom surface below a top surface of the epitaxial source or drain structure Fig 25, the conductive trench contact structure electrically isolated from the epitaxial source or drain structure Fig 25. Glass, Wang and Smith are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify the contact structure because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact structure of Glass and incorporate the teachings of Wang or Smith to improve device performance and avoid contact resistance Wang-¶0013 and 0051.
Regarding claim 7, Wang discloses wherein the conductive trench contact structure is electrically isolated from the epitaxial source or drain structure by a dielectric structure Fig 22, 276.
Regarding claim 8, Wang in view of Glass discloses a second fin; and a second epitaxial source or drain structure at an end of the second fin, wherein the conductive trench contact structure is vertically over and electrically coupled to the second epitaxial source or drain structure Fig 22.
Regarding claim 9, Wang discloses a second conductive trench contact structure laterally spaced apart from the conductive trench contact structure by a dielectric plug Fig 22.
Regarding claim 11, Glass discloses a computing device Fig 4, comprising: a board Fig 4, 1002; and a component coupled to the board Fig 4, the component including an integrated circuit structure Fig 4, comprising: a plurality of horizontally stacked nanowires Fig 2N’, 275; a gate dielectric material layer Fig 2N’, 282 ¶0053 surrounding the plurality of horizontally stacked nanowires; a gate electrode structure Fig 2N’, 284 ¶0053 over the gate dielectric material layer Fig 2N’, 282 ¶0053; an epitaxial source or drain structure Fig 2N’, 262 at an end of the plurality of horizontally stacked nanowires ¶0041; and a conductive trench contact structure Fig 2N’, 290 vertically over the epitaxial source or drain structure. Glass discloses all the limitations but silent on the arrangement of the contact structure. Whereas Wang discloses a conductive trench contact structure Fig 22A-22B having a portion vertically over the epitaxial source or drain structure Fig 22A-22B, 214/216 and a portion laterally spaced apart from the epitaxial source or drain structure Fig 22A-22B, 214/216, the conductive trench contact structure electrically isolated from the epitaxial source or drain structure Fig 22B. Also, Smith discloses a conductive trench contact structure Fig 25, 269a having a first portion vertically over the epitaxial source or drain structure Fig 25 and a second portion laterally spaced apart from the epitaxial source or drain structure Fig 25, the second portion having a bottom surface below a top surface of the epitaxial source or drain structure Fig 25, the conductive trench contact structure electrically isolated from the epitaxial source or drain structure Fig 25. Glass, Wang and Smith are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify the contact structure because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact structure of Glass and incorporate the teachings of Wang or Smith to improve device performance and avoid contact resistance Wang-¶0013 and 0051.
Regarding claim 12, Glass discloses a memory coupled to the board Fig 4.
Regarding claim 13, Glass discloses a communication chip Fig 4, 1006 coupled to the board.
Regarding claim 14, Glass discloses wherein the component is a packaged integrated circuit die Fig 4.
Regarding claim 15, Glass discloses wherein the component is selected from the group consisting of a processor Fig 4, 1004, a communications chip Fig 4, 1006, and a digital signal processor ¶0067.
Regarding claim 16, Glass discloses a computing device Fig 4, comprising: a board Fig 4, 1002; and a component coupled to the board Fig 4, the component including an integrated circuit structure Fig 4, comprising: a fin Fig 2N; a gate dielectric material layer Fig 2N, 282 ¶0053 surrounding the fin; a gate electrode structure Fig 2N, 284 ¶0053 over the gate dielectric material layer; an epitaxial source or drain structure Fig 2N, 262 at an end of the fin; and a conductive trench contact structure vertically over the epitaxial source or drain structure Fig 2N, 290. Glass discloses all the limitations but silent on the arrangement of the contact structure. Whereas Wang discloses a conductive trench contact structure Fig 22A-22B having a portion vertically over the epitaxial source or drain structure Fig 22A-22B, 214/216 and a portion laterally spaced apart from the epitaxial source or drain structure Fig 22A-22B, 214/216, the conductive trench contact structure electrically isolated from the epitaxial source or drain structure Fig 22B. Also, Smith discloses a conductive trench contact structure Fig 25, 269a having a first portion vertically over the epitaxial source or drain structure Fig 25 and a second portion laterally spaced apart from the epitaxial source or drain structure Fig 25, the second portion having a bottom surface below a top surface of the epitaxial source or drain structure Fig 25, the conductive trench contact structure electrically isolated from the epitaxial source or drain structure Fig 25. Glass, Wang and Smith are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify the contact structure because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact structure of Glass and incorporate the teachings of Wang or Smith to improve device performance and avoid contact resistance Wang-¶0013 and 0051.
Regarding claim 17, Glass discloses a memory coupled to the board Fig 4.
Regarding claim 18, Glass discloses a communication chip Fig 4, 1006 coupled to the board.
Regarding claim 19, Glass discloses wherein the component is a packaged integrated circuit die Fig 4.
Regarding claim 20, Glass discloses wherein the component is selected from the group consisting of a processor Fig 4, 1004, a communications chip Fig 4, 1006, and a digital signal processor ¶0067.
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Glass et al (US Publication No. 2020/0258982), Wang et al (US Publication no. 2020/0058744) and Smith et al (US Publication No. 2021/098306) and in further view of Rubin et al (US Publication No. 2020/0135646).
Regarding claims 5 and 10, Glass and Wang disclose all the limitation but silent on the conductive via bar. Whereas Rubin discloses a conductive via bar vertically beneath and electrically coupled to the second conductive trench contact structure Fig and Fig 10 ¶0077. Glass and Rubin are analogous art because they are directed to integrated circuit and one of ordinary skill in the art would have had a reasonable expectation of success to modify the contact structure because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Glass and incorporate the teachings of Rubin to improve device performance and avoid contact resistance ¶0077.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811