DETAILED ACTION
Statement of claims
The present amended application includes:
Claims 1, 6, 8, 15-23 were amended.
Claims 1-26 remain pending in the application. Claims 1-26 are being considered on the merits.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 22, 2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Rejections Under 35 U.S.C. § 103
Applicant argues that:
“Applicant respectfully submits that the combination of Aswathnarayan, Nicol, and Laplante fails to teach or suggest claim 1 as amended herein. Claim 1 has been amended to recite "in response to an application programming interface (API) call, cause a wait operation of a queue to wait until a first count value of a timeline semaphore generated by another API meets a threshold value to cause one or more subsequent operations of the queue to be performed, an indication of the timeline semaphore having been received from the other API." The combination of references fails to teach or suggest at least these features of claim 1." .
Applicant’s arguments have been considered but are moot in view of new ground rejection based on Ashwathnarayan et al. (US 2020/0364088) in view of Turner at al. (US 6, 505,229)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-26 are rejected under 35 U.S.C. 103 as being unpatentable over Ashwathnarayan et al. (US 2020/0364088, Aswathnarayan hereinafter) in view of Turner at al. (US 6, 505,229, Turner hereinafter).
As to claim 1, Ashwathnarayan teaches One or more processors (e.g., see abstract, “a processor comprises one or more circuits to allocate memory to at least two heterogeneous processing cores in response to performing one or more instructions associated with one or more application programming interfaces based, at least in part, on one or more attributes associated with the at least two heterogeneous processing cores.“) comprising: circuitry to in response to an application programming interface (API) call to cause (e.g., “application programming interface model stream” represent the API) a wait operation of a queue to wait until a first count value (e.g., “waits until value ” in para 120) of a timeline semaphore computing platform and application programming interface model external semaphores and parallel computing platform and application programming interface model streams are enhanced using techniques described herein. In at least one embodiment, a parallel computing platform and application programming interface model stream can wait and signal synchronization object by treating it as a type of external semaphore. In at least one embodiment, parallel computing platform and application programming interface model stream is able to wait for tasks running on a plurality of hardware engines. )
[0120] In at least one embodiment, if a semaphore object is type
_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D12_FENCE, then waiting on a semaphore waits until value of semaphore is greater than or equal to _EXTERNAL_SEMAPHORE_PARAMS::params::fence::value.”.) .
However, Ashawathnarayan does not explicitly teach the timeline semaphore generated by another API meets the threshold value to cause one or more subsequent operations of the queue to be performed, an indication of the timeline semaphore having been received from the other API.
Turner teaches the timeline semaphore generated by another API meets the threshold value to cause one or more subsequent operations of the queue to be performed, an indication of the timeline semaphore having been received from the other API (e.g., see FIG. 3a and 3B, col. 7, line 65-67 and col. 8, lines 1-33, “threads may create other threads. The owner or parent thread can also destroy any thread that it created. “, “The owner thread can assign a maximum time-slice to its children threads equal to its own maximum time-slice, but no larger”, “An owner thread can restrict a child thread's time-slice to a value smaller than its own maximum, too.”, “thread A creates a child thread C (85), which is placed on the bottom of the Ready queue (81) by the OS (90) at time=t.sub.9. At time=t.sub.10, thread A exceeds its maximum time-slice, is placed on the bottom of the Ready queue, thread B is allowed to execute on the processor, and child thread C (85) is advanced to the next pending position in the Ready queue by the operating system”
Thus, the “thread” represents the API call , the “thread can assign a maximum time-slice” include “ timeline semaphore generated by another API”. Therefore , the timeline semaphore generated by another API meets the threshold value to cause one or more subsequent operations of the queue to be performed, an indication of the timeline semaphore having been received from the other API).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ashawathnarayan by adopting the teachings of Turner in order to provide “ flexible interprocess communications mechanisms enabling multiple processes within a single processor or among a plurality of processors to communicate with one another.” (see Turner, col. 2, lines 54-58)
As to claim 2, Ashawathnarayan does not teach wherein the other API created the timeline semaphore, and wherein to wait further comprises reading a reference to the timeline semaphore that indicates to wait until a parameter of the timeline semaphore reaches or exceeds a threshold. However, Turner teaches wherein the other API created the timeline semaphore, and wherein to wait further comprises reading a reference to the timeline semaphore that indicates to wait until a parameter of the timeline semaphore reaches or exceeds a threshold (e.g., see FIG. 3a, col. 7, lines 3-35, The variable time-slice classification is determined upon thread creation” , “ FIG. 3a, the event on which thread C (85) is waiting is shown occurring, and thread C is moved to the bottom of the Ready queue (81). Subsequently, thread A (83) executes until its pre-defined maximum execution time expires at time=t.sub.3, and thread A (83) is moved to the bottom of the Ready queue (81). This allows thread B (84) to be executed on the processor (80), and thread C (84) advances to the next pending position in the Ready queue (81). “). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ashawathnarayan by adopting the teachings of Turner in order to provide “ flexible interprocess communications mechanisms enabling multiple processes within a single processor or among a plurality of processors to communicate with one another.” (see Turner, col. 2, lines 54-58)
As to claim 3, Ashawathnarayan teaches wherein to wait refers to a stream waiting until the first count value reaches or exceeds a threshold value (e.g., para [0120] In at least one embodiment, if a semaphore object is type _EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D12_FENCE, then waiting on a semaphore waits until value of semaphore is greater than or equal to _EXTERNAL_SEMAPHORE_PARAMS::params::fence::value. ).
As to claim 4., Ashawathnarayan does not teach wherein the other API created the timeline semaphore, wherein the other API exported a handle of the timeline semaphore, wherein the handle corresponds to a shared memory location of the timeline semaphore, wherein to wait is to include reading a parameter of the timeline semaphore based on the handle, and wherein to wait includes waiting until the timeline semaphore reaches or exceeds a threshold value. However, Turner teaches wherein the other API created the timeline semaphore, wherein the other API exported a handle of the timeline semaphore, wherein the handle corresponds to a shared memory location of the timeline semaphore. (e.g., see abstract, wherein “threads may share the processing bandwidth and system resources cooperatively and efficiently, with minimized coupling of the application threads to each other and system resource control details.”), wherein to wait is to include reading a parameter of the timeline semaphore based on the handle, and wherein to wait includes waiting until the timeline semaphore reaches or exceeds a threshold value (e.g., col. 9, lines 1-20 wherein “synchronization elements such as semaphores, and the like. Upon this request, the system's resource allocation (91) function is invoked, wherein available resources are allocated or locked to the requesting thread (96) for the duration of the life of the thread (96). The thread then executes, passing through periods of execution (93) and suspension (92), shown by the continuation of time at time=t.sub.21 on the time bar (97). Upon conclusion of the processing necessary by the thread, the thread requests termination (94), shown at time=t.sub.22 on the time bar (97), which invokes the system's automatic resource reclamation (95). The resource reclamation function (95) releases all of the system resources which had been allocated or locked to the thread, and places them back into a pool of available resources for other threads to request”). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ashawathnarayan by adopting the teachings of Turner in order to provide “ flexible interprocess communications mechanisms enabling multiple processes within a single processor or among a plurality of processors to communicate with one another.” (see Turner, col. 2, lines 54-58).
As to claim 5, Ashawathnarayan teaches wherein the first count value corresponds to a monotonically increasing integer (e.g., para [0580] synchronization primitives are supported, such as semaphores and syncpoints. In at least one embodiment, UMD waiter sets w_caps to {primitive={semaphore, syncpoint}count={5, 0}} and provides such information to app waiter in any suitable manner. In at least one embodiment, an AttributeList is returned by UMD waiter to app waiter. In at least one embodiment, app waiter sends w_caps to app signaler as AttributeList. In at least one embodiment, signaler sets up a shared fence buffer that is to include fences. In at least one embodiment, app signaler calls GetDeviceCapabilities (&s_caps) to obtain a set of signaler capabilities. In at least one embodiment, UMD signaler fulfills calls to GetDeviceCapabilities( ). In at least one embodiment, UMD sets s_caps to indicate a set of supported primitives. In at least one embodiment, s_caps indicates parameters of supported primitives, for example, max count of a semaphore. In at least one embodiment, UMD signaler sets s_caps {primitive={semaphore, syncpoint}count={5, 0}} and returns s_caps as an AttributeList to app signaler., Thus, the “count={5, 0} include monotonically increasing integer ).
As to claim 6, , Ashawathnarayan does not explicitly teach wherein to wait on the timeline semaphore includes at least two streams waiting on a same timeline semaphore, wherein the at least two streams are performed or to be performed by the circuitry one or more circuits. However, Turner teaches wherein to wait on the timeline semaphore includes at least two streams waiting on a same timeline semaphore, wherein the at least two streams are performed or to be performed by the circuitry one or more circuits. (see Figure 3B). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ashawathnarayan by adopting the teachings of Turner in order to provide “ flexible interprocess communications mechanisms enabling multiple processes within a single processor or among a plurality of processors to communicate with one another.” (see Turner, col. 2, lines 54-58)
As to claim 7, Ashawathnarayan does not explicitly teach wherein to wait on the timeline semaphore includes a timeline semaphore reaching a maximum count value, wherein the maximum count value indicates the timeline semaphore has timed out. However, Turner teaches herein to wait on the timeline semaphore includes a timeline semaphore reaching a maximum count value, wherein the maximum count value indicates the timeline semaphore has timed out ( e.g., see col. 7, lines 30-37, “Subsequently, thread A (83) executes until its pre-defined maximum execution time expires at time=t.sub.3, and thread A (83) is moved to the bottom of the Ready queue (81). “).Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ashawathnarayan by adopting the teachings of Turner in order to provide “ flexible interprocess communications mechanisms enabling multiple processes within a single processor or among a plurality of processors to communicate with one another.” (see Turner, col. 2, lines 54-58).
As to claim 8, see rejection of claim 1 above. Ashawathnarayan teaches further A system, comprising memory to store instructions that, as a result of execution by one or more processors, cause the system (e.g., para [0498] In at least one embodiment, graphics processor 3600 or a component thereof executes computer-readable instructions to allocate memory to at least two heterogeneous processing cores in response to performing one or more instructions associated with one or more application programming interfaces (APIs) based, at least in part, on one or more attributes associated with the at least two heterogeneous processing cores. In at least one embodiment, graphics processor 3600 utilizes computing resources (e.g., CPUs, ASICs, GPUs, FPGAs) to implement inferencing and/or training logic 1515 to perform inferencing and/or training operations associated with one or more embodiments. Graphics processor 3600 may be utilized to implement one or more embodiments described elsewhere in this disclosure, such as those described in connection with FIGS. 1-35 and 37-43.).
As to claims 9, see rejection of claim 2 above.
As to claims 10-14, see rejection of claim 3-7 above.
As to claim 15, see rejection of claim 1 above. Ashawathnarayan teaches further non transitory machine-readable medium having stored thereon one or more instructions, which if performed by one or more processors, cause one or more processors to at least(e.g., para [0498] In at least one embodiment, graphics processor 3600 or a component thereof executes computer-readable instructions to allocate memory to at least two heterogeneous processing cores in response to performing one or more instructions associated with one or more application programming interfaces (APIs) based, at least in part, on one or more attributes associated with the at least two heterogeneous processing cores. In at least one embodiment, graphics processor 3600 utilizes computing resources (e.g., CPUs, ASICs, GPUs, FPGAs) to implement inferencing and/or training logic 1515 to perform inferencing and/or training operations associated with one or more embodiments. Graphics processor 3600 may be utilized to implement one or more embodiments described elsewhere in this disclosure, such as those described in connection with FIGS. 1-35 and 37-43.).
As to claim 16-17, see rejection of claims 2-3 above.
As to claim 18, see rejection of claim 4 above.
As to claim 19-20, see rejection of claims 5-6 above.
As to claim 21, Ashawathnarayan teaches wherein to wait on the timeline semaphore includes one or more streams signaling the timeline semaphore to add another wait (e.g., para [115] multiple waits on same SciSyncFence can be enqueued in different threads and process and on different hardware engines, which may be possible because SciSyncFence can be passed-by-value across software boundaries.) or increase a wait time.
As to claims 22-25, see rejection of claims 1-4 above.
As to claim 26, Ashawathnarayan does not teach wherein the API corresponds to a first software library, the another API corresponds to a second software library, and a portion of a workload corresponding to the second library waits for a portion of a workload corresponding to the first library based, at least in part on, the timeline semaphore. However, Turner teaches wherein the API corresponds to a first software library, the another API corresponds to a second software library, and a portion of a workload corresponding to the second library waits for a portion of a workload corresponding to the first library based, at least in part on, the timeline semaphore (e.g., Figure 3B, “timeline (86),” for “ a variety of application threads may share the processing bandwidth and system resources cooperatively and efficiently” in abstract. Thus, wherein the API corresponds to a first software library, the another API corresponds to a second software library, and a portion of a workload corresponding to the second library waits for a portion of a workload corresponding to the first library based, at least in part on, the timeline semaphore ). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ashawathnarayan by adopting the teachings of Turner in order to provide “ flexible interprocess communications mechanisms enabling multiple processes within a single processor or among a plurality of processors to communicate with one another.” (see Turner, col. 2, lines 54-58)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDOU K SEYE whose telephone number is (571)270-1062. The examiner can normally be reached M-F 9-5:30.
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/ABDOU K SEYE/Examiner, Art Unit 2198
/TUAN C DAO/Primary Examiner, Art Unit 2198
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