Prosecution Insights
Last updated: April 19, 2026
Application No. 17/549,427

LIQUID METAL CONNECTION DEVICE AND METHOD

Non-Final OA §103
Filed
Dec 13, 2021
Examiner
YAP, DOUGLAS ANTHONY
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
3 (Non-Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
3y 3m
To Grant
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
43 granted / 49 resolved
+19.8% vs TC avg
Moderate +12% lift
Without
With
+12.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
48 currently pending
Career history
97
Total Applications
across all art units

Statute-Specific Performance

§103
50.9%
+10.9% vs TC avg
§102
25.2%
-14.8% vs TC avg
§112
21.2%
-18.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 49 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03 November 2025 has been entered. Response to Arguments Applicant’s arguments, see Remarks, filed 03 November 2025, with respect to claims 1 and 9 have been fully considered and are persuasive. The 35 USC § 102 rejection of claim 9 and the 35 USC § 103 rejection of claim 1 has been withdrawn. However, upon further search and considerations, claims 1 and 9 are rejected under 35 USC § 103 over Tuli in view of Hirai and Liu. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: Determining the scope and contents of the prior art. Ascertaining the differences between the prior art and the claims at issue. Resolving the level of ordinary skill in the pertinent art. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1, 3, 6, 8-9, 12, 23-25 and 27-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tuli (US 2009/0001576 A1) in view of Hirai (NPL: Fabrication of Porous Polyimide Membrane with Through‐Hole via Multiple Solvent Displacement Method) and Liu (US 2004/0009686 A1). Regarding claim 1, Tuli teaches an electronic interconnect socket (120&110; see Fig. 1, [0011] or alternatively, 320&310 in Fig. 3 and [0020]), comprising: an array of pins ( 114; Fig. 1 & [0011]; alternatively, 312 in Fig. 3 & [0019]) on a first surface (pins 114/312 are found towards the bottom surface of 120&110/320&310), the pins having a pin cross section dimension (diameter of pins along the horizontal axis; as shown in Figs. 1 & 3, pins 114/312 have a cylindrical shape with pointed tips); an array of liquid metal filled reservoirs ( 122; ¶ [0012]; alternatively, 322 in Fig. 3 & [0020]) on a second surface (122/322 are found towards the top surface of 120&110/320&310); and a cap layer ( 126; ¶ [0013]; alternatively, 326 in Fig. 3 & [0020]; plain meaning: 126/326 are sealing films used to cover the reservoirs 126/322; hence 126/32 is a cap layer) including a resilient material ([0013]: 126 made of polymers such as polyimide or silicone) covering the array of liquid metal filled reservoirs (as shown in Fig. 1 & 3, 126/326 covers 122/322). However, Tuli does not explicitly teach the resilient material to be porous and the pores have curvilinear cross sections in a plane perpendicular to the pin cross section. Hirai, in the same field of invention, teaches a resilient material (polyimide PI) to be a porous polymer (see abstract: porous PI membranes with through-holes) and the pores have curvilinear cross sections (see curvilinear holes in PI membrane in Fig. 1) in a plane (in view with Tuli, this is the vertical plane of Tuli Fig. 3) perpendicular to the pin cross section. A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Hirai into the electronic device of Tuli to use a porous polymer that has pores that have curvilinear cross sections. The ordinary artisan would have been motivated to modify Tuli in the manner set forth above for at least the purpose of enabling the air permeability of the polymer without compromising its water resistance due to the presence of through-hole pores (Page 357: “PI membranes fabricated with 3‐stages immersion showed air‐permeability from the clear through‐holes in all cases except water”) and for enhancing the thermal properties of the polymer (Page 357: “fabricated PI membranes possessed high thermal properties and excellent thermal stability at high temperatures”), thus ensuring efficient heat transfer of the electronic device to the ambient air, due to the air permeability of the polymer, and ensuring its waterproofness. Tuli further teaches inserting the array of pins through the resilient material of the cap layer, hence resulting in additional pores (i.e., holes) created in the resilient material due to the insertion (¶ [0015], [0021]). However, Tuli in view of Hirai does not teach the electronic interconnect socket wherein these pores in the porous resilient material have a diameter larger than the pin cross section dimension. Liu, in the same field of invention, teaches an electronic interconnect socket (100; [0004]) comprising of pins (40) inserted through a resilient material ([0021]: 50 made of polymer), wherein the pores (Figs 1-2: holes in 50 accommodating 40) in the porous resilient material have a diameter (diameter of a hole in 50) larger than the pin cross section dimension (diameter of 40). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Liu into the electronic device of Tuli in view of Hirai to have at least a portion of the pores in the porous polymer having a diameter larger than the pin cross section dimension. The ordinary artisan would have been motivated to modify Tuli in the manner set forth above for using the larger diameter of the pores of the porous polymer at least for the purpose of ensuring proper electrical connection of each individual pin in the array of pins of the device of Tuli in view of Hirai to its corresponding liquid metal filled reservoir (Liu Abstract), so that the electrical signals can be routed between the semiconductor die and the package substrate (110 or 310, see Tuli Figs.1 & 3). Regarding claim 3, the electronic interconnect socket of claim 1, wherein the cap layer is formed from a continuous porous resilient material (plain meaning: as shown in Tuli Fig. 1, 126 is continuous with no breaks or gaps or made of different sections/regions/areas; hence Tuli teaches cap layer formed from a continuous porous resilient material). Regarding claim 6, the electronic interconnect socket of claim 1, further including an adhesive layer (Tuli Figs. 1 & 3, [0023]: “adhesive such as epoxy resin may be used to attach the lower sealing film 326 to the spacer 320”; alternatively [0013]: “the lower sealing film 126 may comprise a sticky tape… the lower sealing film 126 may be attached or stuck to the spacer 120 to improve sealing strength” ) between the cap layer and the array of liquid metal filled reservoirs (as explained in Tuli [0023], [0013], adhesive layer is between 122 and 126 in Fig. 1 or between 322 and 326 in Fig. 3 ). Regarding claim 8, the electronic interconnect socket of claim 1, wherein the liquid metal includes gallium (Tuli ¶ [0012]). Regarding claim 9, Tuli teaches an electronic device (300; Fig. 3, [0019]), comprising: a semiconductor die (340) coupled to a first side (top side of 330) of a substrate (330); an electronic interconnect socket (320&310, see [0020]) on a second side (bottom side of 330) of the substrate 330, the electronic interconnect socket comprising; an array of pins ( 312) on a first surface (312 located towards the bottom surface of 320&310), the pins having a pin cross section dimension (cross-sectional diameter of each pin taken along the horizontal axis of the figure); an array of liquid metal filled reservoirs (322, see [0020]) on a second surface (322 located towards the top surface of 320&310); and a cap layer (326; [0020]: 326 is a lower sealing film used to seal the liquid metal in 322; hence 326 is a cap layer) including a porous (plain meaning of porous from Merriam-Webster dictionary: capable of being penetrated; as shown in Fig. 3, 326 is porous since it is capable of being penetrated by pins ) material ([0013]: lower sealing film made of polymers such as polyimide or silicone) covering the array of liquid metal filled reservoirs (as shown in Fig. 3, 326 covers the bottom surfaces of 322), wherein the porous material comprises a polymer ([0013]: polyimide or silicone). However, Tuli does not explicitly teach the polymer to be a porous polymer. Hirai, in the same field of invention, teaches a polymer (polyimide) to be a porous polymer (see abstract). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Hirai into the electronic device of Tuli to use a porous polymer. The ordinary artisan would have been motivated to modify Tuli in the manner set forth above for at least the purpose of enabling the air permeability of the polymer without compromising its water resistance due to the presence of through-hole pores (Page 357: “PI membranes fabricated with 3‐stages immersion showed air‐permeability from the clear through‐holes in all cases except water”) and for enhancing the thermal properties of the polymer (Page 357: “fabricated PI membranes possessed high thermal properties and excellent thermal stability at high temperatures”), thus ensuring sufficient heat transfer of the electronic device to the ambient air, due to the air permeability of the polymer, and ensuring its waterproofness. Tuli further teaches inserting the array of pins through the resilient material of the cap layer, hence resulting in additional pores (i.e., holes) created in the resilient material due to the insertion (¶ [0015], [0021]). However, Tuli in view of Hirai does not teach the electronic device wherein at least a portion of these pores in the porous polymer having a diameter larger than the pin cross section dimension. Liu, in the same field of invention, teaches an electronic device (socket 100; [0004]) comprising of pins (40) inserted through a resilient material ([0021]: 50 made of polymer), wherein at least a portion (cross-section of each hole in 50) of the pores (holes in 50 accommodating 40) in the porous polymer having a diameter larger (step 520, see Fig. 5 and [0031]) than the pin cross section dimension (cross-sectional diameter of pins 40, with the cross section taken along the horizontal axis of Fig. 2). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Liu into the electronic device of Tuli in view of Hirai to have at least a portion of the pores in the porous polymer having a diameter larger than the pin cross section dimension. The ordinary artisan would have been motivated to modify Tuli in view of Hirai in the manner set forth above for using the larger diameter of the pores of the porous polymer at least for the purpose of ensuring proper electrical connection of each individual pin in the array of pins of the device of Tuli to its corresponding liquid metal filled reservoir (Liu Abstract), so that the electrical signals can be routed between the semiconductor die and the package substrate (210, see Tuli Fig. 3). Regarding claim 12, the electronic device of claim 9, further comprising a moisture barrier layer on lateral edges of the cap layer (Tuli [0023]: “an adhesive such as epoxy resin may be used to attach the lower sealing film 326 to the spacer 320”; epoxy resin are known in the art as moisture barriers; since attaching 326 to 320 with a resin requires applying the resin to the horizontal surface of 326, then Tuli teaches the resin is on the lateral edges of the cap layer). Regarding claim 23, the electronic interconnect socket of claim 1, wherein the pores have elliptical, ovoidal, or spherical cross sections (see Hirai Fig. 1). Regarding claim 24, the electronic interconnect socket of claim 1, wherein at least a portion of the pores are not aligned with the pins (see Hirai Fig. 1 whereby irregularly-shaped pores are disposed in a random pattern throughout the polyimide material). Regarding claim 25, Tuli teaches the electronic device of claim 9 but does not teach: wherein the porous material comprises pores having curvilinear cross-sections in a cross-section (vertical cross-section of Tuli Fig. 3) through the semiconductor die and the substrate (see Hirai Fig. 1 whereby irregularly-shaped curvilinear pores are disposed in a random pattern throughout the polyimide material). Regarding claim 27, the electronic device of claim 9, wherein the porous material comprises pores that are not aligned with the pins (see Hirai Fig. 1 whereby irregularly-shaped pores are disposed in a random pattern throughout the polyimide material). Regarding claim 28, the electronic interconnect socket of claim 1, wherein the porous resilient material comprises a polymer (Hirai Introduction: “Polyimide (PI) is a polymeric material…”). Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Tuli (US 2009/0001576 A1) in view of Hirai (NPL: Fabrication of Porous Polyimide Membrane with Through‐Hole via Multiple Solvent Displacement Method) and Liu (US 2004/0009686 A1) as applied to claim 1 above, and further in view of Seo (US 2006/0163689 A1). Regarding claim 2,Tuli in view of Hirai and Liu teaches the electronic interconnect socket of claim 1, but does not teach: wherein a strain relief pattern in the porous resilient material. Seo, in the same field of invention, teaches a semiconductor device ([0004]) comprising of a strain relief pattern (Figs. 8A-8C, [0072]: 32 & 34 & 36) in the porous resilient material (Figs. 8A-8C, [0070]: 30a&30b&30c: polyimide; see also [0007], [0012]-[0013], [0018], [0029]). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to add a strain relief pattern in the porous resilient material. The ordinary artisan would have been motivated to modify Tuli in view of Hirai and Liu in the manner set forth above for at least the purpose of reducing warpage of the electronic interconnect socket (Seo Abstract, [0006]-[0007], [0011]-[0015], [0030]). Claims 4-5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Tuli (US 2009/0001576 A1) in view of Hirai (NPL: Fabrication of Porous Polyimide Membrane with Through‐Hole via Multiple Solvent Displacement Method) and Liu (US 2004/0009686 A1) as applied to claims 1 and/or 9 above, and further in view of Sauciuc (US 2009/0273083 A1). Regarding claim 4, Tuli in view of Hirai and Liu teaches the electronic interconnect socket of claim 1, but does not teach the cap layer includes a continuous solid portion with isolated resilient material regions corresponding to the array of liquid metal filled reservoirs. Sauciuc, in the same field of invention, teaches a socket (400; Figs. 4A-4B, 5-7; [0038], [0008]-[0011]) wherein the cap layer (410) includes a continuous solid portion (412; as shown in Figs. 4A-4B, 412 is a portion of 410 not having 450) with isolated regions (450; see [0038]) corresponding to the array of liquid metal filled reservoirs (465; see [0043]: liquid metal 470 disposed in 465). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sauciuc into the device of Tuli in view of Hirai and Liu by modifying the cap layer to include a continuous solid portion with isolated resilient material regions corresponding to the array of liquid metal filled reservoirs. The ordinary artisan would have been motivated to modify Tuli in view of Hirai and Liu in the manner set forth above for at least the purpose of using the modified cap layer as critical component of an assembly (500, see Sauciuc Fig. 5 and [0045], [0009]) that has a moisture barrier layer ( 240, see Figs. 6-7, [0048]) that retains the liquid metal in the reservoir and/or to reduces the leakage of the metallic liquid to other interconnects during transportation of the device (Sauciuc [0021], [0026], and [0036]) and that can compensate for non-planarities (warpage, different thermal expansion) and/or misalignment of the critical elements of the package (Sauciuc [0047]). Regarding claim 5, Tuli in view of Hirai and Liu teaches the electronic interconnect socket of claim 1 but does not teach a continuous moisture barrier layer over the cap layer. Sauciuc, in the same field of invention, teaches a device (200; see Fig. 2, [0027]) wherein a continuous moisture barrier layer (240; [0036]: made of polymers such as rubber, which is known in the art to contain moisture) over the cap layer ( 160; [0019]: 160 is analogous to Tuli’s cap layer since it retains the liquid metal 170 within the reservoir 165). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sauciuc into the device of Tuli in view of Hirai and Liu to add a continuous moisture barrier layer over a cap layer. The ordinary artisan would have been motivated to modify Tuli in view of Hirai and Liu in the manner set forth above for at least the purpose of using the moisture barrier layer to retain the liquid metal in the reservoir and/or to prevent leakage of the liquid to other interconnects during transportation of the device (Sauciuc [0021], [0026]). Regarding claim 10, Tuli in view of Hirai and Liu teaches the electronic device of claim 9 but does not teach: further comprising an opposing porous material located on the first surface, the cap layer in contact with the opposing porous material. Sauciuc, in the same field of invention, teaches an electronic device (200, see Figs. 5-7, [0027]) further comprising an opposing porous material (240 is located vertically opposite of 460; also see [0036]: 240 is made of a polymer material such as a sponge-like rubber) located on the first surface (top surface of 160), the cap layer ( 160; [0019]: 160 is analogous to Tuli’s cap layer since it retains the liquid metal 170 within the reservoir 165) in contact with the opposing porous material (Fig. 3 shows 160 in contact with 240). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sauciuc into the device of Tuli add an opposing porous material located on the first surface, with the cap layer in contact with the opposing porous material. The ordinary artisan would have been motivated to modify Tuli in the manner set forth above for at least the purpose of using the opposing porous resilient material to retain the liquid metal in the reservoir and/or to prevent leakage of the liquid to other interconnects during transportation of the device (Sauciuc [0021], [0026]). Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tuli (US 2009/0001576 A1) in view of Hirai (NPL: Fabrication of Porous Polyimide Membrane with Through‐Hole via Multiple Solvent Displacement Method), Liu (US 2004/0009686 A1), and Sauciuc (US 2009/0273083 A1), as applied to claim 10 above, and further in view of Messina (US 2005/0037640 A1). Regarding claim 11, Tuli in view of Hirai, Liu, and Sauciuc teaches electronic device of claim 10 but does not teach, wherein the opposing porous material includes a closed cell porous material. Messina, in the same field of invention, teaches a semiconductor device wherein the opposing porous material includes a closed cell porous material ([0023]: “The gasket 60 may be formed from a variety of materials including butyl, urethane, or silicone rubber materials; filter materials; porous, closed cell foams…,” emphasis added). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to substitute materials that are recognized in the art as equivalent to one another, specifically substituting the rubber that comprises the opposing porous resilient material of Sauciuc with a porous closed cell foam of Messina to obtain an equivalent purpose and/or to obtain a predictable result, which is to prevent seepage of the metallic fluid from leakage out of the cavity and to protect against external contamination and debris (Messina [0004]-[0008]). See MPEP § 2143 (I) (B) and § 2144.06 (II). Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tuli (US 2009/0001576 A1) in view of Hirai (NPL: Fabrication of Porous Polyimide Membrane with Through‐Hole via Multiple Solvent Displacement Method) and Liu (US 2004/0009686 A1) as applied to claim 9 above, and in further view of Lee (US 2017/0373431 A1). Regarding claim 13, Tuli in view of Hirai and Liu teaches the electronic device of claim 9 but does not teach: further comprising an array of rigid protrusions between pins in the array of pins, the array of rigid protrusions configured to compress mating portions of the cap layer when socketed. Lee, in the same field of invention, teaches an electronic device further comprising an array of rigid protrusions (341&342; see Fig. 8, [0127]) between pins (331&332; Figs. 6-11, [0107]; 331&332 are analogous to Tuli’s pins since they provide electrical connections) in the array of pins, the array of rigid protrusions configured to compress mating portions (Fig. 8 shows 342 mating with 320) of a cap layer (320; Fig. 8, [0104], [0123]; plain meaning: 320 is a cap layer since it is covering and/or found above the seal) when socketed (as described in claim 17, ¶ [0130], and in Figs. 10A-11, protrusions 341&342 are pressing protrusions to be pressed by the first circuit board 310 and/or second circuit board 320; hence Lee teaches 341&342 are configured to compress mating portions of the cap layer ). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lee into the device of Tuli in view of Hirai and Liu to include an array of rigid protrusions between pins in an array of pins, with the rigid protrusions configured to compress mating portions of a cap layer when socketed. The ordinary artisan would have been motivated to modify Tuli in view of Hirai and Liu in the manner set forth above for at least the purpose of providing a waterproofed semiconductor packages and/or inhibiting foreign matter such as dust or moisture from entering into the package (Lee [0005]-[0008]). Claim(s) 14 - 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tuli (US 2009/0001576 A1) in view of Hirai (NPL: Fabrication of Porous Polyimide Membrane with Through‐Hole via Multiple Solvent Displacement Method) and Liu (US 2004/0009686 A1) as applied to claim 9 above, and in further view of Ptakova (US 2022/0336300 A1) and Yamanaka (US 2013/0176666 A1). Regarding claim 14, Tuli in view of Hirai and Liu teaches the electronic device of claim 9, but does not teach: further comprising a first fence located on lateral edges of the first surface and a second fence located on lateral edges of the second surface, wherein the first fence and the second fence slidably fit within each other to form a moisture barrier when socketed. Ptakova, in the same field of invention, teaches an electronic device socket (10, Figs. 1-2, [0027]) further comprising a first fence ( 50b; Figs. 6a-6c, [0056]; plain meaning: 50b is a fence since it is an upright structure that encloses other elements) located on lateral edges of the first surface (as shown in Figs. 1-2, 50b is located on a lateral edge of the upper surfaces of 52&14a) and a second fence ( 42b; Figs. 6a-6c, [0056]; plain meaning: 42b is a fence since it is an upright structure that encloses other elements) located on lateral edges of the second surface (as shown in Figs. 1-2, 42b is part of 42, with 42 located on lateral edges of the bottom surfaces marked 42a & 14b), wherein the first fence and the second fence slidably fit within each other (as shown in Fig. 6a-6b, the 50b and 52b slide vertically with each other at different heights h1, h2, and h3 together with the o-ring, which is labelled as element 20 in Figs 1-2). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Ptakova into the device of Tuli in view of Hirai and Liu to modify a seal between a first surface and a second surface of a socket by adding a first fence located on lateral edges of the first surface and by adding a second fence located on lateral edges of the second surface, wherein the first fence and second fence slidably fit within each other. The ordinary artisan would have been motivated to modify Tuli in view of Hirai and Liu in the manner set forth above for at least the purpose of designing a housing structure that does not rupture under arcing or short-circuit events (Ptakova [0003]-[0004], [0012]) and for further protection of the semiconductor device by using a protective ring-shaped as part to the housing (Ptakova [0005], [0061]). As mentioned above, Tuli in view of Hirai, Liu and Ptakova teaches a first fence and a second fence slidably fit within each other and, together with an o-ring, forms a sealing mechanism. However, Tuli in view of Hirai, Liu, and Ptakova is silent whether the sealing mechanism forms a moisture barrier. Yamanaka, in the same field of invention, teaches an electronic device (Fig. 1, [0034]) wherein an o-ring (5; Figs. 3 & 5, [0052]) is a sealing mechanism that forms a moisture barrier ( [0052], [0070]). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yamanaka into the device of Tuli in view of Hirai, Liu, and Ptakova to provide a sealing mechanism that forms a moisture barrier. The ordinary artisan would have been motivated to modify Tuli in view of Ptakova in the manner set forth above for at least the purpose of enabling electronic devices such as tablets and PDAs to be used for outdoor use that have reliable waterproof performance (Yamanaka [0003], [0009]-[0010]). Regarding claim 15, Tuli in view of Hirai, Liu, Ptakova, and Yamanaka teaches the electronic device of claim 14, but does not further teach: including an array of solder balls coupled to the array of pins through the first surface. Another embodiment of Tuli does teach including an array of solder balls (212; Fig. 2, [0016]) coupled to the array of pins (214, see [0016]) through the first surface (bottom surface of 220&210). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Tuli into the device of Tuli in view of Hirai, Liu, Ptakova, and Yamanaka to add solder balls coupled to an array of pins through the first surface of the socket. The ordinary artisan would have been motivated to modify Tuli in view of Hirai, Liu, Ptakova, and Yamanaka in the manner set forth above for at least the purpose of using the solder balls to connect the semiconductor die to other external devices (Tuli [0016]: “the substrate 210 may be a ball grid array (BGA) substrate that may comprise a set of one or more solder balls 212 on one side, e.g., the lower side of FIG. 2; however, in some embodiments, any other external interconnects may be utilized” ). Regarding claim 16, the electronic device of claim 15, wherein the first fence is vertically movable with respect to the first surface (as shown in Ptakova Figs. 6a-6c and [0061], 50b is vertically movable with each other at different heights h1, h2, and h3 with respect to 52). Regarding claim 17, the electronic device of claim 14, further including an o-ring (20; see Ptakova Figs. 1-2 and 6a-6c, [0028], [0061]) between the first fence and the second fence when socketed (as shown in Ptakova Figs. 1-2 and 6a-6c, the o-ring 20 spans vertically between the bottom-most surface of 50b and the topmost surface of 42b). Allowable Subject Matter Claims 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 7, no prior art was found to teach, either in whole or in combination with another, the electronic interconnect socket of claim 1, further including an adhesive layer within a middle portion of the cap layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DOUGLAS YAP/Assistant Examiner, Art Unit 2899 /JOHN M PARKER/Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Dec 13, 2021
Application Filed
Oct 21, 2022
Response after Non-Final Action
May 06, 2025
Non-Final Rejection — §103
Aug 06, 2025
Response Filed
Sep 10, 2025
Final Rejection — §103
Nov 03, 2025
Request for Continued Examination
Nov 11, 2025
Response after Non-Final Action
Jan 06, 2026
Non-Final Rejection — §103
Apr 09, 2026
Applicant Interview (Telephonic)
Apr 09, 2026
Examiner Interview Summary

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+12.2%)
3y 3m
Median Time to Grant
High
PTA Risk
Based on 49 resolved cases by this examiner. Grant probability derived from career allow rate.

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