Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment filed on 6/24/25 has been entered.
Response to Arguments
Applicant’s arguments have been fully considered but they are moot because the arguments do not apply to any of the references being used in the current rejection.
Specification
Number of figures submitted does not match the number of figures listed under Brief Description of Drawings in the specification. All of the figures with alphabets should be listed separately. For example, ‘Figs. 1A-1C’ should be ‘Figs. 1A, 1B and 1C’.
In particular, ‘Figures. 5A-5C’ in the paragraph [0015], ‘Figures. 6A-6C’ in the paragraph [0016] and ‘Figures. 7A-7J’ in the paragraph [0017] are objected.
See MPEP 500 - Receipt and Handling of Mail and Papers, MPEP 507 - Drawing Review in the Office of Patent Application Processing (OPAP). This labeling convention ensures clarity and consistency in referencing figures throughout the patent application and publication. Improper labeling may result in an objection from OPAP and require correction.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Noh (US 20220085161).
Regarding claim 1. (Currently Amended) Fig 2 of Noh discloses An integrated circuit structure, comprising:
a first vertical stack of horizontal nanowires (NW1/NW2/NW3) having a first width (L1);
a second vertical stack of horizontal nanowires (NW4/NW5/NW6) immediately neighboring and parallel with the first vertical stack of horizontal nanowires and having a second width (L2) greater than the first width ([0043]: the third length L3 may be the same as the first length L1. And third length L3 in the first direction DR1 that is smaller than the second length L2. Thus, L2 is greater than L1); and
a third vertical stack of horizontal nanowires (NW7/NW8/NW9) immediately neighboring and parallel with the second vertical stack of horizontal nanowires and having the first width ([0043]: the third length L3 may be the same as the first length L1),
herein the second vertical stack of horizontal nanowires is laterally intervening between the first vertical stack of horizontal nanowires and the third vertical stack of horizontal nanowires (Fig 2).
Regarding claim 2. (Original) Noh discloses The integrated circuit structure of claim 1, further comprising a gate structure G1/G2/G3 over the first, second and third vertical stacks of horizontal nanowires (Fig 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under AIA 35 U.S.C. 103 as being unpatentable over by Noh (US 20220085161) in view of Kim (US 20210057411).
Regarding claim 3. (Original) Noh discloses The integrated circuit structure of claim 2. But Noh does not disclose further comprising a dielectric gate plug in a gate cut of the gate structure.
However, Kim discloses a gate structure (GE/GI) surrounding channel structures CH. As shown in Fig. 1C, Kim further discloses an insulating layer IL [0047] disposed within and interrupting the gate structure GP. The insulating layer IL extends through the gate structure and electrically isolates adjacent portions of the gate structure, thereby forming a dielectric-filled gate-cut isolation region.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate structure of Noh to include the dielectric gate-cut structure taught by Kim because Kim discloses that a dielectric-filled gate interruption may be used to electrically isolate adjacent portions of a gate structure. Incorporating Kim's gate-cut isolation structure into Noh's gate-all-around transistor architecture would have been a predictable use of a known gate-isolation technique to provide electrical separation of adjacent gate regions while preserving normal transistor operation.
Regarding claim 4. (Original) Noh discloses The integrated circuit structure of claim 1. But Noh does not expressly disclose wherein the first and third vertical stacks of horizontal nanowires are NMOS vertical stacks of horizontal nanowires, and the second vertical stack of horizontal nanowires is a PMOS vertical stack of horizontal nanowires.
However, Kim discloses a first region RG1, a second region RG2, and a third region RG1 arranged sequentially along direction D1. Kim further discloses that the transistor structures in RG1 are first transistors and the transistor structures in RG2 are second transistors. Paragraph [0021] expressly discloses that the first transistors may be NMOSFETs and the second transistors may be PMOSFETs. Accordingly, Kim discloses an NMOS-PMOS-NMOS arrangement corresponding to RG1-RG2-RG1.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the first, second, and third nanowire stacks of Noh using the NMOS-PMOS-NMOS arrangement taught by Kim because Kim discloses a known complementary transistor arrangement suitable for adjacent transistor structures, and applying the known conductivity-type assignment to Noh's nanowire transistor architecture would have yielded predictable CMOS circuit functionality.
Claim 5 is rejected under AIA 35 U.S.C. 103 as being unpatentable over by Noh (US 20220085161).
Regarding claim 5. (Original) Noh discloses The integrated circuit structure of claim 1, wherein the second width is about three times greater than the first width (Noh discloses a first width having a range of 5 nm to 20 nm and a second width having a range of 30 nm to 300 nm [0044]. The claimed limitation that the second width is about three times greater than the first width is encompassed by and overlaps the dimensional ranges disclosed by Noh. For example, a first width of 10 nm and a second width of 30 nm, a first width of 15 nm and a second width of 45 nm, or a first width of 20 nm and a second width of 60 nm satisfy the claimed relationship. Thus, the dimensional ranges taught by Noh encompass embodiments falling within the scope of the claimed ratio. Thus, it would have been obvious to one of ordinary skill in the art to select dimensions within the disclosed ranges through routine optimization because the claimed ratio merely represents a value or subrange selected from within the broader dimensional ranges taught by Noh. A prima facie case of obviousness exists where the claimed range overlaps or is encompassed by a range disclosed in the prior art. In re Peterson, 315 F.3d 1325, 1329-30 (Fed. Cir. 2003). Furthermore, where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable values through routine experimentation is ordinarily within the skill of the art. In re Aller, 220 F.2d 454, 456 (CCPA 1955). The claimed ratio also constitutes no more than the selection of an optimum value of a result-effective variable, which is ordinarily obvious. In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990). See also In re Boesch, 617 F.2d 272, 276 (CCPA 1980) (a prima facie case of obviousness exists where the claimed and prior-art ranges are sufficiently close such that one of ordinary skill in the art would have expected them to possess the same properties). Applicant has not identified, and the present record does not demonstrate, any criticality associated with the claimed “about three times” relationship or any unexpected results arising therefrom. Accordingly, the claimed dimensional relationship would have been obvious to one of ordinary skill in the art at the time of the invention).
Claims 6-10 are rejected under AIA 35 U.S.C. 103 as being unpatentable over by Kim (US 20210057411) in view of Noh (US 20220085161).
Regarding claim 6. (Currently Amended) Fig 1C of Kim discloses An integrated circuit structure, comprising:
a first vertical stack (SP1/SP2/SP3 in AP1) of horizontal nanowires having a first width (W1);
a second vertical stack (SP1/SP2/SP3 in AP2) of horizontal nanowires immediately neighboring and parallel with the first vertical stack of horizontal nanowires and having a second width (W2) greater than the first width [0025];
a third vertical stack (SP1/SP2/SP3 in AP3) of horizontal nanowires immediately neighboring and parallel with the second vertical stack of horizontal nanowires and having the second width (W3, [0025]: W2 is equal to W3); and
a fourth vertical stack (SP1/SP2/SP3 in AP4) of horizontal nanowires immediately neighboring and parallel with the third vertical stack of horizontal nanowires and having the first width (W4, [0025]: W1 is equal to W4),
wherein the second vertical stack of horizontal nanowires and the third vertical stack of horizontal nanowires are laterally intervening between the first vertical stack of horizontal nanowires and the fourth vertical stack of horizontal nanowires (Fig 1C).
But Kim does not explicitly disclose that the channel patterns are horizontal nanowires.
However, Noh discloses a semiconductor device including first to sixth nanowires extending in a first direction and further discloses vertically stacked groups of nanowires NW1-NW3, NW4-NW6, and NW7-NW9 associated with active patterns F1, F2, and F3, respectively (Fig. 2).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the stacked channel structures of Kim to employ the nanowire channel architecture taught by Noh because Noh discloses stacked horizontal nanowires as a known gate-all-around transistor channel configuration. Employing Noh's known nanowire channel architecture in Kim's gate-all-around transistor structure would have amounted to the substitution of one known gate-all-around channel geometry for another known gate-all-around channel geometry to obtain predictable results, including known gate-all-around transistor operation and electrostatic gate control.
Regarding claim 7. (Original) Kim in view of Noh discloses The integrated circuit structure of claim 6, Kim discloses further comprising a gate structure (GE/GI) over the first, second, third and fourth vertical stacks of horizontal nanowires (Fig 1C).
Regarding claim 8. (Original) Kim in view of Noh discloses The integrated circuit structure of claim 7, Kim discloses further comprising a dielectric gate plug in a gate cut of the gate structure (Kim further discloses an insulating layer IL [0047] disposed within and interrupting the gate structure GP. The insulating layer IL extends through the gate structure and electrically isolates adjacent portions of the gate structure, thereby forming a dielectric-filled gate-cut isolation region).
Regarding claim 9. (Original) Kim in view of Noh discloses The integrated circuit structure of claim 6, Kim discloses wherein the first and third vertical stacks of horizontal nanowires are NMOS vertical stacks of horizontal nanowires, and the second and fourth vertical stacks of horizontal nanowires are PMOS vertical stacks of horizontal nanowires (Kim discloses a first region RG1, a second region RG2, a third region RG1, and fourth region RG2 arranged sequentially along direction D1. Kim further discloses that the transistor structures in RG1 are first transistors and the transistor structures in RG2 are second transistors). Paragraph [0021] expressly discloses that the first transistors may be NMOSFETs and the second transistors may be PMOSFETs. Accordingly, Kim discloses an NMOS-PMOS-NMOS-PMOS arrangement corresponding to RG1-RG2-RG1-RG2).
Regarding claim 10. (Original) Kim in view of Noh discloses The integrated circuit structure of claim 6, wherein the second width is about three times greater than the first width (Noh discloses a first width having a range of 5 nm to 20 nm and a second width having a range of 30 nm to 300 nm [0044]. The claimed limitation that the second width is about three times greater than the first width is encompassed by and overlaps the dimensional ranges disclosed by Noh. For example, a first width of 10 nm and a second width of 30 nm, a first width of 15 nm and a second width of 45 nm, or a first width of 20 nm and a second width of 60 nm satisfy the claimed relationship. Thus, the dimensional ranges taught by Noh encompass embodiments falling within the scope of the claimed ratio. Thus, it would have been obvious to one of ordinary skill in the art to select dimensions within the disclosed ranges through routine optimization because the claimed ratio merely represents a value or subrange selected from within the broader dimensional ranges taught by Noh. A prima facie case of obviousness exists where the claimed range overlaps or is encompassed by a range disclosed in the prior art. In re Peterson, 315 F.3d 1325, 1329-30 (Fed. Cir. 2003). Furthermore, where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable values through routine experimentation is ordinarily within the skill of the art. In re Aller, 220 F.2d 454, 456 (CCPA 1955). The claimed ratio also constitutes no more than the selection of an optimum value of a result-effective variable, which is ordinarily obvious. In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990). See also In re Boesch, 617 F.2d 272, 276 (CCPA 1980) (a prima facie case of obviousness exists where the claimed and prior-art ranges are sufficiently close such that one of ordinary skill in the art would have expected them to possess the same properties). Applicant has not identified, and the present record does not demonstrate, any criticality associated with the claimed “about three times” relationship or any unexpected results arising therefrom. Accordingly, the claimed dimensional relationship would have been obvious to one of ordinary skill in the art at the time of the invention).
Claims 11-15 are rejected under AIA 35 U.S.C. 103 as being unpatentable over by Crum (US 20200105756) in view of Noh (US 2022/0085161).
Regarding claim 11. (Currently Amended) Fig 10 of Crum discloses A computing device 1000, comprising:
a board 1002; and
a component coupled to the board (Crum further discloses that board 1002 includes processor 1004 and communication chip 1006, wherein processor 1004 is physically and electrically coupled to board 1002 and communication chip 1006 may likewise be physically and electrically coupled to board 1002, [0126]), the component including an integrated circuit structure [0001].
Although Crum discloses a plurality of vertical arrangements of nanowires [Abstract], Crum does not expressly disclose that the component comprising:
a first vertical stack of horizontal nanowires having a first width;
a second vertical stack of horizontal nanowires immediately neighboring and parallel with the first vertical stack of horizontal nanowires and having a second width greater than the first width; and
a third vertical stack of horizontal nanowires immediately neighboring and parallel with the second vertical stack of horizontal nanowires and having the first width wherein the second vertical stack of horizontal nanowires is laterally intervening between the first vertical stack of horizontal nanowires and the third vertical stack of horizontal nanowires.
However, Fig 2 of Noh discloses a first vertical stack of horizontal nanowires (NW1/NW2/NW3) having a first width (L1);
a second vertical stack of horizontal nanowires (NW4/NW5/NW6) immediately neighboring and parallel with the first vertical stack of horizontal nanowires and having a second width (L2) greater than the first width [0043]; and
a third vertical stack of horizontal nanowires (NW7/NW8/NW9) immediately neighboring and parallel with the second vertical stack of horizontal nanowires and having the first width (L3, [0043]: L3 = L1) wherein the second vertical stack of horizontal nanowires is laterally intervening between the first vertical stack of horizontal nanowires and the third vertical stack of horizontal nanowires (Fig 2).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the integrated circuit component of Crum using the gate-all-around transistor arrangement taught by Noh because Noh discloses a known transistor layout suitable for incorporation into integrated circuit devices such as the processors and communication chips expressly disclosed by Crum. The modification merely involves incorporation of a known transistor architecture into a known integrated circuit component to obtain predictable semiconductor device functionality.
Regarding claim 12. (Original) Crum in view of Noh discloses The computing device of claim 11, Crum discloses further comprising:
a memory coupled to the board (Fig 10).
Regarding claim 13. (Original) Crum in view of Noh discloses The computing device of claim 11, Crum discloses further comprising:
a communication chip coupled to the board (Fig 10).
Regarding claim 14. (Original) Crum in view of Noh discloses The computing device of claim 11, Crum discloses wherein the component is a packaged integrated circuit die [0129].
Regarding claim 15. Crum in view of Noh discloses The computing device of claim 11, Crum discloses wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor [0127].
Claims 16-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over by Crum (US 20200105756) in view of Kim (US 20210057411).
Regarding claim 16. (Currently Amended) Fig 10 of Crum discloses A computing device 1000, comprising:
a board 1002; and
a component coupled to the board, the component including an integrated circuit structure (Crum discloses computing device 1000 including board 1002, processor 1004, and communication chip 1006 coupled to board 1002, [0126]).
Although Crum discloses a plurality of vertical arrangements of nanowires [Abstract], Crum does not expressly disclose the component comprising:
a first vertical stack of horizontal nanowires having a first width;
a second vertical stack of horizontal nanowires immediately neighboring and parallel with the first vertical stack of horizontal nanowires and having a second width greater than the first width;
a third vertical stack of horizontal nanowires immediately neighboring and parallel with the second vertical stack of horizontal nanowires and having the second width; and
a fourth vertical stack of horizontal nanowires immediately neighboring and parallel with the third vertical stack of horizontal nanowires and having the first width,
wherein the second vertical stack of horizontal nanowires and the third vertical stack of horizontal nanowires are laterally intervening between the first vertical stack of horizontal nanowires and the fourth vertical stack of horizontal nanowires.
However, Fig 1C of Kim discloses a first vertical stack (SP1/SP2/SP3 in AP1) of horizontal nanowires having a first width (W1);
a second vertical stack (SP1/SP2/SP3 in AP2) of horizontal nanowires immediately neighboring and parallel with the first vertical stack of horizontal nanowires and having a second width (W2) greater than the first width [0025];
a third vertical stack (SP1/SP2/SP3 in AP3) of horizontal nanowires immediately neighboring and parallel with the second vertical stack of horizontal nanowires and having the second width (W3, [0025]: W2 is equal to W3); and
a fourth vertical stack (SP1/SP2/SP3 in AP4) of horizontal nanowires immediately neighboring and parallel with the third vertical stack of horizontal nanowires and having the first width (W4, [0025]: W1 is equal to W4),
wherein the second vertical stack of horizontal nanowires and the third vertical stack of horizontal nanowires are laterally intervening between the first vertical stack of horizontal nanowires and the fourth vertical stack of horizontal nanowires (Fig 1C).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the transistor-stack width arrangement taught by Kim in the nanowire-based integrated circuit structure of Crum because Kim discloses a known arrangement of adjacent transistor stacks having differing widths. Applying Kim's known width relationship to Crum's nanowire gate-all-around architecture would have been a predictable use of a known transistor-layout technique in a known nanowire integrated circuit structure to obtain predictable semiconductor-device design results.
Regarding claim 17. (Original) Crum in view of Kim discloses The computing device of claim 16, Crum discloses further comprising:
a memory coupled to the board (Fig 10).
Regarding claim 18. (Original) Crum in view of Kim discloses The computing device of claim 16, Crum discloses further comprising:
a communication chip coupled to the board (Fig 10).
Regarding claim 19. (Original) Crum in view of Kim discloses The computing device of claim 16, Crum discloses wherein the component is a packaged integrated circuit die [0129].
Regarding claim 20. (Original) Crum in view of Kim discloses The computing device of claim 16, Crum discloses wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor [0127].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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