CTNF 17/550,236 CTNF 100011 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Prosecution is being reopened pursuant to 37 C.F.R. 1.198 following the board decision of 5/29/2026. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-4 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Masai (US Pub. 2009/0197062) and Yu et al. (“Yu” Us Pub. 2022/0344287) . Regarding claim 1, Masai discloses: a planar inductor (1, Figures 1 and 2) including a thin film (12A, 12B, 13A, para. [0044]) at least partially surrounding a conductive trace (coil 14, para. [0044], thin film 12A, 12B, 13A, surrounding conductive trace 14 shown in Figure 2). Masai does not disclose: A microelectronic assembly, comprising: a substrate having a first surface and an opposing second surface, the second surface having a cavity; a first die at least partially nested in the cavity; an insulating material on the second surface of the substrate, the insulating material having a first surface and an opposing second surface, wherein the first surface of the insulating material is at the second surface of the substrate; a second die, at the second surface of the insulating material, electrically coupled to the first die. Yu discloses, however: A microelectronic assembly (Figure 1), comprising: a substrate (122, para. [0043]) having a first surface and an opposing second surface (shown in modified Yu Figure 1), the second surface having a cavity (shown in modified Yu Figure 1); a first die (150, para. [0018]) at least partially nested in the cavity (shown in modified Yu Figure 1); an insulating material (154, 124 contains dielectric layers, para. [0044]-[0051], [0057]) on the second surface of the substrate (122, para. [0043], shown in modified Yu Figure 1), the insulating material (154, 124) having a first surface and an opposing second surface (shown in modified Yu Figure 1), wherein the first surface of the insulating material (154, 124) is at the second surface of the substrate (122, para. [0043], shown in modified Yu Figure 1); a planar inductor (146, para. [0018], shown in Figure 1) embedded in the insulating material (154, 124, para. [0018]), and a second die (160, para. [0018]), at the second surface of the insulating material (154, 124, shown in modified Yu Figure 1), electrically coupled to the first die (150, electrical connection structures in Figure 1 show electrical coupling of the first and second die). It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Yu into the teachings of Masai to include a microelectronic assembly, comprising: a substrate having a first surface and an opposing second surface, the second surface having a cavity; a first die at least partially nested in the cavity; an insulating material on the second surface of the substrate, the insulating material having a first surface and an opposing second surface, wherein the first surface of the insulating material is at the second surface of the substrate; a planar inductor embedded in the insulating material, the planar inductor including a thin film at least partially surrounding a conductive trace; and a second die, at the second surface of the insulating material, electrically coupled to the first die. One of ordinary skill in the art would recognize the advantages of using planar inductors in a multitude of devices (for feedback control, energy storage, filters, etc.), because of its compact size, lower manufacturing cost, and improved thermal management. Regarding claim 2, Masai discloses: wherein the thin film (12A, 12B, 13A) includes a first layer (12A, 12B) having a magnetic material (materials disclosed in para. [0048]) and a second layer (13A) having a dielectric material (material of 13A is silicon oxide, para. [0046]). Regarding claim 3, Masai discloses: wherein the magnetic material (12A, 12B) includes cobalt, zirconium, and tantalum (12A and 12B comprise layers 121 and 122 shown in Figure 5B and disclosed in para. [0048] and comprise CoZrTa and an iron-based film, disclosed in para. [0048]-[0049]) and the dielectric includes alumina, magnesia, or silica (material of 13A is silicon oxide which is silica, para. [0046]). Regarding claim 4, Masai discloses: wherein the first layer (12A, 12B) has a thickness between 100 nanometers and 2,000 nanometers (para. [0071] discloses the thickness ratio of layer 121 to 122 being 3nm/200nm, thus the total thickness of layers 121 and 122 which make up 12A and 12B, is about 203nm) and the second layer (13A) has a thickness between 100 nanometers and 2,000 nanometers (Figure 2 shows layer 13A as substantially the same thickness as layer 12A and 12B. “…drawings, for what they would reasonably teach one of ordinary skill in the art.” See MPEP 2125). Regarding claim 7, Masai discloses: wherein the conductive trace (14) has a horseshoe pattern, a U- shaped pattern, a block shaped pattern, a straight line pattern, a spiral block pattern, a spiral pattern, a serpentine block pattern, or a zigzag pattern (Figure 1 shows a spiral pattern of conductive trace 14). Regarding claim 8, Masai discloses: wherein the planar inductor (1, Figure 1 and 2) has an overall thickness between 25 microns and 100 microns (the lower limit of the thickness of the inductor is the thickness of layer 122 which is disclosed as 100 nanometers to 10 microns, para. [0071], thus it would have been obvious to optimize the overall thickness of the inductor device to be compact, between 25 and 100 microns). Regarding claim 9, Masai discloses wherein the thin film (12A, 12B, 13A) includes between 2 and 20 layers (the thin film 12A, 12B, 13B includes 3 layers). Regarding claim 10, Masai does not disclose wherein the planar inductor is at least partially within a footprint of the second die. Yu discloses wherein the planar inductor (146) is at least partially within a footprint of the second die (160, as shown in Figure 1, planar inductor 146 is located at least partially within the footprint of the second die 160). It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Yu into the teachings of Masai et al. to include the planar inductor at least partially within a footprint of the second die. One of ordinary skill in the art would recognize the advantages of a compact, stacked arrangement of devices for the purpose of making use of available space and enhancing performance of the devices . 07-22-aia AIA Claim s 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Masai (US Pub. 2009/0197062) and Yu et al. (“Yu” Us Pub. 2022/0344287) as applied to claim 1 above, and further in view of Kim et al. (“Kim” US Pub. 2020/0395174) . Regarding claim 5, Masai does not disclose wherein the thin film includes a single layer of a non- conducting, high permeability dielectric material. Kim discloses wherein the thin film (111, para. [0066]) includes a single layer of a non- conducting, high permeability dielectric material (111 comprises Fe, Ni, and Zn in the dielectric composition). It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Kim into the teachings of Masai and Yu to include a single layer of a non- conducting, high permeability dielectric material for the thin film for the purpose of improving high-temperature withstand voltage characteristics (Kim, para. [0075]). Regarding claim 6, Masai does not disclose wherein the non-conducting, high permeability dielectric material includes nickel, zinc, and iron or nickel, cobalt, zinc, and iron. Kim discloses wherein the non-conducting, high permeability dielectric material (111, para. [0066]) includes nickel, zinc, and iron or nickel, cobalt, zinc, and iron (111 includes Ni, Zn, and Fe, para. [0074]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of into the teachings of Masai and Yu to include a single layer of a non- conducting, high permeability dielectric material for the thin film for the purpose of improving high-temperature withstand voltage characteristics (Kim, para. [0075]) . 07-21-aia AIA Claim s 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Masai (US Pub. 2009/0197062) and Yu et al. (“Yu” Us Pub. 2022/0344287) as evidenced by Mizoguchi et al. (“Mizoguchi” JP 2001110639) . Regarding claim 11, Yu discloses: A microelectronic assembly (100, Figure 1), comprising: a substrate (122, para. [0043]) having a first surface and an opposing second surface (shown in modified Yu Figure 1), the second surface having a cavity (shown in modified Yu Figure 1); a first die (150, para. [0018]) at least partially nested in the cavity (shown in modified Yu Figure 1); an insulating material (154, 124 contains dielectric layers, para. [0044]-[0051], [0057]) on the second surface of the substrate (122, para. [0043], shown in modified Yu Figure 1), the insulating material (154, 124) having a first surface and an opposing second surface (shown in modified Yu Figure 1), wherein the first surface of the insulating material (154, 124) is at the second surface of the substrate (122, para. [0043], shown in modified Yu Figure 1); a [planar] inductor (146, para. [0018], shown in Figure 1) embedded in the insulating material (154, 124, para. [0018]), the planar inductor (146) including a thin film (138, 134, para. [0049]) at least partially surrounding a conductive trace (128, para. [0046]), wherein the thin film (138, 134) has a first layer (134) including a magnetic material (134 is comprised of tungsten, para. [0028]) and a second layer (138), on the first layer (134, stacking shown in Figure 1), including a dielectric material (138 is a dielectric material, para. [0049]); and a second die (160, para. [0018]), at the second surface of the insulating material (154, 124, shown in modified Yu Figure 1), electrically coupled to the first die (150, electrical connection structures in Figure 1 show electrical coupling of the first and second die). Yu does not disclose that the inductor (146) is a planar inductor (Yu’s is a solenoid inductor). Masai discloses, however, a planar inductor including a thin film (12A, 12B, 13A, para. [0044]) at least partially surrounding a conductive trace (coil 14, para. [0044], thin film 12A, 12B, 13A, surrounding conductive trace 14 shown in Figure 2), wherein the thin film (12A, 12B, 13A) has a first layer (12A, 12B) including a magnetic material (magnetic films 12A and 12B, para. [0048]) and a second layer (13A), on the first layer (12A, 12B, see Figure 2) having a dielectric material (material of second layer 13A is silicon oxide, para. [0046]). It would have been obvious to incorporate the teachings of Masai into the teachings of Yu to include the planar inductor of Masai in place of the solenoid inductors of Yu for the purpose of reducing the size and thickness of the electronic device, contributing to minimization requirements in the industry, as evidenced by Mizoguchi (see Mizoguchi JP reference attached, page 45, para. 5). Regarding claim 12, Masai discloses wherein the magnetic material (12A, para. [0048]) includes cobalt, zirconium, and tantalum, nickel and iron, or cobalt and iron (magnetic film 12A is comprised of cobalt zirconium tantalum, “CZT”, and an iron based magnetic material, para. [0049]). Regarding claim 13, Masai discloses wherein the dielectric includes alumina, magnesia, or silica (the second layer 13A is made of silicon oxide, or silica, para. [0046]). Regarding claim 14, Yu further discloses a conductive through-substrate via (118, para. [0018]) extending through the substrate (122, para. [0018]); and a conductive pillar (132, 148, 152, para. [0044], [0053]-[0055]) extending through the insulating material (154, 124), wherein the conductive pillar (132, 148, 152) is electrically coupled to the conductive through-substrate via (118, shown in Figure 1). Regarding claim 15, Yu discloses wherein the conductive trace (128) is electrically coupled to the conductive through-substrate via (118) or the conductive pillar (conductive trace 128 is electrically coupled to the conductive through-substrate via 118 through conductive pillar 132, 148, 152) . 07-21-aia AIA Claim s 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (“Yu” Us Pub. 2022/0344287), Masai (US Pub. 2009/0197062), and Kim et al. (“Kim” US Pub. 2020/0395174) as evidenced by Mizoguchi et al. (“Mizoguchi” JP 2001110639) . Regarding claim 16, Yu discloses: A microelectronic assembly (100, Figure 1), comprising: a glass substrate (122, silicon oxide material, para. [0043]) having a first surface and an opposing second surface (shown in modified Yu Figure 1), wherein the second surface has a cavity (shown in modified Yu Figure 1), and wherein the glass substrate (122) includes a plurality of conductive through-glass vias (TGVs) (118, para. [0018]); a first die (150, para. [0018]) at least partially nested in the cavity (shown in modified Yu Figure 1); an insulating material (124, 154, para. [0044]-[0051], [0057]) on the second surface of the glass substrate (122, shown in modified Yu Figure 1) and surrounding the first die (150) in the cavity (shown in modified Yu Figure 1), wherein the insulating material (124, 154) has a first surface and an opposing second surface and the first surface of the insulating material is at the second surface of the glass substrate (shown in modified Yu Figure 1); a [planar] inductor (146, para. [0018]) at the second surface of the glass substrate (122, shown in modified Yu Figure 1) and embedded in the insulating material (124, 154), wherein the planar inductor (146) includes a thin film (138, para. [0049]) at least partially surrounding a conductive trace (128, para. [0044]), wherein the thin film (138) includes a single layer of a non-conducting [high permeability] dielectric material (138 is a dielectric layer, para. [0049]), and wherein the conductive trace (128) is electrically coupled to an individual TGV (118) of the plurality of TGVs (shown in Figure 1); and a second die (160, para. [0018]), at the second surface of the insulating material (124, 154, shown in modified Yu Figure 1), electrically coupled to the first die (electrical coupling through conductive structures in insulating material 124, 154). Yu does not disclose that the inductor (146) is a planar inductor (Yu’s is a solenoid inductor). Masai discloses, however, a planar inductor including a thin film (12A, 12B, 13A, para. [0044]) at least partially surrounding a conductive trace (coil 14, para. [0044], thin film 12A, 12B, 13A, surrounding conductive trace 14 shown in Figure 2). It would have been obvious to incorporate the teachings of Masai into the teachings of Yu to include the planar inductor of Masai in place of the solenoid inductors of Yu for the purpose of reducing the size and thickness of the electronic device, contributing to minimization requirements in the industry, as evidenced by Mizoguchi (see Mizoguchi JP reference attached, page 45, para. 5). Yu does not explicitly disclose a high permeability dielectric material for the thin film. Kim discloses a high permeability dielectric material (111 comprises Fe, Ni, and Zn in the dielectric composition). It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Kim et al. into the teachings of Yu and Masai to include a single layer of a non- conducting, high permeability dielectric material for the thin film for the purpose of improving high-temperature withstand voltage characteristics (Kim, para. [0075]). Regarding claim 17, Kim discloses wherein the non-conducting, high permeability dielectric material (111) includes nickel, zinc, and iron or nickel, zinc, cobalt, and iron (111 comprises Fe, Ni, and Zn in the dielectric composition). Regarding claim 18, the combination of Yu and Masai discloses wherein the planar inductor (incorporated into solenoid inductors 146 of Yu) is one of a plurality of planar inductors (Figure 13 of Yu shows a plurality of inductors which results in a plurality of planar inductors with the combination of teachings). Regarding claim 19, Yu discloses wherein the first die (150) includes an embedded multi-die bridge (EMIB) die, a passive die, an EMIB with through-silicon vias (TSVs), or an active die (die 150 comprise a passive device, para. [0018]). Regarding claim 20, Yu discloses wherein the second die includes a central processing unit (CPU), a graphics processing unit (GPU), or a processing die (die 160 comprises a logic circuit, para. [0018]). Annotated Figure 1 of Yu PNG media_image1.png 448 1124 media_image1.png Greyscale Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached on 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899 /KIESHA R BRYANT/Director, Art Unit 2800 Application/Control Number: 17/550,236 Page 2 Art Unit: 2899 Application/Control Number: 17/550,236 Page 3 Art Unit: 2899 Application/Control Number: 17/550,236 Page 4 Art Unit: 2899 Application/Control Number: 17/550,236 Page 5 Art Unit: 2899 Application/Control Number: 17/550,236 Page 6 Art Unit: 2899 Application/Control Number: 17/550,236 Page 7 Art Unit: 2899 Application/Control Number: 17/550,236 Page 8 Art Unit: 2899 Application/Control Number: 17/550,236 Page 9 Art Unit: 2899 Application/Control Number: 17/550,236 Page 10 Art Unit: 2899 Application/Control Number: 17/550,236 Page 11 Art Unit: 2899 Application/Control Number: 17/550,236 Page 12 Art Unit: 2899 Application/Control Number: 17/550,236 Page 13 Art Unit: 2899
Prosecution Insights