DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/14/2025 has been entered.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3-7, 13, 14, 16, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bierhuizen (US 2016/0133803 A1) in view of Guo (US 2020/0027797 A1).
Regarding claim 1, Bierhuizen discloses a method to produce dies for a wafer reconstitution, the method comprising:
inspecting (testing semiconductor devices in the wafer; Fig. 2, step 12; ¶ 0022) an epitaxial wafer (¶ 0005) to detect one or more defects (¶ 0023);
overlaying a dicing scheme on the epitaxial wafer with the detected defects (Fig. 2, steps 12);
classifying the dies in the dicing scheme as good dies comprising at least a central region with zero defects or bad dies comprising said one or more defects (¶¶ 0023 and 0030); and
dicing the epitaxial wafer into dies and transferring the good dies onto a target or carrier wafer (¶¶ 0022-0023).
Bierhuizen does not disclose that the epitaxial wafer is a blank epitaxial wafer during these steps.
Guo, in the same field of endeavor, discloses that inspection for defects may also occur while the wafer is a blank epitaxial wafer (¶ 0041). There was a benefit to performing inspection, dicing, and transferring of good dies while the epitaxial wafer is blank in that defects in the wafer can be found early in the manufacturing process so as to avoid the unnecessary deposition of functional layers over an already defective area. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to perform the inspecting, dicing, and transferring steps on a blank epitaxial wafer for this benefit.
Regarding claim 3, Guo further discloses inspecting the blank epitaxial wafer by optical techniques (“optical”, ¶ 0041).
Regarding claim 4, Guo further discloses selecting the good dies based on optical properties as measured by photo luminance (¶ 0041).
Regarding claim 5, Bierhuizen further discloses starting with a non-functionalized wafer as the blank epitaxial wafer with an epitaxial layer of III-N material on a substrate (¶ 0005).
Regarding claim 6, Bierhuizen further discloses dicing the epitaxial wafer (which is a blank epitaxial wafer in the method of the combination) comprises laser dicing (¶ 0022).
Regarding claim 7, Guo further discloses wherein the method further comprises the step of detecting epi-pits defects (¶ 0041).
Regarding claim 13, Bierhuizen discloses a system to produce dies for a wafer reconstitution, the system comprising:
a processing means configured to inspect an epitaxial wafer to detect one or more defects by inspection means and overlaying a dicing scheme on the measured defects of the epitaxial wafer (Fig. 2, step 12, ¶¶ 0005 and 0022);
wherein the processing means is further configured to classify the dies as good dies comprising at least a central region with zero defects or bad dies comprising said one or more defects (¶¶ 0022-0023); and
wherein the processing means is further configured to dice the good dies by dicing means (see Fig. 2, step 12).
Bierhuizen does not disclose that the epitaxial wafer is a blank epitaxial wafer during these steps.
Guo, in the same field of endeavor, discloses that inspection for defects may also occur while the wafer is a blank epitaxial wafer (¶ 0041). There was a benefit to performing inspection, dicing, and transferring of good dies while the epitaxial wafer is blank in that defects in the wafer can be found early in the manufacturing process so as to avoid the unnecessary deposition of functional layers over an already defective area. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to perform the inspecting, dicing, and transferring steps on a blank epitaxial wafer for this benefit.
Regarding claim 14, Bierhuizen further discloses wherein the processing means is further configured to dice the good dies (Fig. 2, step 12).
Regarding claim 16, Bierhuizen discloses a reconstituted wafer (Fig. 2, step 14) comprising good dies selected from an epitaxial wafer fixed on a carrier wafer (¶¶ 0005, 0022, 0023);
wherein, in the combination of Bierhuizen and Guo, the good dies are selected from a blank epitaxial wafer using the method according to claim 1 as discussed above;
wherein a plurality of the good dies is fixed or bonded on the target wafer or the carrier wafer (see rejection of claim 1, above).
Regarding claim 17, the resulting reconstituted wafer is suitable for a wafer-to-wafer bonding with a further wafer to form a display device, wherein the bonding is fusion bonding, anodic bonding or dielectric binding or metal-to-metal bonding or adhesive bonding (as the wafer can be bonded with another wafer with display elements on it, the reconstituted wafer is considered “suitable” to be bonded as such).
Claim(s) 2 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bierhuizen in view of Guo as applied to claim 1 above, and further in view of Spears (US 2004/0219443 A1).
Regarding claim 2, Bierhuizen in view of Guo does not disclose a step of adjusting the dicing scheme with a respect to the defects to optimize the location of the dies relative to the detected defects to yield a maximum number of good dies from the epitaxial wafer.
However, it was well-known in the art to adjust a dicing scheme with respect to defects to optimize the location of dies relative to the detected defects to yield a maximum number of good dies from a wafer (¶ 0014-15 of Spears).
There was a benefit to such a step in that it optimizes the dicing of the wafer.
It would have been obvious to one having ordinary skill in the art at the time the Application was filed to use the optimization step of Spears in the method of Bierhuizen for this benefit.
Regarding claim 12, Spears further discloses that the dicing scheme is a regular rectangular grid (see Fig. 1).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bierhuizen in view of Guo as applied to claim 1 above, and further in view of Mitsutake et al. (US 2002/0053065 A1).
Regarding claim 8, Bierhuizen discloses fixing the good dies onto a target wafer (¶ 0023) but does not explicitly disclose that it is by bonding.
However, it was well known in the art that affixation may be accomplished by direct bonding (¶ 0151 of Mitsutake).
There was a benefit to affixing dies by direct bonding in that they are less likely to undesirably separate.
It would have been obvious to one having ordinary skill in the art at the time the Application was filed to affix the dies of Bierhuizen via direct bonding for this benefit.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bierhuizen in view of Guo as applied to claim 1 above, and further in view of Hua et al. (US 11,222,863).
Regarding claim 9, Bierhuizen in view of Guo does not disclose each of the additional steps claimed.
However, it was well known in the art of determining known good dies and bonding them to a wafer to:
remove the substrate of the dies after fixing the good dies to the target wafer/carrier wafer (“removing the carrier wafer” in claim 2 of Hua),
fill gaps between the dies (“forming a dielectric on the second wafer between the first known good dies” in claim 3 of Hua), and
planarizing to form the plurality of defect-free dies distributed across the wafer (“thinning” in claim 1 of Hua).
There were benefits to such steps in that the profile of the resulting device may be made thinner (planarizing and removing the substrate) and maintaining electrical isolation between the good dies (depositing the intervening dielectric layer) which are recognized advantages in the art.
It would have been obvious to one having ordinary skill in the art at the time the Application was filed to remove the substrate of Bierhuizen after fixing the good dies to the carrier wafer to expose the epitaxial layer, fill the gaps between the dies, and planarize the dies to form a plurality of defect-free dies distributed across the wafer for these benefits.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bierhuizen in view of Guo as applied to claim 1 above, and further in view of Wang et al. (US 2019/0189603 A1).
Regarding claim 10, Bierhuizen in view of Guo does not explicitly disclose bonding the reconstituted wafer to a further wafer to form a display device as claimed.
However, it was well known in the art to form display devices (abstract of Wang) by a wafer-to-wafer bonding of a reconstituted wafer onto a further wafer wherein the further wafer comprises CMOS-transistors for driving and/or controlling electro-luminescent diodes made by structuring an epitaxial wafer (¶ 0028 of Wang).
There was a benefit to such a process in that a display device is able to transmit visual information to a consumer.
It would have been obvious to one having ordinary skill in the art at the time the Application was filed to use the additional method steps of Wang in the method taught by Bierhuizen in view of Guo to form a display device for this benefit.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bierhuizen in view of Guo as applied to claim 13 above, and further in view of Simmons (US 2001/0023083 A1).
Regarding claim 15, Bierhuizen in view of Guo does not further disclose that the processing means is configured to map the detected defects on the epitaxial wafer and test properties of a display device fabricated using the good dies and compare the map of detected defects corresponding to the properties of the display device.
However, these additional steps are well known in the art (¶¶ 0003, 0022, and 0031 with claim 8 of Simmons).
There was a benefit to using these additional steps in that it reduces yield losses (see Abstract of Simmons).
It would have been obvious to one having ordinary skill in the art at the time the Application was filed to use the additional method steps taught by Simmons in the system of Bierhuizen for this benefit.
Response to Arguments
Applicant's arguments filed 7/14/2025 have been fully considered but they are not persuasive.
Applicant argues that the inspection performed by Bierhuizen is after functional components have been formed over the device. This argument is not persuasive as Guo was relied upon for bridging the disclosure of Bierhuizen and the method of claims 1 and 12 by disclosing that inspections can occur while the wafer is a blank epitaxial wafer. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5.
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/CHRISTOPHER A CULBERT/ Examiner, Art Unit 2815
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