DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 08/29/2025 has been entered. Claims 1-6, 8, 10 and 12-16 remain pending in the application. Claims 7, 9, 11 and 17-20 have been cancelled. It is noted that, as discussed and agreed during a phone conversation with attorney of record, James M. Howard, on Tuesday, October 14th, 2025, claims 21, 22 and 23 are also canceled.
Applicant’s amendments have overcome 112(b) rejections of claims 14 and 15 previously set forth in the Non-Final Office Action mailed on 05/29/2025.
Claim Rejections - 35 USC § 112 (a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 10 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 10 recites the limitation: “wherein the conduction pathway comprises first vertical vias of a first diameter and pitch within a thickness of a first of the dielectric layers and comprises second vertical vias of a second, larger, diameter and pitch within a thickness of a second of the dielectric layers”. In the remarks filed on 08/29/2025, applicant pointed out that the structural elements of this limitation of claim 10, which is similar to a limitation of claim 1, are illustrated in Fig.1 of the instant application. Fig.1 shows three separate conductive pathways, 112, 114 and 116, neither of which has multiple vias in at least two of the dielectric layers. Fig.1 does not teach that the two vias within the bottom dielectric layer 110C, which have a larger diameter and pitch than the vias within the top dielectric layers, and therefore are associated with the second vertical vias, are part of the same conduction pathway. Top dielectric layer 110A has two vias that belong to the same conduction pathway but do not have a diameter and pitch larger than the diameter and pitch of the vias within the other dielectric layers. Furthermore, no other parts of the specification appear to include a written description of this claim limitation. Therefore, a person skilled in the art, at the time the application was filed, would have not recognized that the inventor was in possession of the invention as claimed in view of the disclosure of the application as filed.
Claims 12-16 are also rejected as being dependent of claim 10.
For the purpose of examination, the limitation of claim 10 described above, will be interpreted as “wherein the conduction pathway comprises first vertical vias of a first diameter and pitch within a thickness of a first of the dielectric layers and comprises a second vertical via
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitations: “at least one of first vias having a first diameter and pitch” and “at least one of second vias having a second, larger diameter and pitch”. The claims are indefinite because “at least one” implies that there can be only a single via, while a pitch requires at least two vias.
Claims 2-6 and 8 are also rejected as being dependent of claim 1.
For the purpose of examination, claim 1 will be interpreted as: An electronic interconnect device, comprising: a laminate stack comprising two or more plurality of dielectric layers coupled by an adhesive layer therebetween; at least one conduction pathway within extending through the laminate stack, the conduction pathway exposing a sidewall through a total thickness of each of at least two of the dielectric layers, wherein the conduction pathway includes at least and a liquid metal material within the conduction pathway, wherein the liquid metal material traverses is within each of the first vias and the second vias, laterally adjacent to the sidewall of each of the at least two layers of the plurality of dielectric layers.
Given the interpretation of claim 1 above, claim 6 will be interpreted as: “The electronic interconnect device of claim 1, wherein one of the at least .
Claim 10 recites the limitation: “substantially filling the first diameter of the first vias and substantially filling the second diameter”. The term "substantially" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Substantially” is defined as "being largely but not wholly that which is specified” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe what is required of the liquid material in order to “substantially fill” the diameter of the vias. The term “substantially” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “substantially” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target and specifically which of these possible values defines the boundaries. “Substantially filled” implies less than 100% filled but also required a lower boundary. Applicant has not defined the metes and bounds of this deviation. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Furthermore, there is no objective consensus in the art of the boundaries for substantially filled.
Claims 12-16 are also rejected as being dependent of claim 10.
For the purpose of examination, claim 10 will be interpreted as: An electronic device, comprising: a semiconductor die coupled to a substrate through an interposing interconnect device, the interposing interconnect device including; a laminate stack comprising two or more dielectric layers coupled by an adhesive layer therebetween; at least one conduction pathway within the dielectric layers, wherein the conduction pathway comprises first vertical vias of a first diameter and pitch within a thickness of a first of the dielectric layers and comprises a second vertical via and a liquid metal material wherein the liquid metal material traverses at least the two or more layers of the plurality of dielectric layers, and electrically couples the semiconductor die to the substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al., (United States Patent Number, US 7,652,213 B2) hereinafter referenced as Yamamoto, in view of Marsh, (United States Patent Application Publication Number, US 2019/0104616 A1) hereinafter referenced as Marsh, in view of Blanchard et al., (United States Patent Application Publication Number, US 2014/0138846 A1), hereinafter referenced as Blanchard and in view of disclosed prior art, Lu Shuang-hao et al., (Chinese Patent Application Publication Number, CN 111385978 A) hereinafter referenced as Lu.
Regarding claim 1, Yamamoto teaches an electronic interconnect device, comprising: a laminate stack comprising two or more of dielectric layers (Fig.1A, top two elements #11A, column 5, rows 12-15) which are pressure bonded (column 10, rows 50-52).
Yamamoto does not teach the dielectric layers are coupled by an adhesive layer therebetween. Marsh teaches dielectric layers coupled by an adhesive layer therebetween (paragraph [0101], rows 6-13). Thus, both references, Yamamoto and Marsh, teach a method of coupling the dielectric layers of a laminate stack. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the pressure bonding method disclosed by Yamamoto could have been replaced with the adhesive bonding method disclosed by Marsh, because both serve the same purpose of providing a method of forming a laminate stack comprising of dielectric layers. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of forming a laminate stack formed of dielectric layers.
Yamamoto further teaches at least one conduction pathway extending through the laminate stack (Fig.1A, shows three conductive pathways), the conduction pathway exposing a sidewall through a total thickness of each of at least two of the dielectric layers (Fig.1A, shows the conductive pathways expose sidewall of the top two layers, elements #11A), wherein the conduction pathway includes at least one of first vias having a first diameter within a first of the dielectric layers (Fig.1A, element #12 is within the top dielectric layer), and at least one of second vias having a second, larger, diameter (Fig.1A, element #17 is within second from top dielectric layer and has a larger diameter as compared to element #12).
Yamamoto teaches multiple first vias within the first of the dielectric layers having a pitch (Fig.1A, element #12, #13, and #14). The combination of Yamamoto and Marsh does not teach wherein the conduction pathway includes at least a conduction pathway includes at least two of first vias (Fig.17, the conduction path, in black, includes two vias in layer element #52). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Blanchard and disclose wherein the conduction pathway includes at least two of first vias. This allows for the same voltage and/or signal to be shared between connected vias located in the same layer, but horizontally spaced apart.
Yamamoto teaches a conductive paste material within the conduction pathway, wherein the conductive paste material is within each of the first vias and the second vias, laterally adjacent to the sidewall of each of the at least two dielectric layers (Fig.1A, the conductive pathways are filled with conductive paste, column 7, rows 13-16). The combination of Yamamoto, Marsh and Blanchard does not teach the conductive material is a liquid metal material. Lu teaches the conductive material within the conduction pathway is a liquid metal (Fig.2, element #5, page 2, row 27 of the machine translation). Thus, both references, Yamamoto and Lu, teach a conductive material that fills the conductive pathway. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the conductive paste disclosed by Yamamoto could have been replaced with the liquid metal disclosed by Lu, because both serve the same purpose of providing a conductive medium for the conductive pathway. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing a conductive medium for the conductive pathway.
Regarding claim 2, the combination of Yamamoto, Marsh, Blanchard and Lu teaches the electronic interconnect device of claim 1 as set forth in the obviousness rejection. The combination of Yamamoto, Marsh and Blanchard does not teach the electronic interconnect device of claim 1, wherein the conduction pathway traverses from a major surface of the interconnect device to an opposite major surface. Lu teaches wherein the conduction pathway traverses from a major surface of the interconnect device to an opposite major surface (Fig.2, element #5 traverses from the bottom surface to the top surface). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lu and disclose wherein the conduction pathway traverses from a major surface of the interconnect device to an opposite major surface. This allows connecting multiple dies or circuit boards to both major surfaces of interconnect device, thus allowing the manufacture of integrated circuit packages with small footprint.
Regarding claim 3, the combination of Yamamoto, Marsh, Blanchard and Lu teaches the electronic interconnect device of claim 1 as set forth in the obviousness rejection. The combination of Yamamoto, Marsh and Blanchard does not teach the electronic interconnect device of claim 1, wherein the liquid metal includes at least one of gallium or indium. Lu teaches wherein the liquid metal includes at least one of gallium or indium (liquid metal includes gallium, page 3, row 14 of the machine translation). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lu and disclose wherein the liquid metal includes at least one of gallium or indium. Gallium is a known liquid metal material and using it would have had a reasonable expectation of success.
Regarding claim 4, the combination of Yamamoto, Marsh, Blanchard and Lu teaches the electronic interconnect device of claim 1 as set forth in the obviousness rejection. Blanchard further teaches a conductive ink within the stack extends horizontally between the at least one of the first vias and the at least one of the second vias (Fig.17, the ink inside the conductive pathway extends horizontally between the leftmost via within dielectric layer, element #52 and the rightmost via within dielectric layer, element #50). Similar to arguments noted in the rejection of claim 1, where to the conductive paste disclosed by Yamamoto was substituted with the liquid metal disclosed by Lu, the conductive ink disclosed by Blanchard can also be substituted by the metal liquid disclosed by Lu. Therefore, the combination of Blanchard and Lu teaches the liquid metal material within the stack extends horizontally between the at least one of the first vias and the at least one of the second vias. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Blanchard and Lu and disclose the liquid metal material within the laminate stack extends horizontally between the at least one of the first vias and the at least one of the second vias. This allows the power and/or voltage to be distributed between contacts located in areas horizontally apart. Furthermore, it allows for the top and bottom surfaces of the electronic interconnect to have different contact pattern and still accommodate different types of dies or substrates that might be connected to the two surfaces of the electronic interconnect.
Regarding claim 6, the combination of Yamamoto, Marsh, Blanchard and Lu teaches the electronic interconnect device of claim 1 as set forth in the obviousness rejection. Yamamoto further teaches the electronic interconnect device of claim 1 wherein one of the at least (Fig.1A, element #12 is within the top dielectric layer), the at least one of the second vias is within the second of the dielectric layers at a second location, horizontally offset from the first location (Fig.1A, element #17 is within the second from the top dielectric layer, and offset horizontally from the first via).
The combination of Yamamoto and Marsh does not teach wherein the offset is by at least the first pitch. Blanchard teaches at least one of the at least two of first vias is within the first of the dielectric layers at a first location (Fig.17, leftmost via inside layer, element #52), and one of the at least one of the second vias is within the second of the dielectric layers at a second location (Fig.17, rightmost via inside layer, element #50), horizontally offset from the first location by at least the first pitch (Fig.17, the two vias are offset horizontally by more than the pitch between the two vias within layer element #52). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Blanchard and disclose one of the second via horizontally offset from the first location by at least the first pitch. This allows the main surfaces of the electronic interconnect to have different contact patterns geometries and pitches, with a reduction in pitch from one main surface to the other, and therefore provides design flexibility and allows the connection of large pitch components or substrates to dies with a much smaller contact pitch.
Blanchard further teaches a conductive ink between one of the at least (Fig.17, the ink forms a conductive pathway that extends horizontally between the leftmost via within dielectric layer, element #52 and the rightmost via within dielectric layer, element #50). Similar to arguments noted in the rejection of claim 1, where to the conductive paste disclosed by Yamamoto was substituted with the liquid metal disclosed by Lu, the conductive ink disclosed by Blanchard can also be substituted by the metal liquid disclosed by Lu. Therefore, the combination of Yamamoto, Blanchard and Lu teaches a liquid metal between one of the at least two of the first via and one of the at least one of the second vias extends horizontally within the laminate stack over the distance between the first and second locations to complete the conduction pathway through the stack. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Yamamoto, Blanchard and Lu and disclose a liquid metal between the ones of the first and second vias extends horizontally within the laminate stack over the distance between the first and second locations to complete the conduction pathway through the stack. This allows the voltage and/or signals to be distributed between contacts located in areas horizontally apart while allowing for the top and bottom surfaces of the electronic interconnect to have different contact patterns.
Regarding claim 8, the combination of Yamamoto, Marsh, Blanchard and Lu teaches the electronic interconnect device of claim 1 as set forth in the obviousness rejection. Yamamoto further teaches the electronic interconnect device of claim 1, wherein the conductive material completely fills the first diameter and completely fills the second diameter (Fig.1A, the conductive material completely fills the vias). As noted in the obviousness rejection of claim 1, the conductive paste disclosed by Yamamoto can be substituted by the liquid metal disclosed by Lu and therefore, the combination of Yamamoto and Lu teaches wherein the conductive material completely fills the first diameter and completely fills the second diameter.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto, in view of Marsh, Blanchard, Lu and in view of disclosed prior art, Bruzewicz et al., (United States Patent Application Publication Number, US 2011/0045577 A1) hereinafter referenced as Bruzewicz.
Regarding claim 5, the combination of Yamamoto, Marsh, Blanchard and Lu teaches the electronic interconnect device of claim 1 as set forth in the obviousness rejection. Lu further teaches wherein each of the plurality of at least two dielectric layers includes an elastomer layer (page 3, row 31 of the machine translation, polyurethane is an elastomer). The combination of Yamamoto, Marsh, Blanchard and Lu does not teach wherein each of the plurality of at least two dielectric layers in an elastomer layer. Bruzewicz teaches wherein each of the plurality of at least two dielectric layers in an elastomer layer (Fig.1A, element #1-110 and #1-105, paragraph [0016], rows 13-16). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Bruzewicz and disclose wherein each of the plurality of at least two dielectric layers in an elastomer layer. As disclosed by Bruzewicz, elastomers are inexpensive, readily available and provide structures that are flexible and conformable and can be easily fabricated (paragraph [0081], rows 5-6 and 12-15).
Claims 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Ioan Sauciuc et al., (United States Patent Number, US 7,939,945 B2) hereinafter referenced as Sauciuc, and in view of Marsh and Blanchard.
Regarding claim 10, Yamamoto teaches an electronic device, comprising: a semiconductor die (Fig.5A, element #40) coupled to an interposing interconnect device (Fig.5A, element #30). Yamamoto does not each the semiconductor die is coupled to a substrate through the interposing interconnect device. Sauciuc teaches a semiconductor die (Fig.8, element #220, column 11, row 17) is coupled to a substrate (Fig.8, element #100B, column 11, rows 17-18) through an interposing interconnect device (Fig.8, element #810, column 11, rows 12-17). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Sauciuc and disclose the semiconductor die is coupled to a substrate through the interposing interconnect device. The substrate can provide power to the semiconductor die through the interposing interconnect device.
Yamamoto further teaches the interposing interconnect device including a laminate stack comprising two or more dielectric layers (Fig.1A, top two elements #11A, column 5, rows 12-15) which are pressure bonded (column 10, rows 50-52). The combination of Yamamoto and Sauciuc does not teach the dielectric layers are coupled by an adhesive layer therebetween. Marsh teaches the dielectric layers are coupled by an adhesive layer therebetween (paragraph [0101], rows 6-13). Thus, both references, Yamamoto and Marsh, teach a method of coupling the dielectric layers of a laminate stack. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the pressure bonding method disclosed by Yamamoto could have been replaced with the adhesive bonding method disclosed by Marsh, because both serve the same purpose of providing a method of forming a laminate stack comprising of dielectric layers. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of forming a laminate stack formed of dielectric layers.
Yamamoto further teaches at least one conduction pathway within the dielectric layers (Fig.1A, shows three conductive pathways), wherein the conduction pathway comprises a first vertical via of a first diameter within a thickness of a first of the dielectric layers (Fig.1A, vertical element #12 is within the top dielectric layer), and comprises a second vertical via(Fig.1A, element #17 is within the second from top dielectric layer and has a larger diameter as compared to element #12).
Yamamoto teaches multiple first vias within the first of the dielectric layers having a pitch (Fig.1A, element #12, #13, and #14). The combination of Yamamoto, Sauciuc and Marsh does not teach wherein the conduction pathway includes at least (Fig.17, the conduction path, in black, includes two vias in layer element #52). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Blanchard and disclose wherein the conduction pathway includes at least two of first vias. This allows for the same voltage and/or signal to be shared between connected vias located in the same layer, but horizontally spaced apart.
Yamamoto teaches a conductive paste material (Fig.1A, the conductive pathways are filled with conductive paste, column 7, rows 13-16), wherein the conductive paste material traverses at least the two or more layers of the plurality of dielectric layers. (Fig.1A, the conductive pathways traverses the top two layers). Yamamoto does not teach the conductive material is a liquid metal material. Sauciuc teaches the conductive material is a liquid metal material (Fig.8, element #870, column 11, row 23-28 and column 1, row 9). Thus, both references, Yamamoto and Sauciuc, teach a conductive material within the conductive pathway. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the conductive paste disclosed by Yamamoto could have been replaced with the liquid metal disclosed by Sauciuc, because both serve the same purpose of providing a conductive medium for the conductive pathway. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing a conductive medium for the conductive pathway
Yamamoto does not teach the liquid metal electrically couples the semiconductor die to the substrate. Sauciuc teaches the liquid metal electrically couples the semiconductor die to the substrate (column 11, rows 22-27). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Sauciuc and disclose the liquid metal electrically couples the semiconductor die to the substrate. The substrate can provide power to the semiconductor die through the connection pathways within the interposing interconnect device, which contain the liquid metal.
Regarding claim 13, the combination of Yamamoto, Sauciuc, Marsh and Blanchard teaches the electronic device of claim 10 as set forth in the obviousness rejection. Blanchard further teaches, wherein the conduction pathway includes horizontal traces within the stack (Fig.14, the conductive pathway include horizontal traces) and coupling together one or more of the first vertical vias with one or more of the second vertical vias (Fig.17, the conductive pathway couples the first vertical vias in layer element #52 with the second vertical vias in later element #50) and wherein conductive ink material is within the horizontal traces (Fig.17, paragraph [0076], rows 2-3). Similar to arguments noted in the rejection of claim 10, where to the conductive paste disclosed by Yamamoto was substituted with the liquid metal disclosed by Sauciuc, the conductive ink disclosed by Blanchard can also be substituted by the metal liquid disclosed by Sauciuc. Therefore, the combination of Blanchard and Sauciuc teaches wherein the liquid metal material is within the horizontal traces. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Blanchard and Sauciuc and disclose the liquid metal material is within the horizontal traces. This allows the power and/or voltage to be distributed between contacts located in areas horizontally apart. Furthermore, it allows for the top and bottom surfaces of the electronic interconnect to have different contact patterns and still accommodate different types of dies or substrates that might be connected to the two surfaces of the electronic interconnect.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Sauciuc, Marsh, Blanchard and Bruzewicz.
Regarding claim 12, the combination of Yamamoto, Sauciuc, Marsh and Blanchard teaches the electronic device of claim 10 as set forth in the obviousness rejection. The combination of Yamamoto, Sauciuc and Marsh does not teach the electronic device of claim 10, wherein each of the dielectric layers is an elastomer layer. Bruzewicz teaches wherein each of the plurality of at least two dielectric layers in an elastomer layer (Fig.1A, element #1-110 and #1-105, paragraph [0016], rows 13-16). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Bruzewicz and disclose wherein each of the plurality of at least two dielectric layers in an elastomer layer. As disclosed by Bruzewicz, elastomers are inexpensive, readily available and provide structures that are flexible and conformable and can be easily fabricated (paragraph [0081], rows 5-6 and 12-15).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Sauciuc, Marsh, Blanchard and Lu.
Regarding claim 14, the combination of Yamamoto, Sauciuc, Marsh and Blanchard teaches the electronic device of claims 10 and 13 as set forth in the obviousness rejection. The combination of Yamamoto, Sauciuc, Marsh, and Blanchard does not teach the electronic device of claim 13, wherein the second vertical via has a cylinder geometry. Lu teaches, second vertical vias has a cylinder geometry (Fig.2, element #2). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Lu and disclose wherein the vertical vias include a cylinder geometry. Cylinder shaped vias are well known in the art and therefore a prima facie case of obviousness exists (MPEP 2144.03).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Sauciuc, Marsh, Blanchard and in view of Huemoeller et al., (United States Patent Number US 6,930,256 B1) hereinafter referenced as Huemoeller.
Regarding claim 15, the combination of Yamamoto, Sauciuc, Marsh and Blanchard teaches the electronic device of claims 10 and 13 as set forth in the obviousness rejection. The combination of Yamamoto, Sauciuc, Marsh and Blanchard does not teach the electronic device of claim 13, wherein the second vertical via has a conical geometry and wherein a small end of the conical geometry is proximal to the first dielectric layer. Huemoeller teaches the second vertical via has a conical geometry and wherein a small end of the conical geometry is proximal to the first dielectric layer (Fig.2b, element #22, column 3, rows 34-36). As disclosed by Huemoeller, this geometry is preferred for addition of conductive material into the via (column 3, rows 35-37).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Sauciuc, Marsh, Blanchard and in view of Ellinger et al., (United States Patent Application Publication Number US 2016/0141092 A1) hereinafter referenced as Ellinger.
Regarding claim 16, the combination of Yamamoto, Sauciuc, Marsh and Blanchard teaches the electronic device of claim 10 as set forth in the obviousness rejection. The combination of Yamamoto, Sauciuc, Marsh and Blanchard does not teach the electronic device of claim 10, wherein the two or more dielectric layers includes different materials in different layers. Ellinger teaches wherein the two or more dielectric layers includes different materials in different layers (Fig.1A, paragraph [0058], rows 1-7). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ellinger and disclose wherein the two or more dielectric layers includes different materials in different layers. A substrate made of dielectric layers that include different materials offer flexibility in terms of creating etch patterns inside the layers, because the materials may have different etching properties where some of the layers can act as etch stop layers for the others.
Response to Arguments
Applicant’s arguments filed on 08/29/2025 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to claims 1, 8, 10 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899