DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on Dec. 30th 2025 has been entered.
Response to Amendment
The amendment filed on Dec. 1st, 2025 has been entered. Claims 1-16 and 21-24 remain pending in the application. Applicant’s amendments to the Claims have overcome each and every objection previously set forth in the Final Office Action mailed on Oct. 1st, 2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20190319095) in view of Rubin et al. (US20200126987).
Regarding claim 1, Zhang teaches an integrated circuit (Abstract) comprising:
a first semiconductor device (fig. 14, pFET left side; para. 0059) having one or more first semiconductor bodies (channel material nanosheets14P in pFET; para. 0059) extending in a first direction (horizontal direction) between a first source or drain region (pFET S/D SiGe regions 22S on the left; para. 0059) and a second source or drain region (22S on the right);
a second semiconductor device (nFET left side; para. 0063) having one or more second semiconductor bodies (14P in nFET) extending in the first direction (horizontal direction) between a third source or drain region ( nFET S/D region26S on the left; para. 0063) and a fourth source or drain region (26S on the right), the one or more first semiconductor bodies (14P in pFET) spaced vertically from the one or more second semiconductor bodies (14P in nFET) in a second direction (vertical direction) different from the first direction (horizontal direction);
a conductive contact structure (first S/D contact structures 36, SiGe region 25; para. 0085) adjacent to at least the second semiconductor device (14P in nFET), the conductive contact structure (36, 25) directly contacting a side surface of the third source or drain region (side surface of 26S) and having a first width at the third source or drain region (width of 36 between 26S), and the conductive contact structure (36, 25) directly contacting a top surface of the first source or drain region (top surface of 22S) and having a second width (width of 25) between the third source or drain region (26S) and the first source or drain region (22S), the second width (width of 25) being greater than the first width (width of 36 between 26S); and
a spacer structure (inner spacer 20; para. 0020) that extends between the one or more first semiconductor bodies and the one or more second semiconductor bodies (14P) in the second direction (vertical direction), the spacer structure (20) directly contacting at least one of the one or more first semiconductor bodies (14P in pFET) and at least one of the one or more second semiconductor bodies (14P in nFET).
Zhang fails to teach the conductive contact structure directly contacting a side surface and a bottom surface of the third source or drain region.
However, Rubin teaches the conductive contact structure (Rubin: fig. 6, interlayer via contact 280, silicide layers 275, underlying metallic interconnect 162, vertical contacts 154 and 152; para. 0070, similar to 36, 25 of Zhang) directly contacting a side surface (Rubin: side up surface) and a bottom surface (Rubin: side down surface as bottom surface) of the third source or drain region (Rubin: epitaxial source/drain layers 270; para. 0059, similar to 26S of Zhang).
Rubin and Zhang are considered to be analogous to the claimed invention because they are in the same field of semiconductor memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the conductive contact structure directly contacting a side surface and a bottom surface of the third source or drain region as taught by Rubin.
Doing so would realize interlayer via contacts effectively increase the volume to decreased resistance and higher performance of the interlayer via contact structures (Rubin: para. 0072).
Regarding claim 2, Zhang in view of Rubin further teaches the integrated circuit of claim 1, wherein the one or more first semiconductor bodies and the one or more second semiconductor bodies (Zhang: fig. 14, 14P) comprise nanoribbons including germanium, or silicon, or both germanium and silicon (Zhang: silicon; para. 0032).
Regarding claim 3, Zhang in view of Rubin further teaches the integrated circuit of claim 1, wherein the second width (Zhang: fig. 14, width of 25) of the conductive contact structure is substantially the same as a width of the first source or drain region (Zhang: width of 22S).
Regarding claim 4, Zhang in view of Rubin further teaches the integrated circuit of claim 1, wherein the conductive contact structure (Zhang: fig. 14, 36, 25) comprises a continuous body of a first material (Zhang: 36 has W or Cu; para. 0086) and a conductive layer (Zhang: 25) having a second material (Zhang: SiGe; para. 0084), the continuous body (Zhang: 36) extending on or adjacent the side surface of the third source or drain region (Zhang: side surface of 26S) to the conductive layer (Zhang: 25), and the conductive layer (Zhang: 25) being directly on the top surface of the first source or drain region (Zhang: top surface of 22S).
Regarding claim 5, Zhang in view of Rubin further teaches the integrated circuit of claim 4, wherein the first material (Zhang: fig. 14, 36 has W or Cu) comprises copper (Cu), ruthenium (Ru), tungsten (W), cobalt (Co), or molybdenum (Mo) (Zhang: W or Cu).
Zhang in view of Rubin as applied to claim 1 fails to teach the second material comprises Mo, W, vanadium (V), or niobium (Nb).
However, Rubin teaches the second material (Rubin: fig. 6, vertical contacts 152; para. 0070, similar to 25 of Zhang) comprises Mo, W, vanadium (V), or niobium (Nb) (Rubin: W; para. 0042).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the second material comprises Mo, W, vanadium (V), or niobium (Nb).
Doing so would realize a self-aligned silicide to decreased resistance and higher performance of the interlayer via contact structures (Rubin: para. 0072).
Regarding claim 7, Zhang in view of Rubin further teaches the integrated circuit of claim 4, wherein a residue of the second material (Zhang: fig. 14, 25) is directly on a portion of a sidewall of the spacer structure (Zhang: sidewall of 20).
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Rubin as applied to claim 4 above, and further in view of Zang et al. (US9831346).
Regarding claim 6, Zhang in view of Rubin teaches the integrated circuit of claim 4, including the conductive layer (Zhang: fig. 14, 25).
Zhang in view of Rubin fails to explicitly teach the conductive layer has a thickness between 0.5 nm and 2 nm.
However, Zang teaches the conductive layer (Zang: fig. 3D, source / drain silicide regions 710; col. 8, lin. 12, similar to 25 of Zhang) has a thickness less than 15nm (Zang: 710 is thinner than the source and drain regions 600, which have 15 nm; col. 6, lin. 47-48), which overlaps the thickness range between 0.5 nm and 2 nm.
Zang, Rubin and Zhang are considered to be analogous to the claimed invention because they are in the same field of semiconductor memory devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the thickness range from less than 15nm to between 0.5 nm and 2 nm.
Doing so would realize a self-aligned silicide increasing size/volume of contacts decreases resistance and improves performance. Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
The specification contains no disclosure of either the critical nature of the claimed thickness range for the conductive layer or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Rubin as applied to claim 1 above, and further in view of Lilak et al. (US 20200006329).
Regarding claim 8, Zhang in view of Rubin teaches the integrated circuit of claim 1.
Zhang in view of Rubin fails to explicitly teach a printed circuit board comprising the integrated circuit of claim 1.
However, Lilak teaches a printed circuit board (Lilak: fig. 5, motherboard 1002; para. 0055) comprising the integrated circuit (Lilak: integrated circuit structures; para. 0055, similar to the integrated circuit of Zhang) of claim 1.
Lilak, Rubin and Zhang are considered to be analogous to the claimed invention because they are in the same field of semiconductor memory devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add a printed circuit board as taught by Lilak.
Doing so would realize a computing system with multiple functions (Lilak: para. 0055).
Claims 9-13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Rubin and Lilak.
Regarding claim 9, Zhang teaches an electronic device (Abstract), comprising:
a first semiconductor device (fig. 14, pFET left side; para. 0059) having one or more first semiconductor nanoribbons (channel material nanosheets14P in pFET; para. 0059) extending in a first direction (horizontal direction) between a first source or drain region (pFET S/D SiGe regions 22S on the left; para. 0059) and a second source or drain region (22S on the right);
a second semiconductor device (nFET left side; para. 0063) having one or more second semiconductor nanoribbons (14P in nFET) extending in the first direction (horizontal direction) between a third source or drain region ( nFET S/D region26S on the left; para. 0063) and a fourth source or drain region (26S on the right), the one or more first semiconductor nanoribbons (14P in pFET) spaced vertically from the one or more second semiconductor nanoribbons (14P in nFET) in a second direction (vertical direction) different from the first direction (horizontal direction);
a conductive contact (first S/D contact structures 36, SiGe region 25; para. 0085) adjacent to at least the second semiconductor device (14P in nFET), the conductive contact (36, 25) having a first portion (top portion of 36) contacting a side surface of the third source or drain region (side surface of 26S), the first portion (top portion of 36) having a first width (width of 36 between 26S), and the conductive contact (36, 25) having a second portion (25) below the first portion (top portion of 36) and above a top surface of the first source or drain region (top surface of 22S), the second portion (25) having a second width (width of 25) between the third source or drain region (26S) and the first source or drain region (22S), the second width (width of 25) being greater than the first width (width of 36 between 26S); and
a spacer structure (inner spacer 20; para. 0020) that extends between the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons (14P) in the second direction (vertical direction), the spacer structure (20) directly contacting at least one of the one or more first semiconductor nanoribbons (14P in pFET) and at least one of the one or more second semiconductor nanoribbons (14P in nFET).
Zhang fails to teach the first portion of the conductive contact and the second portion of the conductive contact have a same material composition.
However, Rubin teaches the first portion (Rubin: fig. 6, interlayer via contact 280; para. 0070, similar to top portion of 36 of Zhang) of the conductive contact (Rubin: fig. 6, 280, silicide layers 275, underlying metallic interconnect 162, vertical contacts 154 and 152; para. 0070, similar to 36, 25 of Zhang) and the second portion (Rubin: 152, similar to 25 of Zhang) of the conductive contact (Rubin: 280, 275, 162, 154, 152) have a same material composition (Rubin: 280 has tungsten and 152 has W; para. 0042, 0069).
Rubin and Zhang are considered to be analogous to the claimed invention because they are in the same field of semiconductor memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the first portion of the conductive contact and the second portion of the conductive contact have a same material composition as taught by Rubin.
Doing so would realize interlayer via contacts effectively increase the volume to decreased resistance and higher performance of the interlayer via contact structures (Rubin: para. 0072).
In addition, Zhang in view of Rubin fails to explicitly teach a chip package comprising one or more dies, at least one of the one or more dies comprising the semiconductor structures.
However, Lilak teaches a chip package (Lilak: fig. 5, processor 1004 and communication chip 1006 integrated circuit die packaged; para. 0055) comprising one or more dies (Lilak: 1004, 1006), at least one of the one or more dies (Lilak: 1004, 1006) comprising the semiconductor structures (Lilak: integrated circuit structures; para. 0055, similar to the electronic device of Zhang).
Lilak, Rubin and Zhang are considered to be analogous to the claimed invention because they are in the same field of semiconductor memory devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add a chip package comprising one or more dies as taught by Lilak.
Doing so would realize a computing system with multiple functions (Lilak: para. 0055).
Regarding claim 10, Zhang in view of Rubin and Lilak further teaches the electronic device of claim 9, wherein the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons (Zhang: fig. 14, 14P) comprise germanium, silicon, or any combination thereof (Zhang: silicon; para. 0032).
Regarding claim 11, Zhang in view of Rubin and Lilak further teaches the electronic device of claim 9, wherein the second width (Zhang: fig. 14, width of 25) of the conductive contact is substantially the same as a width of the first source or drain region (Zhang: width of 22S).
Regarding claim 12, Zhang in view of Rubin and Lilak further teaches the electronic device of claim 9, wherein the conductive contact (Zhang: fig. 14, 36) comprises a first material (Zhang: 36 has W or Cu; para. 0086) and a conductive layer (Zhang: 25) having a second material (Zhang: SiGe; para. 0084), the conductive layer (Zhang: 25) being directly on the top surface of the first source or drain region (Zhang: top surface of 22S).
Regarding claim 13, Zhang in view of Rubin and Lilak further teaches the electronic device of claim 12, wherein the first material (Zhang: fig. 14, 36 has W or Cu) comprises copper (Cu), ruthenium (Ru), tungsten (W), cobalt (Co), or molybdenum (Mo) (Zhang: W or Cu), and the second material (Rubin: fig. 6, 152, similar to 25 of Zhang) comprises Mo, W, vanadium (V), or niobium (Nb) (Rubin: W; para. 0042).
Regarding claim 15, Zhang in view of Rubin and Lilak further teaches the electronic device of claim 12, wherein a residue of the second material (Zhang: fig. 14, 25) is directly on a portion of a sidewall of the spacer structure (Zhang: sidewall of 20).
Regarding claim 16, Zhang in view of Rubin and Lilak further teaches the electronic device of claim 9, further comprising a printed circuit board (Lilak: fig. 5, motherboard 1002; para. 0055), wherein the chip package (Lilak: 1004, 1006) is attached to the printed circuit board (Lilak: 1002).
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Rubin and Lilak as applied to claim 12 above, and further in view of Zang.
Regarding claim 14, Zhang in view of Rubin and Lilak further teaches the electronic device of claim 12, including the conductive layer (Zhang: fig. 14, 25).
Zhang in view of Rubin and Lilak fails to explicitly teach the conductive layer has a thickness between 0.5 nm and 2 nm.
However, Zang teaches the conductive layer (Zang: fig. 3D, source / drain silicide regions 710; col. 8, lin. 12, similar to 25 of Zhang) has a thickness less than 15nm (Zang: 710 is thinner than the source and drain regions 600, which have 15 nm; col. 6, lin. 47-48), which overlaps the thickness range between 0.5 nm and 2 nm.
Zang, Lilak, Rubin and Zhang are considered to be analogous to the claimed invention because they are in the same field of semiconductor memory devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the thickness range from less than 15nm to between 0.5 nm and 2 nm.
Doing so would realize a self-aligned silicide increasing size/volume of contacts decreases resistance and improves performance. Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
The specification contains no disclosure of either the critical nature of the claimed thickness range for the conductive layer or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Rubin.
Regarding claim 21, Zhang teaches an integrated circuit (Abstract) comprising:
a generic first source or drain region (Annotation fig. 14, nFET S/D region 26S on the left; para. 0063) at the ends of a first plurality of semiconductor bodies (channel material nanosheets 14P in nFET on the left; para. 0063);
a second source or drain region (26S on the right) at the ends of a second plurality of semiconductor bodies (14P in nFET on the right);
a generic third source or drain region (pFET S/D SiGe regions 22S; para. 0059) extending between a third plurality of semiconductor bodies (14P in pFET on the left; para. 0059) beneath the first plurality of semiconductor bodies (14P in nFET on the left) and a fourth plurality of semiconductor bodies (14P in pFET on the right) beneath the second plurality of semiconductor bodies (14P in nFET on the right);
a conductive contact (first S/D contact structures 36, SiGe region 25; para. 0085) that contacts a side surface of the first source or drain region (26S on the left), a side surface of the second source or drain region (26S on the right), and a top surface of the generic third source or drain region (22S), wherein the conductive contact (36, 25) has a first width (width of 36 between 26S) between the first source or drain region and the second source or drain region (26S) and a second width (width of 25) at the top surface of the generic third source or drain region (top surface of 22S), the second width (width of 25) being greater than the first width (width of 36 between 26S);
a first spacer structure (inner spacer 20 on the left; para. 0020) that extends between the first plurality of semiconductor bodies (14P in pFET on the left) and the third plurality of semiconductor bodies (14P in pFET on the left), the first spacer structure (20) directly contacting at least one of the first plurality of semiconductor bodies (14P in nFET on the left) and at least one of the third plurality of semiconductor bodies (14P in pFET on the left); and
a second spacer structure (20 on the right) that extends between the second plurality of semiconductor bodies (14P in nFET on the right) and the fourth plurality of semiconductor bodies (14P in pFET on the right), the second spacer structure (20) directly contacting at least one of the second plurality of semiconductor bodies (14P in nFET on the right) and at least one of the fourth plurality of semiconductor bodies (14P in pFET on the right).
Zhang fails to explicitly teach the generic first source or drain region at the ends of a first plurality of semiconductor bodies,
the generic third source or drain region extending between a third plurality of semiconductor bodies and a fourth plurality of semiconductor bodies,
the conductive contact does not extend into any portion of the third source or drain region.
However, Rubin teaches the generic first source or drain region (Rubin: fig. 6, epitaxial source/drain layers 270 on M3; para. 0059, similar to 26S of Zhang) at the ends of a first plurality of semiconductor bodies (Rubin: semiconductor layers N1, N2, N3, N4 and N5 on nanosheet FET devices M3; para. 0035, 0070, similar to 14P of Zhang).
the generic third source or drain region (Rubin: source/drain layer 141; para. 0035, similar to 22S of Zhang) extending between a third plurality of semiconductor bodies (Rubin: nanosheet or nanowire of FinFET devices M1; para. 0039, 0070, similar to left pFET of Zhang) and a fourth plurality of semiconductor bodies (Rubin: nanosheet or nanowire of FinFET device M2; para. 0039, 0070, similar to right pFET of Zhang),
the conductive contact (interlayer via contact 280, silicide layers 275, underlying metallic interconnect 162, vertical contacts 154 and 152; para. 0070, similar to 36, 25 of Zhang) does not extend into any portion of the third source or drain region (Rubin: 141).
Rubin and Zhang are considered to be analogous to the claimed invention because they are in the same field of semiconductor memory.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange the generic first source or drain region at the ends of a first plurality of semiconductor bodies and the generic third source or drain region extending between a third plurality of semiconductor bodies and a fourth plurality of semiconductor bodies, the conductive contact does not extend into any portion of the third source or drain region.
Doing so would realize a structure share the interlayer via contacts that the devices can be positioned closer together so take up less area on the substrate, and allows for increased circuit density and a self-aligned silicide to decreased resistance and higher performance of the interlayer via contact structures (Rubin: para. 0002, 0072).
Regarding claim 22, Zhang in view of Rubin further teaches the integrated circuit of claim 21, wherein the conductive contact (Zhang: fig. 14, 36, 25) comprises a continuous body (Zhang: 36) of a first material (Zhang: 36 has W or Cu; para. 0086) and a conductive layer (Zhang: 25) having a second material (Zhang: SiGe; para. 0084), the continuous body (36) of the first material extending on or adjacent the side surface of the first source or drain region (side surface of 26S), and the conductive layer (Zhang: 25) being directly on the top surface of the third source or drain region (Zhang: top surface of 22S).
Regarding claim 23, Zhang in view of Rubin further teaches the integrated circuit of claim 22, wherein the first material (Rubin: Rubin: fig. 6, 280, similar to 36 of Zhang, has metallic fill material) comprises copper Cu, Ru, W, Co, or Mo, (Rubin: W, Cu; para. 0041) and the second material (Rubin: 152, similar to 25 of Zhang) comprises Mo, W, V, or Nb (Rubin: W; para. 0042).
Regarding claim 24, Zhang in view of Rubin further teaches the integrated circuit of claim 21, wherein the conductive contact (Rubin: fig. 6, interlayer via contact 280, silicide layers 275, underlying metallic interconnect 162, vertical contacts 154 and 152; para. 0070, similar to 36, 25 of Zhang) also contacts top and bottom surfaces (Rubin: 275 contacts the top side surface of the top apex and bottom side surface of the bottom apex of 270 on M3 and M4) of both of the first source or drain region and second source or drain region.
Response to Arguments
Applicant’s arguments with respect to claims 1-16 rejected under 35 U.S.C.102 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed on Dec. 1st, 2025 with respect to claims 21-24 have been fully considered but they are not persuasive.
With respect to pages 7-9 of applicant’s response of claim 21 is rejected under 35 U.S.C.103.
Applicant submits "Rubin discloses an entirely different semiconductor structure compared to Zhang. Accordingly, even if the Examiner determines that the noted claim features are disclosed separately in Rubin, those features cannot be incorporated into the structure of Zhang."
The examiner respectfully disagrees.
The semiconductor structures of Rubin and Zhang are similar, and both are vertically stacked field effect transistors for memory devices. The interlayer contact structure (280, 275, 162, 154 and 152) of Rubin are similar to the interlayer contact structure (36, 25) of Zhang, both connect two S/D from the upper level to one S/D in the lower level. In addition, as cited in fig. 6 and para. 0072 of Rubin, the conductive contact (280, 275, 162, 154 and 152, similar to 36, 25 of Zhang) does not extend into any portion of the third source or drain region (141) to realize a self-aligned silicide to decreased resistance and higher performance of the interlayer via contact structures.
As result, given a broadest reasonable interpretation, Zhang in view of Rubin teaches all limitations of claims 21. Details of rejections are discussed above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Basker et al. (US 9711501) teaches the conductive contact does not extend into any portion of the third source or drain region.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818