DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/ has been entered.
Status of the Claims
Claims 1-20 are pending in the application and are currently being examined. Claims 1, 7, and 14 have been amended. Claims 7-20 have been withdrawn per the 1/29/2025 restriction election. No new claims have been added. No claims have been cancelled.
Response to Arguments
Applicant's arguments filed 3/ have been fully considered but they are not persuasive.
Applicant asserts that Chiang teaches an angle away from the first upper device as referenced in an annotated figure on pages 8 and 9 of the Remarks. While Examiner is provided a black and white annotated figure, the written description is clear enough to determine where the reference colors should be. With reference to the angle of the surface being angled away from the first upper device, Examiner respectfully disagrees. The current claim language does not specify where this angle is measured in reference to, only that it is measured from a vertical. As such, in the annotated Figure 24 provided below, Chiang does teach an angle of the contact plug angled toward the first upper device.
With regard to the argument on page 8 with the annotated Figure on page 9, Applicant asserts that the plug of Chiang does not cover “a top surface of the first lower device”. Again Examiner respectfully disagrees with the assertation. The language of the currently amended claim 1 does not necessitate that the entirety of the top surface of the first lower device be covered, which appears to be the argument of the Applicant. Under BRI, any covering of the top surface would read on the limitation “the angled via covers a top surface of the first lower device”. If the claim had language specifying the entirety of the top surface of the first lower device, Examiner would agree that Chiang does not teach that limitation. However, as the amended claim 1 is presently written, Examiner argues that Chiang teaches the limitations of claim 1.
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Regarding the argument on the allowability of the dependent claims, as they rely on the arguments set forth for independent claim 1, they are still rejected for the reasons above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiang et al. (US 2020/0135634 A1, hereafter Chiang).
Regarding claim 1, in Fig. 24 Chiang teaches a semiconductor structure (10, [0022]), comprising:
a first lower device (50, [0032]) at a lower level (region between Line1 and Line2 in annotated Fig. 24) of the semiconductor structure (10);
a first upper device (portion of 86, [0049] located above Line3 in annotated Fig. 24) at an upper level (region above Line3 in annotated Fig. 24) of the semiconductor structure (10),
a second upper device (96, [0052]) laterally adjacent to the first upper device (portion of 86 in upper level) at the upper level, wherein the upper level is vertically above the lower level (as depicted in annotated Fig. 24);
an angled via (region of 86 located between Line2 and Line3 in annotated Fig. 24) electrically connecting the first lower device (50) and the first upper device, wherein the first lower device (50) is laterally between the first upper device and the second upper device, and the angled via covers a top surface of the first lower device (50) (the via covers a portion of a top surface of the first lower device, under BRI this means the via covers the top surface); and
an angled surface (rightmost boundary of element 86) from a top of the first upper device along the angled via to a top of the first lower device (50) comprising an angle angled toward the first upper device relative to a vertical axis (see larger annotated Fig. 24) such that a first lateral distance (see larger annotated Fig. 24) from the top of the first upper device (86) to the second upper device (96) is greater than a second lateral distance (see larger annotated Fig. 24) from the top of the first lower device (50) to the second upper device (96).
The second annotated Fig. 24 has a line extending up from a boundary of the first lower device (50). This line shows a portion of the second upper device (96) in line with said boundary, there also is a portion of the second upper device (96) vertically overlapping the first lower device (50). This would make the second lateral distance from the top of the first lower device (50) to the second upper device (96) equal to zero, which is definitely less than the first lateral distance.
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Regarding claim 2, in Fig. 24 Chiang teaches the semiconductor structure of claim 1, wherein the first lower device is a buried power rail (50, [0032]).
Regarding claim 3, in Fig. 24 Chiang teaches the semiconductor structure of claim 2, wherein the first upper device (portion of 86, [0049] located above Line3 in annotated Fig. 24) is a source/drain.
Regarding claim 4, in Fig. 24 Chiang teaches the semiconductor structure of claim 1, wherein a distance between the angled via (region of 86 located between Line2 and Line3 in annotated Fig. 24) and the second upper device (96, [0052]) is at least as great as a distance between the angled via and a second lower device (see annotated Fig. 24) laterally adjacent to the first lower device (50, [0032]) at the lower level (region between Line1 and Line2 in annotated Fig. 24). As the phrase “a distance” is vague, any distance can be selected such that the distance from the angled via and the second upper device is at least equidistant compared to the distance from the angled via and the second lower device.
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Regarding claim 5, in Fig. 24 Chiang teaches the semiconductor structure of claim 1, wherein the first lower device (50, [0032]) is a first wire line of a lower back end of line (BEOL) metal layer (region between Line1 and Line2 in annotated Fig. 24) and the first upper device (portion of 86, [0049] located above Line3 in annotated Fig. 24) is a wire line of an upper BEOL metal layer (region above Line3 in annotated Fig. 24).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang in view of Xia et al. (US 2009/0093100 A1, hereafter Xia).
Regarding claim 6, in Fig. 24 Chiang teaches the semiconductor structure of claim 5. Chiang fails to teach a second wire line at the lower BEOL metal layer and a straight via electrically connecting the second wire line and the second upper device.
However, in Fig. 1I Xia teaches a device similar to Chiang with an upper layer and lower layer (see analogous Line1a, Line2a, and Line3a in annotated Fig. 1I) with a first upper device (UD1 in annotated Fig. 1I, 121, [0046]), second upper device (UD2 in annotated Fig. 1I, 121), first lower device (LD1 in annotated Fig. 1I, 121), and second lower device (UD2 in annotated Fig. 1I, 121). Xia teaches teach a second wire line (LD2, 121) at the lower BEOL metal layer (region between Line1a and Line2a in annotated Fig. 1I) and a straight via (V2 in annotated Fig. 1I) electrically connecting the second wire line (LD2) and the second upper device (UD2). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Chiang to include more interconnect devices, as shown in Xia to get the expected result of densely packed metal structures within a device as taught by Xia [0021].
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892