DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/16/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (20190363048) in view of Chanemougame et al. (20200075456)
Regarding Claim 1, in Fig. 4C and paragraphs 0046-0049, 0051, 0054, 0073, 0082 and 0085, Zhao et al discloses a semiconductor structure comprising: a first dielectric 415 positioned on a first metal contact 409; a second dielectric 403 laterally surrounding the first dielectric 415 (see the recess portion of element 415) and the first metal contact 409; and a second metal contact 427/421 present extending through the first dielectric 415 into contact with the first metal contact 409. Zhao et al. fails to disclose the newly added “same elevation” limitation. However, Chanemougame et al. discloses a semiconductor device where in Fig. 8 (elements 30/22/26/48) the required same elevation limitation (between elements 22 and 30) is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required “same elevation” limitation in Zhao et al. as taught by Chanemougame et al.in order to have lower directional resistance (see paragraphs 0014 and 0023 of Chanemougame et al).
Regarding Claim 2, in Zhao et al., the first metal contact 409 has a first length dimension that is greater than a first width dimension for the first metal contact (see the interface region around element 421).
Regarding Claim 3, in Zhao et al., the second metal contact 427 has a second length dimension that is less than the first length dimension of the first metal contact, and the second metal contact has a second width dimension that is substantially equal to the first width dimension of the first metal contact (see around the interface region around element 421).
Regarding Claim 4, in Zhao et al., the first metal contact 409 and the second metal contact 421 extend through a via level 421 into contact with a metal line of an underlying first metal line level.
Regarding Claim 5, in Zhao et al., via level 421 is positioned underlying an second metal line level 427, wherein a first interface between the first dielectric and the first metal contact is vertically offset (see the interface region around element 421) from a second interface of the second dielectric 403 and the second metal line level 427.
Regarding Claim 6, in Zhao et al., a second metal line level 427 is present overlying a via level 421 including the first and second metal contact, the second metal line level including a second line level dielectric 403/413 having a line trench filled with a seed layer and a metal fill 409, wherein a portion of the seed layer and metal fill extends from the second metal line level into the via level 421 to provide the second metal contact 427.
Regarding Claim 7, in Zhao et al., in Fig. 4C and paragraphs 0046-0049, 0051, 0054, 0073, 0082 and 0085, Zhao et al discloses a semiconductor structure comprising: a first metal line level having a first metal line 409 ;a second metal line level having a second metal line 427; and a via line 421 level present between the first and second metal line levels, the via line level including via interlevel dielectric 403 surrounding a via stack 409/415/421 including an interface metal portion 421 that is in contact with the first metal line, a via intralevel dielectric 415 on the interface metal portion, and a cap metal 421 portion in contact with the second metal line and extending through the via intralevel dielectric 415 into contact with the interface metal portion (interface between 421 and 409), wherein a length of the interface metal portion of the via is greater than a width of the interface metal portion of the via stack (see the shaped portion at the interface between 421 and 409). Zhao et al. fails to disclose the newly added “same elevation” limitation. However, Chanemougame et al. discloses a semiconductor device where in Fig. 8 (elements 30/22/26/48) the required same elevation limitation (between elements 22 and 30) is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required “same elevation” limitation in Zhao et al. as taught by Chanemougame et al.in order to have lower directional resistance (see paragraphs 0014 and 0023 of Chanemougame et al).
Regarding Claim 8, in Zhao et al., a first cap dielectric layer 415 is present between the first metal line level and the via line level.
Regarding Claim 9, in Zhao et al., a second cap dielectric layer 415 (namely the recessed portion of element 415) is present between the second metal line level and the via line level.
Regarding Claim 10, in Zhao et al., the length of the interface metal portion of the via is substantially parallel to a metal line length for the first metal line.
Regarding Claim 11, in Zhao et al., the cap metal portion (the shaped portion at the interface of 427 and 409 around element 421) has a length dimension that is less than the length dimension of the interface metal portion of the via stack, and the cap metal portion has a width dimension that is substantially equal to the width dimension of the interface metal portion of the via stack.
Regarding Claim 12, in Zhao et al., the width dimension of the interface metal portion of the via stack is substantially equal to a metal line width for the first metal line.
Regarding Claim 13, in Zhao et al., the second metal line level 427 includes a second line level dielectric having a line trench filled with a seed layer and a metal fill, wherein a portion of the seed layer and metal fill extends from the second metal line level into the via level to provide the cap metal portion.
Regarding Claim 14, in Zhao et al., the interface metal portion (shaped portion around element 421) has a width substantially equal to a metal line width for the first metal line, wherein the length ofthe interface metal portion for the via is greater than a width of the interface metal portion for the via.
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 1/26/2026