DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 29 January 2026 has been entered.
Claim and Specification Status
The Examiner acknowledges the amendments to claim 1, 6, 11, 13, 21, 23, 25 and 27 in the Applicant’s response dated 21 October 2025. The claim amendments and the Applicant’s accompanying comments have been addressed below.
The Examiner acknowledges the renumbering of claims 27 and 28 in the Applicant’s response dated 21 October 2025. Previously presented claim 27 will be entered as renumbered claim 26 and previously presented claim 28 will be entered as renumbered claim 27.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-7, 12-13 and 20-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tung Ying Lee et al. (US 2021/0336138 A1; hereinafter “Lee”).
Regarding Claim 1, Lee teaches a phase change memory structure comprising:
a bottom electrode (50, Fig. 16, para [014] describes a bottom electrode 50);
a top electrode having a low resistivity (56, Fig. 16, para [0049] and para [0050] describe a top electrode 56 comprised of a conductive material wherein a conductive material may have a low resistivity);
a first phase change material between the bottom electrode and the top electrode (54, Fig. 16, para [0029] describes a phase change material layer 54);
a first dielectric surrounding the first phase change material (42, Fig. 16, para [0022] describes forming a dielectric layer 42 surrounding the first phase change material 54) and having a selective adhesion to the first phase change material stack versus the top electrode (42, Fig. 16, para [0022] describes wherein the first dielectric layer 42 may be comprised of a nitride or silicon oxide such as the first dielectric of the instant application, further wherein para [0044] describes the first phase change material may be comprised of a chalcogenide material such as GST such as the phase change material of the instant application, para [0049] and para [0026] describes wherein the top electrode may be comprised of a conductive material including tungsten such as the top electrode of the instant application, please see MPEP 2112.01 (I) wherein the structure of the first dielectric layer, phase change material layer, and top electrode as recited by Lee is substantially identical to that of the claims therefore claimed properties, such as adhesion properties, or functions are presumed to be present);
a second dielectric (62, Fig. 16, para [0053] describes forming a dielectric layer 62), deposited as a backfill on an upper surface of the first dielectric surrounding the top electrode (62, Fig. 16, para [0053] describes wherein second dielectric 62 is formed on an upper surface of the first dielectric 42 and surrounds top electrode 56), and having a lower surface disposed higher than a top surface of the first phase change material (LS and US, annotated Fig. 16 depicts wherein a lower surface of the second dielectric LS is higher than a top surface of the phase change material 54) , the second dielectric having selective adhesion to the top electrode as compared to the first phase change material (62, Fig. 16, para [0053] and para [0018] describes wherein second dielectric 62 may be formed of a low-k dielectric material such as the second dielectric of the instant application, further wherein para [0044] describes the first phase change material may be comprised of a chalcogenide material such as GST such as the phase change material of the instant application, para [0049] and para [0026] describes wherein the top electrode may be comprised of a conductive material including tungsten such as the top electrode of the instant application, please see MPEP 2112.01 (I) wherein the structure of the second dielectric layer, phase change material stack, and top electrode as recited by Lee is substantially identical to that of the claims therefore claimed properties, such as adhesion properties, or functions are presumed to be present);
a first metal feature contacting the bottom electrode (40, Fig. 16, para [0020] describes a metallization layer 40 which is in contact with bottom electrode 50); and
a second metal feature extending through the second dielectric and contacting the top electrode (64, Fig. 16, para [0053] describes a metallization layer 64 which is in contact with top electrode 56).
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Regarding Claim 2, Lee teaches the phase change memory structure of Claim 1, further comprising a first memristive stack including the first phase change material (660, Fig. 16, para [0014] describes PCRAM cells 60 further including the first phase change material 54).
Regarding Claim 3, Lee teaches the phase change memory structure of Claim 1, wherein the first dielectric is a silicon nitride material (42, Fig. 16, para [0022] describes wherein the first dielectric 42 may be a silicon oxynitride material).
Regarding Claim 4, Lee teaches the phase change memory structure of Claim 1, wherein the second dielectric is a low-K dielectric material, different than the first dielectric (62, Fig. 16, para [0053] and para [0022] describes wherein second dielectric 62 may be formed of dielectric material similar to those previously described for first dielectric 42 wherein said process describes a different process than the silicon oxynitride of first dielectric layer 42 and further includes a low-k dielectric material).
Regarding Claim 5, Lee teaches the phase change memory structure of Claim 1, wherein the second dielectric thermally isolates the first phase change material from an adjacent second phase change material (62, Fig. 16 depicts wherein second dielectric layer 62 thermally isolates top electrodes of a first phase change material and an adjacent second phase change material wherein upon thermally isolating the top electrodes the second dielectric would further thermally isolate the adjacent phase change materials).
Regarding Claim 6, Lee teaches the phase change memory structure of Claim 1, further comprising a liner disposed on the first phase change material (56, Fig. 16, para [0049] describes wherein the top electrode 56 includes a barrier layer), between the first phase change material and the top electrode (56, Fig. 16, para [0049] describes wherein the top electrode 56 includes a barrier layer between phase change material 54 and a conductive portion of the top electrode),
wherein a height of the first dielectric is at least sufficient to cover sidewalls of the first phase change material (42, Fig. 16 depicts wherein a height of the first dielectric layer 42 is sufficient to cover the sidewalls of the first phase change material 54).
Regarding Claim 7, Lee teaches the phase change memory structure of Claim 6, wherein the liner is at least one of an adhesion layer, an atomic barrier layer, and a thermal barrier layer (para [0025] and para [0049] describes wherein barrier layer of top electrode 56 may be formed using the same atomic layer deposition process as barrier layer 46 resulting in an atomic barrier layer).
Regarding Claim 12, Lee teaches the phase change memory structure of Claim 1, further comprising a second nitride liner on at least one surface of the bottom electrode (46, Fig. 14, para [0025] describes wherein a barrier layer 46 formed of a metal nitride material may cover at least one surface of bottom electrode 50).
Regarding Claim 13, Lee teaches the phase change memory structure of Claim 12, wherein the second nitride liner is a metal-nitride adhesion layer exposing a top surface of the bottom electrode (46, Fig. 14, para [0025] describes wherein a barrier layer 46 formed of a metal nitride material may cover at least one surface of bottom electrode 50 and further exposes a top surface of the bottom electrode 50 wherein the structure of the bottom electrode, phase change material stack, and metal nitride liner as recited by Lee is substantially identical to that of the claims therefore claimed properties, such as adhesion properties, or functions are presumed to be present (please see MPEP 2112.01 (I))).
Regarding Claim 20, Lee teaches the phase change memory structure of Claim 1, wherein the first dielectric is a silicon nitride or a silicon dioxide (42, Fig. 16, para [0022] describes wherein the first dielectric 42 may be a silicon oxynitride material), and the second dielectric is a low-K dielectric material, different than the first dielectric (62, Fig. 16, para [0053] and para [0022] describes wherein second dielectric 62 may be formed of dielectric material similar to those previously described for first dielectric 42 wherein said process describes a different process than the silicon oxynitride of first dielectric layer 42 and further includes a low-k dielectric material).
Regarding Claim 21, Lee teaches the phase change memory structure of Claim 1,
wherein the first dielectric fills a space between extends from the first phase change material and to a second phase change material adjacent to first phase change material (42, annotated Fig. 16 depicts wherein the first dielectric 42 fills a space extending between the first phase change material FPCM and a second phase change material SPCM adjacent to the first phase change material), and
wherein the second dielectric is disposed on the first dielectric and the top electrode (62, Fig. 16, para [0053] describes wherein second dielectric 62 is formed on the first dielectric 42 and top electrode 56).
Regarding Claim 22, Lee teaches the phase change memory structure of Claim 1, wherein the first dielectric is an encapsulation filling a space between the first phase change material and a second phase change material adjacent to first phase change material (42, annotated Fig. 16 depicts wherein the first dielectric 42 fills a space extending between the first phase change material FPCM and a second phase change material SPCM adjacent to the first phase change material) and including an overburden portion extending higher than a height of the first phase change material and the second phase change material (42, annotated Fig. 16 depicts wherein first dielectric 42 includes an overburden portion extending above the heights of the first phase change material FPCM and second phase change material SPCM), and
wherein the second dielectric is disposed on the first dielectric and surrounding the top electrode (62, Fig. 16, para [0053] describes wherein second dielectric 62 is formed on the first dielectric 42 and surrounds top electrode 56).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 23-25 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Tung Ying Lee et al. (US 2021/0336138 A1; hereinafter “Lee”) in view of Injo Ok et al. (US Patent 10,741,756 B1; hereinafter “Ok”).
Regarding Claim 9, Lee discloses the phase change memory structure of Claim 1, further comprising:
a first interlevel dielectric surrounding the first metal feature (36, Fig. 16, para [0020] describes dielectric layer 36 surrounding the first metal feature 40); and
a third metal feature in the first interlevel dielectric (40, Fig. 16, para [0020] describes wherein metallization layer has a third metal feature as shown in Fig. 16).
Lee fails to explicitly disclose the phase change memory structure of Claim 1, further comprising:
a second interlevel dielectric surrounding the bottom electrode; and a fourth metal feature in the first dielectric, the second dielectric, and the second interlevel dielectric, and contacting the third metal feature.
However, Ok teaches a similar phase change memory device as Lee, further comprising:
a first interlevel dielectric surrounding the first metal feature (120 and 130, Fig. 15, column 4, lines 26-38 describes the process of forming a first interlayer dielectric 120 on the substrate in which the lower conductive pads 130, (further described as metal features in column 4, lines 54-55) are formed);
a second interlevel dielectric surrounding the bottom electrode (140 and 150, Fig. 15, column 4, lines 63-67 describes forming the isolation layer 140, acting as a second interlayer dielectric, surrounding the bottom electrode 150 (see annotated Fig. 15 below));
a third metal feature in the first interlevel dielectric (130, Fig. 15, column 4, lines 54-55 describe the conductive pads 130 as metal features, wherein the middle conductive pad is the third metal feature (see annotated Fig. 15 below)); and
a fourth metal feature in the first dielectric, the second dielectric, and the second interlevel dielectric, and contacting the third metal feature (295, Fig. 15, column 10, lines 61-67 and column 11, lines 1-8 describes a conductive via 295, contacting the upper conductive pad 290 (second metal feature), and the third metal feature 130, wherein the conductive via can be made from a metal, and is in the first dielectric 170, the second dielectric 280, and the second interlevel dielectric 140 (see annotated Fig. 15 below)).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Lee and Ok to further disclose a phase change memory device which comprises a first interlevel dielectric, a second interlevel dielectric, and third and fourth metal features, in order to electrically connect the upper metal features with the lower metal features for the further advantage of providing current to the device in order to provide read or write signals for the memory unit (Ok, column 10, lines 55-60), the first and second interlevel dielectric layers further providing the advantage of protecting underlying layers during the etching process (Ok, column 3, lines 31-50).
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Regarding Claim 23, Lee discloses a phase change memory structure comprising:
a first interlevel dielectric layer (36, Fig. 16, para [0020] describes a first interlevel dielectric layer 36);
a first metal feature disposed in the first interlevel dielectric layer (40, Fig. 16, para [0020] describes a metallization layer 40 disposed in the first interlevel dielectric layer 36);
a bottom electrode contacting the first metal feature (50, Fig. 16, para [014] describes a bottom electrode 50 which can be seen contacting first metal feature 40)
a top electrode formed of tungsten (56, Fig. 16, para [0026], para [0049] and para [0050] describe a top electrode 56 comprised of a conductive material wherein a conductive material may be a same material of conductive material 48 which may be tungsten);
a first memristive stack disposed between the bottom electrode and the top electrode (54, Fig. 16, para [0029] describes a phase change material layer 54 disposed between the bottom electrode 50 and top electrode 56);
a first dielectric forming a selective encapsulation surrounding the first memristive stack (42, Fig. 16, para [0022] describes forming a dielectric layer 42 encapsulating the first phase change material 54)
wherein the first dielectric is formed of a silicon nitride or a silicon dioxide (42, Fig. 16, para [0022] describes wherein the first dielectric 42 may be a silicon oxynitride material);
a second dielectric (62, Fig. 16, para [0053] describes forming a dielectric layer 62) disposed as a backfill on an upper surface of the first dielectric and surrounding the top electrode (62, Fig. 16, para [0053] describes wherein second dielectric 62 is formed on an upper surface of the first dielectric 42 and surrounds top electrode 56), and having a lower surface disposed higher than a top surface of the first phase change material (LS and US, annotated Fig. 1 depicts wherein a lower surface of the second dielectric LS is higher than a top surface of the phase change material 54); and
a second metal feature disposed in the second dielectric and contacting the top electrode (64, Fig. 16, para [0053] describes a metallization layer 64 which is in contact with top electrode 56).
Lee fails to explicitly disclose phase change memory structure comprising a second interlevel dielectric layer disposed on the first interlevel dielectric layer; a bottom electrode disposed in the second interlevel dielectric layer and contacting the first metal feature; a first dielectric disposed on the second interlevel dielectric layer and forming a selective encapsulation surrounding the first memristive stack; and wherein the second dielectric is formed of a carbon-doped silicon oxide.
However, Ok teaches a similar phase change memory device as Lee, further comprising:
a second interlevel dielectric layer disposed on the first interlevel dielectric layer (140, Fig. 5, column 4, lines 63-67 describe an isolation layer 140 formed on a first interlevel dielectric layer 120);
a bottom electrode (150, Fig. 5, column 5, lines 36-45 describe a bottom electrode 150) disposed in the second interlevel dielectric layer and contacting the first metal feature (150, Fig. 5, column 5, lines 36-45 describe a bottom electrode 150 disposed in the second interlevel dielectric layer 140 contacting a first metal feature 130);
a first dielectric disposed on the second interlevel dielectric layer and forming a selective encapsulation surrounding the first memristive stack (170, Fig. 13, column 6 lines 14-19 describe a dielectric fill layer 170 disposed on the second interlevel dielectric 140 which can be seen encapsulating the phase change material stack 210); and
wherein the second dielectric is formed of a carbon-doped silicon oxide (280, Fig. 15, column 10, lines 44-54 describe a second interlayer dielectric layer (ILD), which can be seen surrounding the top electrode in Fig. 15, being comprised of a dielectric material, including carbon doped silicon oxide (SiO:C)).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Lee and Ok to further disclose a phase change memory device which includes a second interlevel dielectric in which a bottom electrode may be formed in and a first dielectric may be disposed on in order to provide the advantage of providing for an isolation layer that may act as a diffusion barrier and provide electrical isolation for the bottom electrodes (Ok, column 5, lines 1-4) and to further disclose a second dielectric layer comprising a low-k material such as carbon doped silicon oxide as taught by Ok to produce the predictable result of reducing current leakage to other components within the device.
Regarding Claim 24, the combination of Lee and Ok teach the phase change memory structure of Claim 23, wherein the second dielectric fills a space between the top electrode and an adjacent top electrode (Lee, 62, Fig. 16 depicts wherein the second dielectric 62 fills a space between the top electrode 56 of the first memristive stack FPCM and adjacent top electrode of the second memristive stack SPCM from annotated Fig. 16) and thermally isolates the first memristive stack from a second memristive stack adjacent to the first memristive stack (Lee, 62, Fig. 16 depicts wherein second dielectric layer 62 thermally isolates top electrodes of a first phase change material and an adjacent second phase change material wherein upon thermally isolating the top electrodes the second dielectric would further thermally isolate the adjacent phase change materials).
Regarding Claim 25, the combination of Lee and Ok teach the phase change memory structure of Claim 23, further comprising a liner disposed on the first memristive stack (Ok, 56, Fig. 16, para [0049] describes wherein the top electrode 56 includes a barrier layer) and separating the first memristive stack and the top electrode (Lee, 56, Fig. 16, para [0049] describes wherein the top electrode 56 includes a barrier layer between first memristive stack 54 and a conductive portion of the top electrode),
wherein the first dielectric is an encapsulation including an overburden portion extending higher than a height of the first memristive stack to surround the liner (Lee, 42, Fig. 16 depicts wherein a height of the first dielectric layer 42 includes an overburden portion extending higher than the height of the first memristive stack 54 and would therefore surround the barrier layer liner of the top electrode).
Regarding Claim 27, Lee discloses a phase change memory structure comprising:
a first interlevel dielectric layer (36, Fig. 16, para [0020] describes a first interlevel dielectric layer 36);
a plurality of first metal features disposed in the first interlevel dielectric layer (40, Fig. 16, para [0020] describes a metallization layer 40 including a plurality of metal features disposed in the first interlevel dielectric layer 36);
a plurality of bottom electrodes contacting the plurality of first metal features, respectively (50, Fig. 16, para [014] describes bottom electrode 50 wherein a plurality of bottom electrodes in Fig. 16 contact the plurality of first metal features 40);
a plurality of top electrodes formed of tungsten (56, Fig. 16, para [0026], para [0049] and para [0050] describe top electrodes 56 formed on at least first memristive stack FPCM and second memristive stack SPCM from annotated Fig. 16 above, comprised of a conductive material wherein a conductive material may be a same material of conductive material 48 which may be tungsten;
a plurality of memristive stacks disposed between the plurality of bottom electrodes and the plurality of top electrodes, respectively (FPCM and SPCM, Fig. 16, para [0029] describes a first phase change material layer FPCM and a second phase change material layer SPCM disposed between the bottom electrodes 50 and top electrodes 56);
a first dielectric (42, Fig. 16, para [0022] describes forming a dielectric layer 42),
wherein the first dielectric is formed of a silicon nitride or a silicon dioxide (42, Fig. 16, para [0022] describes wherein the first dielectric 42 may be a silicon oxynitride material), fills an entire space between plurality of memristive stacks (42, annotated Fig. 16 depicts wherein the first dielectric 42 fills a space extending between the first phase change material FPCM and a second phase change material SPCM adjacent to the first phase change material), and includes an overburden portion extending higher than a height of the plurality of memristive stacks (42, annotated Fig. 16 depicts wherein first dielectric 42 includes an overburden portion extending above the heights of the first phase change material FPCM and second phase change material SPCM);
a second dielectric (62, Fig. 16, para [0053] describes forming a dielectric layer 62) disposed as a backfill on the overburden portion of the first dielectric and surrounding the plurality of top electrodes (62, Fig. 16, para [0053] describes wherein second dielectric 62 is formed on an upper surface of the first dielectric 42 and surrounds top electrodes 56 above the plurality of memristive stacks), and having a lower surface disposed higher than a top surface of the plurality of memristive stacks (LS and US, annotated Fig. 16 depicts wherein a lower surface of the second dielectric LS is higher than a top surface of the memristive stacks FPCM and SPCM),
wherein the second dielectric fills a space between the plurality of top electrodes (62, Fig. 16 depicts wherein the second dielectric 62 fills a space between the top electrode 56 of the first memristive stack FPCM and adjacent top electrode of the second memristive stack SPCM from annotated Fig. 16), and has a higher thermal resistivity than the first dielectric (62, Fig. 16, please see MPEP 2112.01 (I) wherein the structure of the second dielectric layer 62, described in para [0053] and para [0018], and the structure of the first dielectric layer 42, described in para [0022], as recited by Lee is substantially identical to that of the claims therefore claimed properties, such as thermal resistivity, or functions are presumed to be present); and
a plurality of second metal features disposed in the second dielectric and contacting the plurality of top electrodes, respectively (64, Fig. 16, para [0053] describes a metallization layer 64 comprising multiple metal features which are in contact with top electrodes 56).
Lee fails to explicitly disclose a second interlevel dielectric layer disposed on the first interlevel dielectric layer; a plurality of bottom electrodes disposed in the second interlevel dielectric layer and contacting the plurality of first metal features, respectively; a first dielectric disposed on the second interlevel dielectric layer, wherein the second dielectric is formed of a carbon-doped silicon oxide.
However, Ok teaches a similar phase change memory device as Lee, further comprising:
a second interlevel dielectric layer disposed on the first interlevel dielectric layer (140, Fig. 5, column 4, lines 63-67 describe an isolation layer 140 formed on a first interlevel dielectric layer 120);
a plurality of bottom electrodes (150, Fig. 5, column 5, lines 36-45 describe a bottom electrode 150 wherein upon combining Lee with Ok would result in a plurality of bottom electrodes) disposed in the second interlevel dielectric layer and contacting the plurality of first metal features, respectively (150, Fig. 5, column 5, lines 36-45 describes the bottom electrode 150 is disposed in the second interlevel dielectric layer 140 contacts a first metal feature 130 wherein upon combining Lee with Ok would result in a plurality of bottom electrodes contacting a plurality of metal features);
a first dielectric disposed on the second interlevel dielectric layer (170, Fig. 13, column 6 lines 14-19 describe a dielectric fill layer 170 disposed on the second interlevel dielectric 140); and
wherein the second dielectric is formed of a carbon-doped silicon oxide (280, Fig. 15, column 10, lines 44-54 describe a second interlayer dielectric layer (ILD), which can be seen surrounding the top electrode in Fig. 15, being comprised of a dielectric material, including carbon doped silicon oxide (SiO:C)).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Lee and Ok to further disclose a phase change memory device which includes a second interlevel dielectric in which a bottom electrode may be formed in and a first dielectric may be disposed on in order to provide the advantage of providing for an isolation layer that may act as a diffusion barrier and provide electrical isolation for the bottom electrodes (Ok, column 5, lines 1-4) and to further disclose a second dielectric layer comprising a low-k material such as carbon doped silicon oxide as taught by Ok to produce the predictable result of reducing current leakage to other components within the device.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Tung Ying Lee et al. (US 2021/0336138 A1; hereinafter “Lee”) in view of Injo Ok et al. (US 2020/0395537 A1; hereinafter “Ok II”).
Regarding Claim 10, Lee discloses all the limitations of claim 1.
Lee fails to explicitly disclose the phase change memory structure of Claim 1, further comprising a first nitride liner on at least one surface of the top electrode and separating the top electrode from the second dielectric.
However, Ok II teaches a similar phase change memory structure, further comprising a first nitride liner on at least one surface of the top electrode (112, Fig. 9, para [0075] describes a liner 112 being deposited on top electrode 94’ wherein the liner 112 may be a TaN liner) and separating the top electrode from the second dielectric (120, Fig. 10, para [0078] describes wherein the liner 112 separates the top electrode from the surrounding ILD 120 wherein upon combining Lee with Ok II the liner 112 would separate the top electrode from the second dielectric layer of Ok II).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Lee with Ok II to further disclose a phase change memory structure which comprises a first nitride liner separating a top electrode and dielectric layer in order to provide the well-known advantage providing a liner which may promote adhesion to the layers on which it is deposited and further prevent current leakage to surrounding elements of the phase change memory device which would produce undesirable device characteristics.
Regarding Claim 11, the combination of Lee and Ok II teach the phase change memory structure of Claim 10, wherein the first nitride liner is a metal-nitride adhesion layer (112, Fig. 8, para [0075] describes wherein the first nitride liner 112 may be a TaN liner or other metal type liner wherein a resulting metal liner would have an adhesive property to the metal electrode on which it is deposited) and the second metal feature extends through the first nitride liner (112, Fig. 9 and Fig. 10, para [0077] describes wherein the first nitride liner 112 may be a etched to form an opening on a top surface of the top electrode 94’ wherein para [0078] describes wherein a conductive material 82 fills the opening forming a second metal feature 82 extending through the first nitride liner 112).
Claims 26 is rejected under 35 U.S.C. 103 as being unpatentable over Tung Ying Lee et al. (US 2021/0336138 A1; hereinafter “Lee”) in view of Injo Ok et al. (US Patent 10,741,756 B1; hereinafter “Ok”) and in further view of Injo Ok et al. (US 2020/0395537 A1; hereinafter “Ok II”).
Regarding Claim 26, the combination of Lee and Ok discloses all the limitations of claim 23.
The combination of Lee and Ok fails to explicitly disclose the phase change memory structure of Claim 23, further comprising a first nitride liner on at least one surface of the top electrode, wherein the first nitride liner is a metal-nitride adhesion layer, and wherein the second dielectric surrounds the first nitride liner.
However, Ok II teaches a similar phase change memory structure, further comprising a first nitride liner on at least one surface of the top electrode (112, Fig. 9, para [0075] describes a liner 112 being deposited on top electrode 94’ wherein the liner 112 may be a TaN liner),
wherein the first nitride liner is a metal-nitride adhesion layer (112, Fig. 8, para [0075] describes wherein the first nitride liner 112 may be a TaN liner or other metal type liner wherein a resulting metal liner would have an adhesive property to the metal electrode on which it is deposited) and
wherein the second dielectric surrounds the first nitride liner (120, Fig. 10, para [0078] describes an ILD layer surrounding the first nitride liner 112 wherein upon combining the second dielectric layer 62 and top electrode 56 of Lee with the first nitride liner of Ok II 112, the sidewalls of the top electrode 56 of Lee being surrounded by the first nitride liner 112 of Ok II would result in the second dielectric 62 of Lee surrounding the first nitride liner of Ok II 112).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Lee and Ok with Ok II to further disclose a phase change memory structure which comprises a first metal nitride liner separating a top electrode and a surrounding dielectric layer in order to provide the well-known advantage providing a liner which may promote adhesion to the layers on which it is deposited and further prevent current leakage to surrounding elements of the phase change memory device which would produce undesirable device characteristics.
Response to Arguments
Applicant’s arguments with respect to claims 1, 6, 11, 13, 21, 23, 25 and 27 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898