CTFR 17/552,581 CTFR 100011 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 5, and 10-17 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Mano et al. (“Mano” US 2007/0257761) . Regarding claim 1, Mano discloses a microelectronic assembly (Figure 1), comprising: a substrate (13) having a first surface (lower surface) and an opposing second surface (upper surface), wherein a material of the substrate includes a glass material (see para. [0080]-[0086] which discloses a glass material and manufacturing process for substrate 130, which corresponds to the package 2 as shown in Figure 1, i.e. corresponds to the substrate 13 in Figure 1), and wherein the substrate (13) includes a conductive through-glass via (TGV) (28, middle), and the second surface of the substrate (upper surface) includes a cavity (opening within which the inductor 10 in placed, see Figure 1, here a cavity is interpreted to mean an opening or space within something, Figure 1 shows the opening extends to or starts at the upper surface of the substrate 13); a first die (10, inductor die) at least partially nested in the cavity (see Figure 1); an insulating material (15u/25u), on the second surface of the substrate (13, on the upper surface), the insulating material (15u/25u) having a first surface (lower surface) and an opposing second surface (upper surface), wherein the first surface of the insulating material is at the second surface of the substrate (see Figure 1); a first conductive pillar (53u, directly above far left inductor die 10) through the insulating material (15u/25u); a second conductive pillar (56u, far left) through the insulating material (15u/25u); a capacitor (C) in the insulating material (15u/25u) at the second surface of the substrate (13, upper surface), the capacitor including: a first layer (52u-1) directly on and in direct physical contact with the second surface of the substrate (13, see Figure 1), the first layer (52u-1) including a conductive material (“conductor circuit”, para. [0039]) electrically coupled to the TGV (28, middle) and the first conductive pillar (53u, directly above far left inductor die 10, electrically coupled through traces and components shown in Figure 1), wherein the first layer (52u-1) forms a first plate of the capacitor (C, see Figure 1, para. [0039]); a second layer (8) on the first layer (52u-1), the second layer (8) including a dielectric material (para. [0040]); and a third layer (54u-1) on the second layer (8), the third layer (54u-1) including the conductive material (para. [0039]) electrically coupled to the second conductive pillar (56u, far left), wherein the third layer (54u-1) forms a second plate of the capacitor (C, see Figure 1, para. [0039]); and a second die (6, MPU), at the second surface of the insulating material (15u/25u, see Figure 1), electrically coupled to the first die (10, see Figure 1). Regarding claim 5, Mano discloses wherein the first layer (52u-1) is a first conductive trace or a first conductive pad (52u-1 is considered a trace since it provides electrical connection through the package and has a sheet-like structure in the cross-section of Figure 1), and the third layer (54u-1) is a second conductive trace or a second conductive pad (similarly, 54u-1 is considered a trace since it provides electrical connection through the package and has a sheet-like structure in the cross-section of Figure 1). Regarding claim 10, Mano discloses wherein the capacitor (C) is one of a plurality of capacitors (see para. [0043]). Regarding claim 11, Mano discloses a microelectronic assembly (Figure 1), comprising: a substrate (13) having a first surface (lower surface) and an opposing second surface (upper surface), wherein a material of the substrate includes a glass material (see para. [0080]-[0086] which discloses a glass material and manufacturing process for substrate 130, which corresponds to the package 2 as shown in Figure 1, i.e. corresponds to the substrate 13 in Figure 1), and wherein the substrate (13) includes a conductive through-substrate via (TGV) (28, middle), and the second surface of the substrate (upper surface) includes a cavity (opening within which the inductor 10 in placed, see Figure 1, here a cavity is interpreted to mean an opening or space within something, Figure 1 shows the opening extends to or starts at the upper surface of the substrate 13); a first die (10, inductor die) at least partially nested in the cavity (see Figure 1); an insulating material (15u), on the second surface of the substrate (13, on the upper surface), the insulating material (15u) having a first surface (lower surface) and an opposing second surface (upper surface), wherein the first surface of the insulating material is at the second surface of the substrate (see Figure 1); a first conductive pillar (53u, directly above far left inductor die 10) through the insulating material (15u); a second conductive pillar (56u, far left) through the insulating material (15u/25u); a capacitor (C) at the second surface of the substrate (13) and embedded in the insulating material (15u, see Figure 1), the capacitor including: a first conductive trace (52u-1) directly on and in direct physical contact with the second surface of the substrate (13, upper surface, see Figure 1), the first conductive trace (52u-1) electrically coupled to the TGV (28, middle) and the first conductive pillar (53u, directly above far left inductor die 10, electrically coupled through traces and components shown in Figure 1), wherein the first conductive trace (52u-1) forms a first electrode of the capacitor (C, see para. [0039]); a dielectric material (8, para. [0040]) on the first conductive trace (52u-1, see Figure 1); and a second conductive trace (54u-1) on the dielectric material (8), the second conductive trace electrically coupled to the second conductive pillar (56u, far left), wherein the second conductive trace (54u-1) forms a second electrode of the capacitor (C, see para. [0039]); and a second die (6, MPU), at the second surface of the insulating material (15u, see Figure 1), electrically coupled to the first die (10, see Figure 1). Regarding claim 12, Mano discloses wherein the first conductive pillar (53u, directly above far left inductor die 10) and the second conductive pillar (56u, far left) are further electrically coupled to the second die (6, see Figure 1). Regarding claim 13, Mano discloses wherein the first die (10) includes first conductive contacts (52d) on a first surface (lower surface), second conductive contacts (52u) on an opposing second surface (upper surface), and the second die (6) is electrically coupled to the first die (10) by the second conductive contacts (52u, see Figure 1), and microelectronic assembly further comprises: a small TGV (53d) electrically coupled to an individual one of the first conductive contacts (52d) on the first die (10); and a package substrate (insulating layers 15d and 25d, plus traces embedded therein) at the first surface of the substrate (lower surface, 13), the package substrate (15d/25d and conductive traces embedded therein) electrically coupled to the capacitor (C) by the TGV (28, middle) and electrically coupled to the first die (10) by the small TGV (53d, see Figure 1). Regarding claim 14, Mano discloses wherein the TGV (28, middle) is one of a plurality of TGVs (Figure 1 shows a plurality of TGVs 28), and the microelectronic assembly further comprising: a third conductive pillar (53u, far right) extending through the insulating material (15u, see Figure 1), wherein the third conductive pillar (53u, far right) is electrically coupled to an individual one of the plurality of TGVs (28, see Figure 1), and wherein the package substrate (15d/25d plus traces embedded therein) is electrically coupled to the second die (6) by the third conductive pillar (53u, far right) and the individual one of the plurality of TGVs (28 connected to 53u far right, see Figure 1). Regarding claim 15, Mano discloses a redistribution layer (25u) between the insulating material (15u) and the second die. (6, see Figure 1). Regarding claim 16, Mano discloses wherein the first die (10) includes an embedded multi- die bridge (EMIB) die, a passive die, an EMIB with through-silicon vias (TSVs), or an active die (the first die 10 is an inductor, thus is a passive die). Regarding claim 17, Mano discloses wherein the second die includes a central processing unit (CPU), a graphics processing unit (GPU), or a processing die (the second die 6 is an MPU, which is a processing die) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim s 2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Mano as applied to claim 1 above, and further in view of Lin et al. (“Lin” US 2016/0276324) . Regarding claim 2, Mano does not disclose wherein an overall thickness of the capacitor (C) is between 35 nanometers and 2,000 nanometers. Lin discloses, however, an overall thickness of the capacitor (Figure 1B) is between 35 nanometers and 2,000 nanometers (since T1, T2, T3 are each designed to be less than 4 microns thick, the overall thickness of the capacitor is designed to be less than 12 microns). It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Lin into the teachings of Mano to include an overall thickness of the capacitor to be between 35 nanometers and 2,000 nanometers for the purpose of decreasing the thickness of the capacitor so that a larger capacitance value is obtained (Lin, para. [0034]). Regarding claim 6, Mano does not disclose wherein a thickness of the second layer is between 10 nanometers and 250 nanometers. Lin discloses, however, wherein a thickness (T3) of the second layer (456a) is between 10 nanometers and 250 nanometers (para. [0030] discloses the second layer 456a as less than 4 microns). It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Lin into the teachings of Mano to include wherein a thickness of the second layer is between 10 nanometers and 250 nanometers for the purpose of utilizing a thin capacitor so that a larger capacitance value is obtained (Lin, para. [0034]) . 07-22-aia AIA Claim s 3-4 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Mano as applied to claim 1 above, and further in view of Origuchi et al. (“Origuchi” US 2009/0237900) . Regarding claim 3, Mano does not disclose wherein a thickness of the first layer is between 10 nanometers and 15 microns and a thickness of the third layer is between 10 nanometers and 15 microns. Origuchi discloses wherein a thickness of the first layer (103) is between 10 nanometers and 15 microns (8 microns thick, para. [0056]) and a thickness of the third layer (102) is between 10 nanometers and 15 microns (8 microns thick, para. [0056]). It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Origuchi into the teachings of Mano to include the claimed range of thickness for the first and second layers for the purpose of achieving electrical reliability (Origuchi, para. [0024]). Regarding claim 4, Mano does not explicitly disclose wherein the conductive material includes copper, silver, nickel, gold, aluminum, or alloys thereof. Origuchi discloses wherein the conductive material includes copper, silver, nickel, gold, aluminum, or alloys thereof (nickel, para. [0022]-[0023]). It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Origuchi into the teachings of Mano to use a conductive material including nickel for the conductive material for the purpose of utilizing a material with a comparatively high melting point and reducing costs (Origuchi, para. [0023]). Regarding claim 7, Mano does not explicitly disclose wherein the dielectric material includes barium, titanium, and oxygen; strontium, titanium, and oxygen; titanium and oxygen; lead, zirconium, and titanium; barium, strontium, and titanium; a ferroelectric material; or a ferroelectric perovskite material. Origuchi discloses wherein the dielectric material (104) includes barium, titanium, and oxygen; strontium, titanium, and oxygen; titanium and oxygen; lead, zirconium, and titanium; barium, strontium, and titanium; a ferroelectric material; or a ferroelectric perovskite material (barium titanate, para. [0057]). It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Origuchi into the teachings of Mano to include barium titanate for the dielectric material for the purpose of utilizing a material with a high dielectric constant (Origuchi, para. [0025]). Regarding claim 8, Mano does not disclose wherein a thickness of the substrate is between 50 microns and 1,000 microns. Origuchi discloses wherein a thickness of the substrate (11) is between 50 microns and 1,000 microns (1mm, which is 1,000 microns, para. [0050]). It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Origuchi into the teachings of Mano to include the claimed thickness range for the substrate because the range disclosed by Origuchi overlaps the claimed range, and in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art,” a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)). Additionally, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized overall thickness of the module and mechanical robustness to be result effective variables affecting substrate thickness. Thus, it would have been obvious to modify the device of Mano to have the thickness of the substrate of Origuchi within the claimed range in order to optimize mechanical robustness and keep up with the industry’s minimization requirements, and since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05 II.B and 2143 . 07-22-aia AIA Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Mano as applied to claim 1 above, and further in view of Knickerbocker et al. (“Knickerbocker” US 2018/0344245) . Regarding claim 9, Mano does not disclose wherein the glass material of the substrate includes photoglass, borosilicate glass, soda lime glass, quartz, or a photoimageable glass. Knickerbocker discloses, however, wherein the glass material of the substrate (102) includes photoglass, borosilicate glass, soda lime glass, quartz, or a photoimageable glass (para. [0040]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Knickerbocker above into the teachings of Mano for the purpose of using a material with mechanical robustness, and low material and manufacturing cost (Knickerbocker, para. [0040], [0060]) . 07-22-aia AIA Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Mano as applied to claim 11 above, and further in view of Origuchi et al. (“Origuchi” US 2009/0237900) . Regarding claim 18, Mano does not explicitly disclose wherein the dielectric material includes barium, titanium, and oxygen; strontium, titanium, and oxygen; titanium and oxygen; lead, zirconium, and titanium; barium, strontium, and titanium; a ferroelectric material; or a ferroelectric perovskite material. Origuchi discloses wherein the dielectric material (104) includes barium, titanium, and oxygen; strontium, titanium, and oxygen; titanium and oxygen; lead, zirconium, and titanium; barium, strontium, and titanium; a ferroelectric material; or a ferroelectric perovskite material (barium titanate, para. [0057]). would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Origuchi into the teachings of Mano to include barium titanate for the dielectric material for the purpose of utilizing a material with a high dielectric constant (Origuchi, para. [0025]). Response to Arguments Applicant’s arguments with respect to claims 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 17/552,581 Page 2 Art Unit: 2899 Application/Control Number: 17/552,581 Page 3 Art Unit: 2899 Application/Control Number: 17/552,581 Page 4 Art Unit: 2899 Application/Control Number: 17/552,581 Page 5 Art Unit: 2899 Application/Control Number: 17/552,581 Page 6 Art Unit: 2899 Application/Control Number: 17/552,581 Page 7 Art Unit: 2899 Application/Control Number: 17/552,581 Page 8 Art Unit: 2899 Application/Control Number: 17/552,581 Page 9 Art Unit: 2899 Application/Control Number: 17/552,581 Page 10 Art Unit: 2899
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