DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114 was filed in this application after appeal to the Patent Trial and Appeal Board, but prior to a decision on the appeal. Since this application is eligible for continued examination under 37 CFR 1.114 and the fee set forth in 37 CFR 1.17(e) has been timely paid, the appeal has been withdrawn pursuant to 37 CFR 1.114 and prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant’s submission filed on February 17 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7-8, and 10-17 are rejected under 35 U.S.C. 103 as being unpatentable over Origuchi et al. (“Origuchi” US 2009/0237900).
Regarding claim 1, Origuchi discloses a microelectronic assembly (Figure 14), comprising:
a substrate (core substrate 11) having a first surface (lower surface) and an opposing second surface (upper surface), wherein a material of the substrate (11) includes a glass material (disclosed in para. [0050]), and wherein the substrate (11) includes a conductive through-glass via (16, para. [0050]) (TGV), and the second surface of the substrate includes a cavity (housing hole, para. [0011]);
a first die (61) at least partially nested in the cavity (shown in Figure 14);
an insulating material (insulating layers of 31, para. [0053]), on the second surface of the substrate (11, shown in Figure 14), the insulating material having a first surface (lower surface) and an opposing second surface (upper surface), wherein the first surface of the insulating material is at the second surface of the substrate (shown in Figure 14, the top surface of the substrate 11 is coplanar with the lower surface of the insulating material, the insulating layers of 31);
a first conductive pillar (27, 28) through the insulating material (shown in Figure 14);
a second conductive pillar (24, 26) through the insulating material (shown in Figure 14);
a capacitor (101) in the insulating material (shown in Figure 14) at the second surface of the substrate (the capacitor 101 is contacting the second surface of the substrate), the capacitor (101) including:
a first layer (103) directly on the second surface of the substrate (shown in Figure 14), the first layer including a conductive material (nickel, para. [0057]) electrically coupled to the TGV (16, see the layer 103 electrically coupled to IC chip 21, and TGV electrically coupled to IC chip 21, thus the first layer 103 and the TGV 16 are electrically coupled) and the first conductive pillar (27, 28, para. [0058]), wherein the first layer forms a first plate of the capacitor (101, para. [0057]);
a second layer (104) on the first layer (103, shown in Figure 14), the second layer including a dielectric material (para. [0057]); and
a third layer (102) on the second layer, the third layer including the conductive material (nickel, para. [0058]) electrically coupled to the second conductive pillar (24, 26, para. [0058]), wherein the third layer (102) forms a second plate of the capacitor 101, para. [0057]); and
a second die (21), at the second surface of the insulating material (shown in Figure 14), electrically coupled to the first die (61, coupling shown in Figure 14 through conductive structures 25, 23, 43).
While Origuchi does not explicitly state that the TGV and the first layer are electrically coupled, they share an electrical interface with the IC chip. Since the TGV and the first layer are each electrically coupled to the same IC chip, it would have been obvious to one having ordinary skill in the art that the TGV and the first layer are electrically coupled through electrical interconnections/pathways within the IC chip.
Regarding claim 3, Origuchi discloses wherein a thickness of the first layer (103) is between 10 nanometers and 15 microns (8 microns thick, para. [0056]) and a thickness of the third layer (102) is between 10 nanometers and 15 microns (8 microns thick, para. [0056]).
Regarding claim 4, Origuchi discloses wherein the conductive material includes copper, silver, nickel, gold, aluminum, or alloys thereof (nickel, para. [0057]).
Regarding claim 5, Origuchi discloses wherein the first layer (103) is a first conductive trace or a first conductive pad, and the third layer (102) is a second conductive trace or a second conductive pad (both the third layer and first layer are interpreted to also be conductive pads or traces because they electrically connect parts of the device, which is the purpose of conductive pads or traces).
Regarding claim 7, Origuchi discloses wherein the dielectric material (104) includes barium, titanium, and oxygen; strontium, titanium, and oxygen; titanium and oxygen; lead, zirconium, and titanium; barium, strontium, and titanium; a ferroelectric material; or a ferroelectric perovskite material (barium titanate, para. [0057]).
Regarding claim 8, Origuchi discloses wherein a thickness of the substrate (11) is between 50 microns and 1,000 microns (1mm, which is 1,000 microns, para. [0050]).
Regarding claim 10, Origuchi discloses wherein the capacitor (101) is one of a plurality of capacitors (more capacitors 213 are shown in Figure 14, para. [0093]).
Regarding claim 11, Origuchi discloses a microelectronic assembly, comprising:
a substrate (core substrate 11) having a first surface (lower surface) and an opposing second surface (upper surface), wherein a material of the substrate (11) includes a glass material (disclosed in para. [0050]), and wherein the substrate (11) includes a conductive through-glass via (16, para. [0050]) (TGV), and the second surface of the substrate includes a cavity (housing hole, para. [0011]);
a first die (61) at least partially nested in the cavity (shown in Figure 14);
an insulating material (33, 35), on the second surface of the substrate (11, shown in Figure 14), the insulating material (33, 35) having a first surface (bottom surface) and an opposing second surface (top surface), wherein the first surface of the insulating material (33, 35) is at the second surface of the substrate (the top surface of the substrate is coplanar with the bottom surface of the insulating material, shown in Figure 14);
a first conductive pillar (43, on the far right of the device shown in Figure 14) through the insulating material (33, 35);
a second conductive pillar (43, on the left side of the device, through the hole of the capacitor 101, shown in Figure 14) through the insulating material (33, 35);
a capacitor (101) at the second surface of the substrate (11, shown in Figure 14 the capacitor 101 is on the substrate 11) and embedded in the insulating material (33, 35, shown in Figure 14), the capacitor including:
a first conductive trace (103) directly on the second surface of the substrate (11, shown in Figure 14), the first conductive trace (103) electrically coupled to the TGV (16, see the layer 103 electrically coupled to IC chip 21, and TGV electrically coupled to IC chip 21, thus the first conductive trace 103 and the TGV 16 are electrically coupled) and the first conductive pillar (para. [0058]), wherein the first conductive trace (103) forms a first electrode of the capacitor (101, para. [0057]);
a dielectric material (104) on the first conductive trace (103, shown in Figure 14);
and a second conductive trace (102) on the dielectric material (104, shown in Figure 14), the second conductive trace (102) electrically coupled to the second conductive pillar (43 on the left, para. [0058]), wherein the second conductive trace (102) forms a second electrode of the capacitor (101, para. [0057]); and
a second die (21), at the second surface of the insulating material (33, 35, second die 21 is on the insulating material), electrically coupled to the first die (61, coupled through conductive structures 22, 23, 25, 43, 65, shown in Figure 14).
While Origuchi does not explicitly state that the TGV and the first conductive trace are electrically coupled, they share an electrical interface with the IC chip. Since the TGV and the first conductive trace are each electrically coupled to the same IC chip, it would have been obvious to one having ordinary skill in the art that the TGV and the first conductive trace are electrically coupled through electrical interconnections/pathways within the IC chip.
Regarding claim 12, Origuchi discloses wherein the first conductive pillar (43 on the right) and the second conductive pillar (43 on the left) are further electrically coupled to the second die (21, electrical coupling shown in Figure 14 through conductive structures).
Regarding claim 13, Origuchi discloses wherein the first die (61) includes first conductive contacts (42) on a first surface (lower surface), second conductive contacts (65) on an opposing second surface (upper surface), and the second die (21) is electrically coupled to the first die (61) by the second conductive contacts (65, shown in Figure 14), and microelectronic assembly further comprises:
a small TGV (221) electrically coupled to an individual one of the first conductive contacts (65) on the first die (61, shown in Figure 14); and
a package substrate (32) at the first surface of the substrate (lower surface, shown in Figure 14), the package substrate (32) electrically coupled to the capacitor (101) by the TGV (16) and electrically coupled to the first die (61) by the small TGV (221, electrical coupling through conductive structures shown in Figure 14).
Regarding claim 14, Origuchi discloses wherein the TGV (16) is one of a plurality of TGVs (plurality of TGVs 16 are disclosed in para. [0050]), and the microelectronic assembly further comprising:
a third conductive pillar (41) extending through the insulating material (33, 35), wherein the third conductive pillar (41) is electrically coupled to an individual one of the plurality of TGVs (16, shown in Figure 14), and
wherein the package substrate (32) is electrically coupled to the second die (21) by the third conductive pillar (41) and the individual one of the plurality of TGVs (16, coupling through 41 and 16 is shown in Figure 14).
Regarding claim 15, Origuchi further discloses a redistribution layer (37, 50) between the insulating material (33, 35) and the second die (21, 37, 50 are insulating layers with conductive structures embedded therein and thus is interpreted to be a redistribution layer).
Regarding claim 16, Origuchi discloses wherein the first die (61) includes an embedded multi-die bridge (EMIB) die, a passive die, an EMIB with through-silicon vias (TSVs), or an active die (para. [0005] and [0014] discloses semiconductor integrated circuit device [IC chip] as a microprocessor).
Regarding claim 17, Origuchi discloses wherein the second die (21) includes a central processing unit (CPU), a graphics processing unit (GPU), or a processing die (para. [0005] and [0014] discloses semiconductor integrated circuit device [IC chip] as a microprocessor).
Regarding claim 18, Origuchi discloses wherein the dielectric material (104) includes barium, titanium, and oxygen; strontium, titanium, and oxygen; titanium and oxygen; lead, zirconium, and titanium; barium, strontium, and titanium; a ferroelectric material; or a ferroelectric perovskite material (barium titanate, para. [0057]).
Claims 2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Origuchi as applied to claim 1 above, and further in view of Lin et al. (“Lin” US 2016/0276324).
Regarding claim 2, Origuchi does not disclose wherein an overall thickness of the capacitor is between 35 nanometers and 2,000 nanometers.
Lin discloses, however, an overall thickness of the capacitor (Figure 1B) is between 35 nanometers and 2,000 nanometers (since T1, T2, T3 are each designed to be less than 4 microns thick, the overall thickness of the capacitor is designed to be less than 12 microns).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Lin into the teachings of Origuchi to include wherein an overall thickness of the capacitor is between 35 nanometers and 2,000 nanometers for the purpose of decreasing the thickness of the capacitor so that a larger capacitance value is obtained (Lin, para. [0034]).
Regarding claim 6, Origuchi does not disclose a thickness of the second layer is between 10 nanometers and 250 nanometers.
Lin discloses, however, wherein a thickness (T3) of the second layer (456a) is between 10 nanometers and 250 nanometers (para. [0030] discloses the second layer 456a as less than 4 microns).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Lin into the teachings of Origuchi to include wherein a thickness of the second layer is between 10 nanometers and 250 nanometers for the purpose of decreasing the thickness of the capacitor so that a larger capacitance value is obtained (Lin, para. [0034]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Origuchi as applied to claim 1 above, and further in view of Knickerbocker et al. (“Knickerbocker” US 2018/0344245).
Regarding claim 9, Origuchi does not disclose wherein the glass material of the substrate includes photoglass, borosilicate glass, soda lime glass, quartz, or a photoimageable glass.
Knickerbocker discloses, however, wherein the glass material of the substrate (102) includes photoglass, borosilicate glass, soda lime glass, quartz, or a photoimageable glass (para. [0040]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Knickerbocker above into the teachings of Origuchi for the purpose of using a material with mechanical robustness, and low material and manufacturing cost (Knickerbocker, para. [0040], [0060]).
Response to Arguments
Applicant's arguments filed February 17 2026 regarding the interpretation of the term “on” have been fully considered but they are not persuasive.
Applicant argues that “to one of ordinary skill in the art, in the context of integrated circuit packaging, the dielectric layers of Origuchi break the direct (or even transitive) "on" relationship between Origuchi's capacitor and glass substrate. Second, Applicant's usage of "on either side" in paragraph 36 does not support the Examiner's interpretation. That usage of "on" is positional (the chips are positionally nearby), rather than defining contact/support. The issue is moot in view of Applicant's amendments. Origuchi lacks the now-recited structure (as is well documented in the appeal).” The Examiner respectfully disagrees.
It is the Examiner’s position that the terms “on” and “directly on” do not require direct physical contact and allow for intervening layers or elements. For example, one may assert that a cup is directly on a counter, even though there is a magazine and a coaster stacked therebetween. Similarly, one may assert that a house is directly on a lake, even though there is a degree of physical distance between the house and the lake. With this common usage of the terms “on” and “directly on”, one may also conclude that the capacitor of Origuchi is directly on the glass substrate even with the dielectric layers in between.
Regarding Applicant’s second argument, it is the Examiner’s position that the usage of the term “on” in Applicant’s specification, see para. [0036], is no different than the usage of “on” in the claims. “On” is used as a prepositional phrase in both instances, i.e. is used to describe the relationship between two elements, thus it is unclear how the usages are distinct from each other, one referring to position, the other referring to contact/support.
Ultimately, Applicant’s reading of the term “on” is narrow compared to its ordinary meaning. If Applicant has intended to claim that the first layer/conductive trace is in direct physical contact with the second surface of the substrate, the Examiner suggests amending the claims to specifically include this limitation, since incorporating this limitation would distinguish the claimed and disclosed invention over the prior art as applied in the rejection.
Applicant’s arguments regarding the interpretation of “electrically coupled” are not persuasive. Applicant essentially alleges that the Examiner’s primary basis for the assertion that the first layer/conductive trace of the capacitor is electrically coupled to the TGV is that Origuchi is silent to any electrical isolation between the first layer/conductive trace and the TGV, and thus the Examiner is relying on filling in the gaps of the disclosure of Origuchi. However, this was not the basis of the Examiner’s argument, rather a further clarification as to the fact that the first layer/conductive trace and the TGV would be considered electrically coupled since there is also no explicit electrical isolation between the elements or devices in Origuchi, in addition to the foundational argument which is stated in the Answer, mailed December 19 2025, see the first and second paragraphs of page 9. The Examiner stated the first layer/conductive trace of Origuchi is electrically coupled to the IC chip, and the IC chip is electrically coupled to the TGV, thus the first layer/conductive trace and the TGV are electrically coupled through the IC chip and electrical energy can be transferred therebetween. If Applicant is alleging that Origuchi’s IC chip has electrical isolation therein, the Examiner would be open to discussing that matter.
Conclusion
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899