DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with paragraph numbers and line numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner are encouraged to fill out the online Automated Interview Request (AIR) form:
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
See MPEP § 502.03 & § 713.01(II) and Interview Practice for additional details.
Status of claims to be treated in this office action:
Independent: Claim 1
Amended: Claims 1-2, 9, 11 & 18
Pending: Claims 1-4, 6-12 & 18-26
New: Claims 21-26
Cancelled: Claims 5 & 13-17
Withdrawn: Claims 8, 10-12, 18-20 & 26
Note that Claim 26 (New) is dependent upon Claim 11 (Withdrawn – Currently Amended), hence not examined.
Response to Arguments
Regarding Applicant’s argument to “not submit replacement drawings to address the objection regarding the reference to traces in Claim 7 so as to not obscure the drawing” on page 11 in the reply filed on 4 August 2025, the Examiner finds Applicant’s argument persuasive and withdraws the associated objection.
Regarding Applicant’s argument that Claim 9 is not a Markush claim on page 12 in the reply filed on 4 August 2025, the Examiner finds Applicant’s argument persuasive and withdraws the associated rejection.
Regarding Applicant’s argument about the prior art rejections of Claims 1-7 & 9 on pages 12-13 of the response filed on 4 August 2025, the Examiner has considered Applicant’s argument but said arguments are moot because they do not apply to the new grounds of rejection presented in this Office Action as necessitated by Applicant’s amendment.
Applicant’s correction of the typographical error in Claim 9 in the reply filed on 4 August 2025 is acknowledged.
Applicant’s submission of replacement drawings and the corrections made therein in the reply filed on 4 August 2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 23 (New) is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 23 (New), this claim cites the limitation “the second conductive interconnects have a smaller pitch than the first conductive interconnects”. However, the drawings of the elected species (Fig. 2 and/or Fig. 3) and the specification ([0089] and/or [0158]) support the opposite statement, making the intent of this claim language unclear and, therefore, indefinite.
For the purposes of examination, and to avoid a New Matter issue, this limitation will be interpreted as “the second conductive interconnects have a larger pitch than the first conductive interconnects”.
Regarding Claim 25 (New), a broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, Independent Claim 1 (Currently Amended) broadly cites “the third die comprising passive components”, and Claim 25 (New), which depends upon Independent Claim 1 (Currently Amended), also cites “the third IC die lacks active components” which is the narrower statement of the range/limitation. The claim(s) are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims.
For the purposes of examination and compact prosecution, this limitation will be interpreted as “a portion of the third IC die lacks active components”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 6-7, 9 & 21-25 are rejected under 35 U.S.C 103 as being unpatentable over LIN (US 20120193785 A1) in view of ALE (US 20190198447 A1).
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Re: Independent Claim 1 (Currently Amended), LIN discloses a microelectronic assembly (LIN Annotated Fig. 4), comprising:
a first integrated circuit (IC) die (LIN Annotated Fig. 4: D2.),
the first IC die comprising an input/output (IO) circuit (LIN Annotated Fig. 4 shows D2 comprising 7 in D2, where LIN [0061] teaches 7 in D2 may be an IO circuit, receiving IO signals via TSVs.);
in a portion of the first IC die (LIN Annotated Fig. 4 shows 7 inside of D2 is in a portion of D2.)
and other circuitry in another portion of the first IC die (LIN Annotated Fig. 4 shows 40 in D2 in another portion of D2, where 40—an interconnect—is construed as other circuitry.)
and a plurality of IC dies (LIN Annotated Fig. 4: D1 & D3),
the plurality of IC dies comprising a second IC die (LIN Annotated Fig. 4: D3),
and a third IC die, (LIN Annotated Fig. 4: D1)
and the third die comprising passive components (LIN [0048] teaches 7 in D1 may comprise passive components.)
coupled with the IO circuit (LIN Abstract teaches “the stacked chips can be connected to each other”, which is construed to mean the passive components of D1 may be coupled with the IO circuit of D2.)
wherein the microcontroller circuit of the second die is over and substantially aligned with the IO circuit of the first IC die, (LIN Annotated Fig. 4 shows 7 in D3 is over and substantially aligned with the 7 in D2 where 7 in D3 is an “IC device” modified in view of ALE to be a microcontroller circuit, as stated below.)
and the first IC die is coupled with via conductive interconnects (LIN Annotated Fig. 4: shows D2 coupled with D1 & D3 via 40s where LIN [0054] teaches each 40 is a “metal layer”, which “may be for interconnection”.)
having a pitch of less than 10 micrometers
LIN is silent to:
the second IC die comprising a microcontroller circuit to control the IO circuit,
However, ALE discloses:
the second IC die (ALE Fig. 1: 104; as ALE [0027] teaches 104 is a die “of a[n] integrated circuit [device]”.) comprising a microcontroller circuit to control the IO circuit (ALE [0027] teaches “dies 102 and 104 can be of a similar type of integrated circuit devices or can be different. For example, dies 102 and 104 can be any of…input/output (I/O) controllers…or memory devices, among other devices. Dies 102 and 104 are coupled with contacts”.),
LIN and ALE both disclose a microelectronic assembly. Hence, both are art analogous to the instant application and to each other. ALE also discloses a second IC die comprising a microcontroller circuit to control the IO circuit. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the “IC device” of the second IC die of LIN with the microcontroller of ALE, as doing so would provide “a connection point for additional devices…through which a user might interact with the system”, ALE [0055].
Re: Claim 4 (Original), LIN & ALE disclose all of the limitations of Independent Claim 1 (Currently Amended), upon which this claim depends.
LIN further discloses:
wherein the IO circuit (LIN Annotated Fig. 4: 7 in D2) is proximate to a periphery of the first IC die (LIN Annotated Fig. 4 shows 7 in D2 to be in direct contact with a lower surface of D2.).
Re: Claim 6 (Original), LIN & ALE disclose all of the limitations of Independent Claim 1 (Currently Amended), upon which this claim depends.
LIN further discloses:
further comprising conductive traces between the IO circuit and the plurality of IC dies (As established in the rejection of Claim 3 (Original), the plurality of IC dies may interact with the IO circuit, and this interaction is via interconnects 40, which themselves constitute said conductive traces.).
Re: Claim 7 (Original), LIN & ALE disclose all of the limitations of Claim 6 (Original), upon which this claim depends.
LIN further discloses:
wherein a portion of the conductive traces is in the first IC die and another portion of the conductive traces is in the second IC die (LIN Annotated Fig. 4 shows the interconnects/conductive traces 40 passing through both the first IC die D2 and the second IC die D3.).
Re: Claim 9 (Currently Amended), LIN & ALE disclose all of the limitations of Independent Claim 1 (Currently Amended), upon which this claim depends.
LIN further discloses:
further comprising a dielectric surrounding
Re: Claim 21 (New), LIN & ALE disclose all of the limitations of Independent Claim 1 (Currently Amended), upon which this claim depends.
LIN further discloses:
wherein: a footprint of the second IC die fits within a boundary of IO circuit. (LIN Annotated Fig. 4 shows D3 as a whole—construed to be the footprint of D3—fits within a boundary of D2 as a whole—construed to be a boundary of the IO circuit, as the elements contained within D2 may be construed as components of the IO circuit.)
Re: Claim 22 (New), LIN & ALE disclose all of the limitations of Claim 21 (New), upon which this claim depends.
LIN further discloses:
wherein the footprint is a first footprint, and wherein: a second footprint of the third IC die fits within the boundary of the IO circuit. (LIN Annotated Fig. 4 shows D1 as a whole—construed to be the second footprint of D1—fits within the boundary of D2 as a whole—construed to be the boundary of the IO circuit, as the elements contained within D2 may be construed as components of the IO circuit.)
Re: Claim 23 (New), LIN & ALE disclose all of the limitations of Independent Claim 1 (Currently Amended), upon which this claim depends.
The embodiment of LIN represented by LIN Annotated Fig. 4 is silent to:
wherein the conductive interconnects are first conductive interconnects, and wherein the microelectronic assembly further comprises: a package substrate below and coupled with the first IC die; and second conductive interconnects between and coupled with the package substrate and the first IC die, wherein the second conductive interconnects have a larger pitch than the first conductive interconnects.
However, another embodiment of LIN discloses:
wherein the conductive interconnects are first conductive interconnects, and wherein the microelectronic assembly further comprises: a package substrate below and coupled with the first IC die; (LIN Fig. 92 shows a package substrate 288 below and coupled with the first IC die 240—via the third IC die 238—for a similar microelectronic assembly.)
and second conductive interconnects between and coupled with the package substrate and the first IC die, (LIN Fig. 92 shows second conductive interconnects 248/252/254 between and coupled with 288 and the 240—via 238—for a similar microelectronic assembly.)
wherein the second conductive interconnects have a larger pitch than the first conductive interconnects. (LIN Fig. 92 shows 248/252/254 have a larger pitch than the first conductive interconnects—246/250/264/284—for a similar microelectronic assembly.)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify one embodiment of LIN to comprise the package substrate and second conductive interconnects of another similar embodiment of LIN, as these inventions are similar embodiments of the same invention.
Re: Claim 24 (New), LIN & ALE disclose all of the limitations of Independent Claim 1 (Currently Amended), upon which this claim depends.
LIN further discloses:
the second IC die and the third IC die are coplanar (LIN Annotated Fig. 4 shows D3 and D1 are both in the plane of the figure. Therefore, D3 and D1 are coplanar.)
and wherein the microelectronic assembly further comprises: a dielectric material between the second IC die and the third IC die. (As stated for Claim 9 (Currently Amended), LIN discloses dielectric layers surrounding D2. Further, LIN Annotated Fig. 4 shows D2 between D3 and D1. Therefore, the dielectric layers surrounding D2 are also between D3 and D1.)
Re: Claim 25 (New), LIN & ALE disclose all of the limitations of Independent Claim 1 (Currently Amended), upon which this claim depends.
LIN further discloses:
wherein: a portion of the third IC die lacks active components. (LIN Annotated Fig. 4 shows a portion 6 of D1 that is insulative material, and therefore lacks active components.)
Claims 2 & 3 are rejected under 35 U.S.C 103 as being unpatentable over LIN in view of ALE and in further view of LIN2 (US 20070235878 A1).
Re: Claim 2 (Currently Amended), LIN & ALE disclose all of the limitations of Independent Claim 1 (Currently Amended), upon which this claim depends.
LIN & ALE are both silent to:
wherein the passive components is integrated into a metallization stack of the third IC die.
However, LIN2 discloses:
the third IC die (LIN2 Fig.1: 102; as LIN2 [0021] teaches 102 is an integrated circuit die.) comprising the passive components is integrated into a metallization stack of the third IC die (LIN2 [0049] teaches there are “inductors in the second metal layer”; LIN2 [0023] teaches “[the] second metal layer 122 is patterned on the first metal layer 114”; LIN2 Fig. 1 shows 114 on 106 on 102; and LIN2 [0029] teaches 106 is the “final metal layer” of IC die 102.).
LIN & ALE and LIN2 all disclose a microelectronic assembly. Hence, all are art analogous to the instant application and to each other. LIN2 also discloses an IC die comprising passive components integrated into a metallization stack of the IC die. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the microelectronic assembly of LIN and ALE with the passive component integration design of LIN2, as doing so provides a means to address “one of the major challenges in the creation of [modern] analog processing circuitry…[, which] is that a number of the components that are used for analog circuitry are large in size and are therefore not readily integrated into integrated circuits”, LIN2 [0003]. That is, the passive component integration design of LIN2 helps to continue to miniaturize microelectronic assemblies.
Re: Claim 3 (Original), LIN & ALE, and LIN2 disclose all of the limitations of claim 2, upon which this claim depends. LIN further discloses:
further comprising a fourth IC die in the plurality of IC dies, the fourth IC die comprising one or more circuits to interact with the IO circuit (Regarding LIN Annotated Fig. 4, LIN [0061] teaches “the quantity of the stacked memory chips may be any suitable quantity, such as 4, 8, 16, or more”.)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Thursday, 9 A.M. to 6 P.M., and every other Friday, 9 A.M. to 5 P.M. (EST)..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ajay Ojha can be reached at 571-272-8936. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898
/AJAY OJHA/Supervisory Patent Examiner, Art Unit 2898 10/3/2025