DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3.3.2026 has been entered.
Election/Restrictions
Claims 4-5 and 9-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5.9.2025 and subsequent voicemail from Justin Brask received on 7.15.2025.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the trench of claims 2 and 7 (note: where is said trench in elected Fig. 1O?) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102 and 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 6-7 are rejected under 35 U.S.C. 102(a)(1) or 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (US 20210226020 A1).
Regarding claim 1, Lin discloses an integrated circuit structure, comprising:
a sub-fin (104N/104P) in a shallow trench isolation (STI) structure (110, Fig. 2P-3);
a plurality of horizontally stacked nanowires (108) over the sub-fin;
a gate dielectric material layer (154) surrounding the plurality of horizontally stacked nanowires;
a gate electrode structure (156) over the gate dielectric material layer;
a confined epitaxial source or drain structure (132/142) at an end of the plurality of horizontally stacked nanowires (Figs. 2P-1 and 2P-2); and
a dielectric anchor (112) laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure (Fig. 2P-3), the dielectric anchor in direct physical contact with the first portion of the STI structure, and the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure (Fig. 2P-1) and below an uppermost surface of the plurality of horizontally stacked nanowires (Fig. 2P-3).
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Regarding claim 2, Lin discloses the integrated circuit structure of claim 1, wherein a second portion of the STI structure (110) on a side of the plurality of horizontally stacked nanowires (108) opposite the dielectric anchor (one anchor 112) has a trench therein (occupied by another anchor 112; Fig. 2P-3).
Regarding claim 6, Lin discloses an integrated circuit structure, comprising:
a fin (104N/104P/108) having a portion (108) protruding above a shallow trench isolation (STI) structure (110, Figs. 2P-1 and 2P-3);
a gate dielectric material layer (154) over the protruding portion (108) of the fin;
a gate electrode structure (156) over the gate dielectric material layer;
a confined epitaxial source or drain structure (132/142) at an end of the fin (Fig. 2P-2); and
a dielectric anchor (112) laterally spaced apart from the fin and recessed into a first portion of the STI structure (110), the dielectric anchor in direct physical contact with the first portion of the STI structure (110), and the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure (Fig. 2P-1) and below an uppermost surface of the fin (Fig. 2P-3; see annotated figures above).
Regarding claim 7, Lin discloses the integrated circuit structure of claim 6, wherein a second portion of the STI structure (110) on a side of the fin opposite the dielectric anchor (one 112) has a trench therein (occupied by another 112; Figs. 2P-1 and 2P-3).
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20210226020 A1) in view of Mehandru et al. (of record, US 20190252525 A1).
Regarding claims 11-15, Lin discloses (claim 11) a computing device, comprising:
a sub-fin (104N/104P) in a shallow trench isolation (STI) structure (110, Fig. 2P-3);
a plurality of horizontally stacked nanowires (108) over the sub-fin;
a gate dielectric material layer (154) surrounding the plurality of horizontally stacked nanowires;
a gate electrode structure (156) over the gate dielectric material layer;
a confined epitaxial source or drain structure (132/142) at an end of the plurality of horizontally stacked nanowires (Figs. 2P-1 and 2P-2); and
a dielectric anchor (112) laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure (Fig. 2P-3), the dielectric anchor in direct physical contact with the first portion of the STI structure, and the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure (Fig. 2P-1) and below an uppermost surface of the plurality of horizontally stacked nanowires (Fig. 2P-3; see figures annotated above).
Lin fails to disclose (claim 11) a board; and a component coupled to the board, the component including an integrated circuit structure, (claim 12) further comprising: a memory coupled to the board, (claim 13) further comprising: a communication chip coupled to the board, (claim 14) wherein the component is a packaged integrated circuit die, and, (claim 15) wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
Mehandru discloses (claim 11) a board (2902, Fig. 29); and a component (2904/2906) coupled to the board, the component including an integrated circuit structure (inherent, [0140]), (claim 12) further comprising: a memory (e.g., DRAM) coupled to the board (2902, Fig. 29), (claim 13) further comprising: a communication chip (2906) coupled to the board (Fig. 29), (claim 14) wherein the component is a packaged integrated circuit die ([0140]), and, (claim 15) wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor ([0137-0140], Fig. 29).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Mehandru in Lin and arrive at the claimed invention so as to provide an integrated computing device with diverse electronic devices for the purposes of creating, e.g., a consumer electronic product with multiple functions, e.g., a cell phone, and/or because the use of conventional elements (boards, components, memories, processors, communication chips, packages and digital signal processors) to perform their known function is prima-facie obvious and would have yielded predictable results to one of ordinary skill in the art.
Regarding claims 16-20, Lin discloses a computing device, comprising:
a fin (104N/104P/108) having a portion (108) protruding above a shallow trench isolation (STI) structure (110, Figs. 2P-1 and 2P-3);
a gate dielectric material layer (154) over the protruding portion (108) of the fin;
a gate electrode structure (156) over the gate dielectric material layer;
a confined epitaxial source or drain structure (132/142) at an end of the fin (Fig. 2P-2); and
a dielectric anchor (112) laterally spaced apart from the fin and recessed into a first portion of the STI structure (110), the dielectric anchor in direct physical contact with the first portion of the STI structure (110), and the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure (Fig. 2P-1) and below an uppermost surface of the fin (Fig. 2P-3; see annotated figures above).
Lin fails to disclose (claim 16) a board; and a component coupled to the board, the component including an integrated circuit structure, (claim 17) further comprising: a memory coupled to the board, (claim 18) further comprising: a communication chip coupled to the board, (claim 19) wherein the component is a packaged integrated circuit die, and, (claim 20) wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
Mehandru discloses (claim 16) a board (2902, Fig. 29); and a component (2904/2906) coupled to the board, the component including an integrated circuit structure (inherent, [0140]), (claim 17) further comprising: a memory (e.g., DRAM) coupled to the board (2902, Fig. 29), (claim 18) further comprising: a communication chip (2906) coupled to the board (Fig. 29), (claim 19) wherein the component is a packaged integrated circuit die ([0140]), and, (claim 20) wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor ([0137-0140], Fig. 29).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Mehandru in Lin and arrive at the claimed invention so as to provide an integrated computing device with diverse electronic devices for the purposes of creating, e.g., a consumer electronic product with multiple functions, e.g., a cell phone, and/or because the use of conventional elements (boards, components, memories, processors, communication chips, packages and digital signal processors) to perform their known function is prima-facie obvious and would have yielded predictable results to one of ordinary skill in the art.
Response to Arguments
Applicant’s arguments with respect to the pending claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818