DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In view of the Appeal Brief filed on 10/15/2025, PROSECUTION IS HEREBY REOPENED. A new ground of rejection is set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
/Timothy J. Dole/ Supervisory Patent Examiner, Art Unit 2848
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 10-11, and 15 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Morimoto et al. (U.S. 20020179955) hereafter Morimoto.
As to claim 1, Morimoto discloses an electronic package (semiconductor device, para-0055, line 1) as shown in figures 1-11, comprising:
a core (L2) with a first surface (top surface) and a second surface (bottom surface), wherein the core comprises glass (silicon oxide = silica, para-0061+);
a first buildup layer (L3, L4) over the first surface of the core;
a second buildup layer (L1, 7, 1) under the second surface of the core;
a via (not label, the via is formed where the element W2, P2 are conductor filled in, hereafter V) through the core (L2) between the first and second surfaces of the core; and
a recess (not label, the recess is formed where the metal film 9 filled in, hereafter R) into the first surface of the core and filled with a metal (9, para-0061), wherein a width of the recess (R) is greater than a width of the via (V), and wherein the metal (9) has an uppermost surface at a same level as the first surface of the core (L2), see figure 3.
As to claim 4, Morimoto discloses in figure 3 that a top surface of the recess (R) is substantially coplanar with the first surface (top surface) of the core (L2).
As to claim 10, Morimoto discloses a method of forming an electronic package (the semiconductor device) as shown in figures 1-11 comprising:
providing a core (L2), wherein the core is a glass substrate (silicon oxide, para-0061+) with a first surface (top surface) and a second surface (bottom surface);
exposing the first surface and the second surface with a laser (using BEOL, Black End of the Line, process, i.e. ablation) to form exposed regions, wherein the exposed regions comprise:
a plane region (9); and
a via region (W2, P2);
etching (para-0066+) the exposed regions to form a plane opening (not label, the recess is formed where the metal film 9 filled in, hereafter R) and a via opening (not label, the via is formed where the element W2, P2 are conductor filled in, hereafter V); and
filling the plane opening (W2, P2) and the via opening (9) with a conductive material to form a plane and a via, wherein the plane has an uppermost surface at a same level as the first surface of the core (L2), figure 3.
As to claim 11, Morimoto discloses the plane region (9) is formed by exposing only the first surface of the core, and wherein the via region (W2, P2) is formed by exposing the first surface of the core and the second surface of the core (L2).
As to claim 15, Morimoto discloses a width of the plane (9 or R) is greater than a width of the via (V).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 5, 7-9, 12-14, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morimoto in view of Hibino et al. (U.S. 2012/0246924).
Regarding claims 2, 12, Morimoto discloses all of the limitations of claimed invention except for the recess or plane comprises tapered sidewalls.
Hibino teaches a multilayer printed circuit board (10) as shown in figures 2-7
comprising a glass core substrate (30) having the recess or plane (26a) comprises
tapered sidewalls.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Hibino employed in the electronic package of
Morimoto in order to provide excellent electrical bonding connections.
Regarding claims 3, 13-14, Morimoto discloses all of the limitations of claimed invention except for the via comprises tapered sidewalls or an hourglass shaped cross-section.
Hibino teaches a multilayer printed circuit board (10) as shown in figures 2-7
comprising a glass core substrate (30) having the via (26a) comprises tapered sidewalls
or an hourglass shaped cross-section.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Hibino employed in the electronic package of
Morimoto in order to ensure a reliable electrical connection between different layers of the PCB, particularly when there might be slight misalignment between layers due to
manufacturing tolerances, or to improve the electrical connection between different
layers of the board by providing a wider surface area for plating at the top and bottom of
the hole, while maintaining a smaller diameter in the middle to minimize the amount of
space taken up between layers; essentially optimizing signal transmission and reducing
potential for signal interference by minimizing the "stub" length of the via where the
signal transitions between layers.
Regarding claim 5, Morimoto discloses all of the limitations of claimed invention except for a surface metal over the recess on the first surface of the core; and a pad over the via on the first surface of the core.
Hibino teaches a multilayer printed circuit board (10) as shown in figures 2-7
comprising a glass core substrate (30) having a surface metal (52 or 158A) over the
recess (26 or 38A) on the first surface of the core; and a pad (56) over the via (36) on
the first surface of the core.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Hibino employed in the electronic package of
Morimoto in order to provide excellent electrical bonding connections.
Regarding claim 7, Morimoto discloses all of the limitations of claimed invention except for a plurality of recesses into the first surface of the core, wherein the plurality of recesses are substantially parallel to each other.
Hibino teaches the core (30) having a plurality of recesses (26 or 38A) into the first surface of the core, wherein the plurality of recesses (26 or 38A) are substantially parallel to each other, see figure 2E.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Hibino employed in the electronic package of
Morimoto in order to provide excellent electrical bonding connections.
Regarding claim 8, Morimoto discloses all of the limitations of claimed invention except for a second plurality of recesses into the second surface of the core, wherein the second plurality of recesses are interdigitated with the plurality of recesses.
Hibino teaches the core (30) having a second plurality of recesses (26b or 38B) into the second surface of the core, wherein the plurality of recesses (26b or 38B) are interdigitated with the plurality of recesses, see figure 2E.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Hibino employed in the electronic package of
Morimoto in order to provide excellent electrical bonding connections.
Regarding claim 9, Morimoto discloses all of the limitations of claimed invention except for the plurality of recesses are coupled together by a first metal layer on the first surface of the core, and wherein the second plurality of recesses are coupled together by a second metal layer on the second surface of the core.
Hibino teaches the core (30) having the plurality of recesses (38A) are coupled together by a first metal layer (34A) on the first surface of the core, and wherein the second plurality of recesses (38B) are coupled together by a second metal layer (34B) on the second surface of the core.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Hibino employed in the electronic package of
Morimoto in order to provide excellent electrical bonding connections.
Regarding claim 17, Morimoto discloses all of the limitations of claimed invention
except for the via is a high speed I/O via.
Hibino teaches the via (36) is a high speed I/O via.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Hibino employed in the electronic package of
Morimoto in order to provide excellent electrical bonding connections.
Regarding claims 18-19, Morimoto discloses all of the limitations of claimed invention except for a metal layer over the plane on the first surface of the core, and pads above and below the via.
Hibino teaches a multilayer printed circuit board (10) as shown in figures 2-7
comprising a glass core substrate (30) having a surface metal (52 or 158A) over the
recess (26 or 38A) on the first surface of the core; and pads (56) formed above and below the via (36) on.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Hibino employed in the electronic package of
Morimoto in order to provide excellent electrical bonding connections.
Claim(s) 6, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Morimoto in view of Won et al. (U.S. 2006/0157766).
Regarding claims 6 and 16, Morimoto discloses all of the limitations of claimed
invention except for the recess or plane extends past a midpoint of the core in a
thickness direction.
Won teaches a glass core (230, para-0070+) comprising the recess or plane (219) extends past a midpoint of the core (230) in a thickness direction.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Won employed in the electronic package of
Morimoto in order to provide excellent electrical bonding connections.
Claim(s) 20-21, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arai (‘470) in view of Morimoto (‘955).
As to claim 20, Arai discloses an electronic package (10) as shown in figures 2-12, comprising:
a core (11) with a first surface (11b) and a second surface (11a), wherein the
core is a glass substrate;
a first buildup layer (16, 18, 20) over the first surface of the core;
a second buildup layer (21, 23, 25) under the second surface of the core;
power delivery features (13, 14) embedded within a thickness of the core (11),
wherein the power delivery features (13, 14) comprise a plurality of conductive planes (ground/power planes, and wherein the metal power delivery features (13, 14) having an uppermost surface; and a via (15 or 11z) through a thickness of the core (11).
Arai does not specifically disclose the metal power delivery features having an uppermost surface at the same level as the first surface of the core.
Morimoto teaches the semiconductor device (para-0055) comprising a core (L2) having a metal power delivery feature (9, para-0061+) having an uppermost surface, figure 3, at the same level as the first surface of the core (L2).
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Morimoto employed in the electronic package of Arai in order to provide stabilizing potential power supply structures for the electronic package.
Regarding to claim 21, Arai as modified by Morimoto discloses the plurality of conductive planes (13, 14) extend into the first surface (11a) of the core, and wherein the plurality of conductive planes (13, 14) do not pass entirely through the thickness of the core.
As to claim 24, Arai discloses an electronic system as shown in figures 2-12,
comprising:
a board (mount board or motherboard, not illustrated, para-0059+);
a package substrate (10) coupled to the board (the electrode pads 24 are connected to the motherboard),
wherein the package substrate (10) comprises:
a core (11) with a first surface (11a) and a second surface (11b), wherein the core comprises glass (para-0002, 0029):
a first buildup layer (16, 18, 20) over the first surface of the core;
a second buildup layer (21, 23, 25) under the second surface of the core;
a via through (15) the core between the first surface of the core and the second surface of the core; and a plane (13 or 14) into the first surface of the core,
wherein a width of the plane (13 or 14) is greater than a width of the via (15), and
a die (semiconductor chip, para-0055, not illustrated) coupled to the package substrate (10).
Arai does not specifically disclose the plane has an uppermost surface at the same level as the first surface of the core.
Morimoto teaches the semiconductor device (para-0055) comprising a core (L2) having a plane (9, para-0061+) having an uppermost surface, figure 3, at the same level as the first surface of the core (L2).
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Morimoto employed in the electronic package of Arai in order to provide stabilizing potential power supply structures for the electronic package.
Claim(s) 22-23, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arai (‘470) in view of Morimoto (‘855), and further in view of Hibino (‘924)
Regarding claims 22 and 25, Arai as modified by Morimoto discloses all of the limitations of claimed invention except for the recess or plane comprises tapered sidewalls.
Hibino teaches a multilayer printed circuit board (10) as shown in figures 2-7
comprising a glass core substrate (30) having the recess or plane (26a) comprises
tapered sidewalls.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Hibino employed in the electronic package of
Arai and Morimoto in order to provide excellent electrical bonding connections.
Regarding claim 23, Arai as modified by Morimoto discloses all of the limitations of claimed invention except for the via comprises tapered sidewalls or an hourglass shaped cross-section.
Hibino teaches a multilayer printed circuit board (10) as shown in figures 2-7
comprising a glass core substrate (30) having the via (26a) comprises tapered sidewalls
or an hourglass shaped cross-section.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Hibino employed in the electronic package of
Arai and Morimoto in order to ensure a reliable electrical connection between different layers of the PCB, particularly when there might be slight misalignment between layers due to manufacturing tolerances, or to improve the electrical connection between different layers of the board by providing a wider surface area for plating at the top and bottom of the hole, while maintaining a smaller diameter in the middle to minimize the amount of space taken up between layers; essentially optimizing signal transmission and reducing potential for signal interference by minimizing the "stub" length of the via where the signal transitions between layers.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN T DINH whose telephone number is (571)272-1929. The examiner can normally be reached MON-FRI: 8AM-4:30PM.
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/TUAN T DINH/Primary Examiner, Art Unit 2848