Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant's arguments filed September 11th, 2025 have been fully considered but they are not persuasive.
As Applicant’s arguments are directed toward limitations of the independent claim which were added via amendment, they will be addressed in the rejections below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims are rejected under 35 U.S.C. 103 as being unpatentable over Smith (US 2023/0085143) in view of Raja (US 2021/0294607).
Regarding claim 1, Smith teaches an apparatus comprising:
a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction comprising fields to indicate a memory address that stores a capability comprising an address field, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an address space to which the capability authorizes access (Fig 2, [0065-0066], [0068], capability registers & associated fields including bounds and address pointer, constraint metadata to indicate validity and permissions, [0067], bounds embodied as lower and upper bounds for capability access), a single destination register, and an opcode to indicate that an execution circuit is to load a first proper subset of the address field and the bounds field of the capability from the memory address into the single destination register ([0065], capability registers [0074-0078], [0088-0091], instruction for memory access utilizing a destination register referencing capability register as a source);
the execution circuit to execute the decoded single instruction according to the opcode (Fig 1, [0060], execution stage 16); and
a capability management circuit to check a capability in the single destination register for a memory access request (Fig 2, [0065-0066], [0068], capability registers & associated fields including bounds and address pointer, constraint metadata to indicate validity and permissions).
Smith fails to teach wherein the instruction loads data into an implicit second destination register, wherein the implicit second destination register is for a memory access request.
Raja teaches an apparatus comprising a decoder circuit to decode a single instruction comprising an opcode to indicate that an execution circuit is to load a first proper subset of data into a destination register and a second proper subset of the data from a memory address into an implicit second destination register ([0088], decode stage & [0079], [0081], [0104], implicitly encoding a second destination register as a target of a load instruction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Smith and Raja to utilize a memory access instruction which implicitly targets multiple registers. While Smith does not explicitly disclose the possibility of memory access instructions having multiple destination register targets, both Smith and Raja disclose the use of instructions which may be decoded or split into multiple micro-operations (Raja [0088], Smith [0059]). Therefore, utilizing a load pair instruction to load data into multiple different destination registers as distinct micro-operations would allow the processor to move data to and from capability registers in fewer instructions, thus increasing the efficiency of the processor and reducing the overhead of address calculation and other operations on the load operations. As Raja also contemplates loading a variable number of destination registers beyond two (Raja [0081]), this would also allow for checking capabilities for a variable number of destination registers beyond the first. As this combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and would have been obvious to one of ordinary skill in the art.
Regarding claim 5, the combination of Smith and Raja teaches the apparatus of claim 1, wherein the capability comprises a permission field that is to indicate how the capability is permitted to be used (Smith [0066], permissions field).
Regarding claim 6, the combination of Smith and Raja teaches the apparatus of claim 1, wherein the capability comprises an object type field that is to indicate an object type of the capability (Smith [0042], [0068], types of access rights indicated by metadata).
Regarding claim 7, the combination of Smith and Raja teaches the apparatus of claim 1, wherein the opcode is to indicate that the execution circuit is to lock a memory comprising the memory address until the loads of both the first proper subset of the capability from the memory address into the single destination register, and the second proper subset of the capability from the memory address into the implicit second destination register are complete (Smith [0065], [0070], updates to memory locations following capability instructions may not be permitted).
Claims 9 and 13-15 refer to a method embodiment of the apparatus embodiment of claims 1 and 5-7, respectively. Therefore, the above rejection for claims 1 and 5-7 are applicable to claims 9 and 13-15, respectively.
Claims 17 and 21-23 refer to a medium embodiment of the apparatus embodiment of claims 1 and 5-7, respectively. Therefore, the above rejection for claims 1 and 5-7 are applicable to claims 17 and 21-23, respectively.
Allowable Subject Matter
3. Claims 2-4, 8, 10-12, 16, 18-20, and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Muller (US 2021/0109760) discloses a processor for performing memory operations using multiple implicit destination registers.
Plotnikov (US 2018/0246722) discloses a processor for performing memory operations on packed destination registers which may be addressed implicitly.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 7:30-4.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Caldwell can be reached at 571-272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183