DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "the thickness of the substrate" in the last line of the claim. There is insufficient antecedent basis for this limitation in the claim. It is recommended to replace it with “a thickness of the substrate.”
Claim 20 recites the limitation "the structure of the substrate" in the last line of the claim. There is insufficient antecedent basis for this limitation in the claim. It is recommended to replace it with “a structure of the substrate.”
Allowable Subject Matter
The indicated allowability of claims 8, 15 and 19 is withdrawn in view of the newly discovered reference(s) to Hsieh et al. (US 20210057561 A1). Rejections based on the newly cited reference(s) follow.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-6, 11-14, 17 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dasgupta et al. (US 2018/0145052 A1) in view of Hsieh et al. (US 20210057561 A1).
Regarding claim 19, Dasgupta et al. teach an epitaxy substrate (205/225 of 403; Figs. 4 and 5, [0030]), comprising: a substrate (205 of 403; Figs. 4 and 5, [0027]) having a first surface (the top surface of 205 in Fig. 4) and a second surface (the bottom surface of 205 in Fig. 4) opposite to each other, wherein the substrate (205) has a ring-shaped protrusion (the outmost portion of 205 surrounding 441s/442s, which can be annular shape; Figs. 4 and 5, [0042, 0044]) on an edge of the second surface (the bottom surface of 205 in Fig. 4); an aluminum nitride layer (225, which can be AlN as disclosed in [0030]; or 210, a portion of an embodiment of 225 as disclosed in [0031]; Figs. 4 and 2) located on the first surface of the substrate (the top surface of 205 in Figs. 4 and 2); and a buffer layer (215; Fig. 2, [0031]) located on the aluminum nitride layer (210; Fig. 2, [0031]), wherein a lattice of the buffer layer (215; [0029, 0031]) is between a lattice of the aluminum nitride layer (210; [0029, 0031]) and a lattice of a gallium nitride epitaxial layer (220; Fig. 2, [0029, 0031]).
Dasgupta et al. do not teach wherein the buffer layer comprises a superlattice material.
In the same field of endeavor of semiconductor manufacturing, Hsieh et al. teach wherein the buffer layer (130; Fig. 2, [0031]) comprises a superlattice material ([0031]).
Dasgupta et al. teach all the claimed elements except that Dasgupta et al. is using an AlGaN layer (215; Fig. 2, [0032]) for tuning wafer flatness ([0032]) rather than a superlattice material.
In the same field of endeavor of semiconductor manufacturing, Hsieh et al. teach using a superlattice material (130; Fig. 2, [0040]) for tuning wafer flatness (avoiding bows; [0040]).
One of ordinary skill in the art would have recognized that an AlGaN layer and a superlattice material are known equivalents for tuning wafer flatness within the semiconductor art.
It would have been obvious to one of ordinary skill in the art at the time of invention was made to substitute one know element (an AlGaN layer) for another known equivalent element (a superlattice material) resulting in the predictable result of tuning wafer flatness (KSR rationales B).
Regarding claim 2, Dasgupta et al. teach the epitaxy substrate according to claim 19, wherein a height of the ring-shaped protrusion (a height of the outmost portion of 205 surrounding 441s/442s protruding from the top surface of 441 in Fig. 4, i.e. the height/depth of 441; [0043]) is 10-3000 µm ([0043]), which overlaps the claimed range of between 10 µm and 200 µm, that establishes a prima facie case of obviousness (MPEP 2144.05).
Regarding claim 3, Dasgupta et al. teach the epitaxy substrate according to claim 19, wherein a width of the ring-shaped protrusion (the outmost portion of 205 surrounding 441s/442s; Figs. 4 and 5).
Dasgupta et al. do not teach a width of the ring-shaped protrusion is less than or equal to 5 mm (emphasis added).
Parameters such as the width of the ring-shaped protrusion, which would affect the mechanical strength of the ring-shaped protrusion, in the art of semiconductor manufacturing process are subject to routine experimentation and optimization to achieve the desired stress tuning process during device fabrication ([0041-0043]). Therefore, it would have been obvious to one of the ordinary skill in the art at the time the invention was made to incorporate the width of the ring-shaped protrusion within the range as claimed in order to achieve the desired stress tuning process ([0041-0043]).
Regarding claim 4, Dasgupta et al. teach the epitaxy substrate according to claim 19, wherein a thickness of the aluminum nitride layer (225; [0031]).
Dasgupta et al. do not teach a thickness of the aluminum nitride layer is between 1 nm and 100 nm (emphasis added).
Parameters such as the thickness of the aluminum nitride layer in the art of semiconductor manufacturing process are subject to routine experimentation and optimization to achieve the desired stress tuning process during device fabrication ([0025, 0031]). Therefore, it would have been obvious to one of the ordinary skill in the art at the time the invention was made to incorporate the thickness of the aluminum nitride layer within the range as claimed in order to achieve the desired stress tuning process ([0025, 0031]).
Regarding claim 5, Dasgupta et al. teach the epitaxy substrate according to claim 19, wherein the thickness of the substrate (205 of a silicon substrate; [0027]) is between 625µm and 1000µm (725 µm; [0002]).
Regarding claim 6, Dasgupta et al. teach the epitaxy substrate according to claim 19, wherein the substrate (205) comprises a silicon material (silicon; [0027]).
Regarding claim 11, Dasgupta et al. teach an epitaxial wafer structure (205/225/230 of 403 of Figs. 4 and 5 with an embodiment of 225 having 210/215/220 shown in [0031]; [0030, 0038]) comprising: an epitaxy substrate (205/225 of 403; Figs. 4 and 5, [0030]), comprising: a substrate (205 of 403; Figs. 4 and 5, [0027]) having a first surface (the top surface of 205 in Fig. 4) and a second surface (the bottom surface of 205 in Fig. 4) opposite to each other, wherein the substrate (205) has a ring-shaped protrusion (the outmost portion of 205 surrounding 441s/442s, which can be annular shape; Figs. 4 and 5, [0042, 0044]) on an edge of the second surface (the bottom surface of 205 in Fig. 4); and an aluminum nitride layer (210, a portion of an embodiment of 225 as disclosed in [0031]; Figs. 4 and 2) located on the first surface of the substrate (the top surface of 205 in Figs. 2 and 4); and a buffer layer (215; Fig. 2, [0031]) located on the aluminum nitride layer (210; Fig. 2, [0031]), wherein a lattice of the buffer layer (215; [0029, 0031]) is between a lattice of the aluminum nitride layer (210; [0029, 0031]) and a lattice of a gallium nitride epitaxial layer (220; Fig. 2, [0029, 0031]); and an epitaxial layer (220; Fig. 2, [0029, 0031]) located on the buffer layer (215; see Fig. 2).
Dasgupta et al. do not teach wherein the buffer layer comprises a superlattice material.
In the same field of endeavor of semiconductor manufacturing, Hsieh et al. teach wherein the buffer layer (130; Fig. 2, [0031]) comprises a superlattice material ([0031]).
Dasgupta et al. teach all the claimed elements except that Dasgupta et al. is using an AlGaN layer (215; Fig. 2, [0032]) for tuning wafer flatness ([0032]) rather than a superlattice material.
In the same field of endeavor of semiconductor manufacturing, Hsieh et al. teach using a superlattice material (130; Fig. 2, [0040]) for tuning wafer flatness (avoiding bows; [0040]).
One of ordinary skill in the art would have recognized that an AlGaN layer and a superlattice material are known equivalents for tuning wafer flatness within the semiconductor art.
It would have been obvious to one of ordinary skill in the art at the time of invention was made to substitute one know element (an AlGaN layer) for another known equivalent element (a superlattice material) resulting in the predictable result of tuning wafer flatness (KSR rationales B).
Regarding claim 12, Dasgupta et al. teach the epitaxial wafer structure according to claim 11, wherein: a height of the ring-shaped protrusion is between 10 µm and 200 µm; a width of the ring-shaped protrusion is less than or equal to 5 mm; a thickness of the aluminum nitride layer is between 1 nm and 100 nm; or (Dasgupta et al. teach the last option) the thickness of the substrate (205 of a silicon substrate; [0027]) is between 625 µm and 1000µm (725 µm; [0002]).
Regarding claim 13, Dasgupta et al. teach the epitaxial wafer structure according to claim 11, wherein the substrate (205) comprises a silicon material (silicon; [0027]).
Regarding claim 14, Dasgupta et al. teach the epitaxial wafer structure according to claim 11, wherein the aluminum nitride layer (210) and the epitaxial layer (220) directly contact two opposite sides of the buffer layer (215; see Fig. 2), and wherein the epitaxial layer (220) is a gallium nitride epitaxial layer ([0029, 0031]).
Regarding claim 17, Dasgupta et al. teach the epitaxial wafer structure according to claim 11, wherein a bow of the epitaxy substrate (205/225) containing the substrate (205) and the aluminum nitride layer (210) and the epitaxial layer (220, i.e. the bow after the III-N material layers 225 growth; [0029-0031, 0024]) is between -30µm and 30µm ([0024]).
Regarding claim 20, Dasgupta et al. teach the epitaxy substrate according to claim 19, wherein the structure of the substrate (205 of 403) consists of a first portion (sections of 205 having a smaller vertical thickness; see Fig. 4 below) and a second portion (sections of 205 having a larger vertical thickness; see Fig. 4 below), the second portion (sections of 205 having a larger vertical thickness; see Fig. 4 below) surrounds the first portion (sections of 205 having a smaller vertical thickness; see Fig. 4 below) and corresponds to the ring-shaped protrusion (the outmost portion of 205 surrounding 441s/442s), and maximum thickness of the substrate (maximum thickness of 205) only corresponds to the second portion (sections of 205 having a larger vertical thickness; see Fig. 4 below).
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[AltContent: textbox (First portion)][AltContent: textbox (Second portion)][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow]
A portion of Fig 4 of Dasgupta et al. showing a first portion and the second portion of 205
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dasgupta et al. and Hsieh et al. as applied to claim 11 above, and further in view of Sie et al. (US 2021/0336058 A1).
Regarding claim 16, Dasgupta et al. teach the epitaxial wafer structure according to claim 11, wherein: the epitaxial layer (220).
Dasgupta et al. do not teach a uniformity of film thickness of the epitaxial layer is less than 3%; or a crack of the epitaxial layer is less than 3 mm.
In the same field of endeavor of semiconductor manufacturing, Sie et al. teach a crack of the epitaxial layer (E; [0067]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Dasgupta et al., Hsieh et al. and Sie et al. and to shorten the crack length of the epitaxial layer as taught by Sie et al. ([0067]), because it can prevent the plastic deformation or cracking of a chip as taught by Sie et al. ([0067]).
Sie et al. do not teach a crack of the epitaxial layer is less than 3 mm (emphasis added).
Parameters such as the crack length of the epitaxial layer in the art of semiconductor manufacturing process are subject to routine experimentation and optimization to prevent the plastic deformation or cracking of a chip during device fabrication ([0067] of Sie et al.). Therefore, it would have been obvious to one of the ordinary skill in the art at the time the invention was made to incorporate the crack length of the epitaxial layer within the range as claimed in order to prevent the plastic deformation or cracking of a chip ([0067] of Sie et al.).
Response to Arguments
Applicant's arguments with respect to claims 11 and 19 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Unannounced inventor (CN 112687772 A) teaches etching a ring at the edge of wafer to improve the performance of the light emitting diode.
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/HSIN YI HSIEH/Primary Examiner, Art Unit 2899 12/22/2025